Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 1 | config SOC_INTEL_ALDERLAKE |
| 2 | bool |
| 3 | help |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 4 | Intel Alderlake support. Mainboards should specify the PCH |
| 5 | type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead |
| 6 | of selecting this option directly. |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 7 | |
Bora Guvendik | 2c805b9 | 2022-06-08 15:55:52 -0700 | [diff] [blame] | 8 | config SOC_INTEL_RAPTORLAKE |
| 9 | bool |
Subrata Banik | 6526e78 | 2022-10-26 20:06:42 +0530 | [diff] [blame] | 10 | select X86_INIT_NEED_1_SIPI |
Bora Guvendik | 2c805b9 | 2022-06-08 15:55:52 -0700 | [diff] [blame] | 11 | help |
| 12 | Intel Raptorlake support. Mainboards using RPL should select |
| 13 | SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together. |
| 14 | |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 15 | config SOC_INTEL_ALDERLAKE_PCH_M |
| 16 | bool |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 17 | select SOC_INTEL_ALDERLAKE |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 18 | help |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 19 | Choose this option if your mainboard has a PCH-M chipset. |
| 20 | |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 21 | config SOC_INTEL_ALDERLAKE_PCH_N |
| 22 | bool |
| 23 | select SOC_INTEL_ALDERLAKE |
Michał Żygowski | 6297df8 | 2022-06-30 16:22:35 +0200 | [diff] [blame] | 24 | select MICROCODE_BLOB_UNDISCLOSED |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 25 | help |
| 26 | Choose this option if your mainboard has a PCH-N chipset. |
| 27 | |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 28 | config SOC_INTEL_ALDERLAKE_PCH_P |
| 29 | bool |
| 30 | select SOC_INTEL_ALDERLAKE |
Michał Żygowski | 073779b | 2022-06-29 11:32:01 +0200 | [diff] [blame] | 31 | select HAVE_INTEL_FSP_REPO |
| 32 | select PLATFORM_USES_FSP2_3 |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 33 | help |
| 34 | Choose this option if your mainboard has a PCH-P chipset. |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 35 | |
Michał Żygowski | a1636d7 | 2022-04-07 14:56:10 +0200 | [diff] [blame] | 36 | config SOC_INTEL_ALDERLAKE_PCH_S |
| 37 | bool |
| 38 | select SOC_INTEL_ALDERLAKE |
Michał Żygowski | 073779b | 2022-06-29 11:32:01 +0200 | [diff] [blame] | 39 | select HAVE_INTEL_FSP_REPO |
| 40 | select PLATFORM_USES_FSP2_3 |
Michał Żygowski | a1636d7 | 2022-04-07 14:56:10 +0200 | [diff] [blame] | 41 | help |
| 42 | Choose this option if your mainboard has a PCH-S chipset. |
| 43 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 44 | if SOC_INTEL_ALDERLAKE |
| 45 | |
| 46 | config CPU_SPECIFIC_OPTIONS |
| 47 | def_bool y |
Angel Pons | a25eaff | 2020-09-23 15:37:15 +0200 | [diff] [blame] | 48 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Sugnan Prabhu S | dcf0459 | 2021-12-03 19:07:04 +0530 | [diff] [blame] | 49 | select ACPI_ADL_IPU_ES_SUPPORT |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 50 | select ARCH_X86 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 51 | select BOOT_DEVICE_SUPPORTS_WRITES |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 52 | select CACHE_MRC_SETTINGS |
| 53 | select CPU_INTEL_COMMON |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 54 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | 5307f12 | 2021-09-19 00:32:37 +0200 | [diff] [blame] | 55 | select CPU_SUPPORTS_INTEL_TME |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 56 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Matt DeVillier | decbf7b | 2023-01-18 18:58:38 -0600 | [diff] [blame] | 57 | select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 58 | select DISPLAY_FSP_VERSION_INFO |
Eric Lai | 4ea47c3 | 2020-12-21 16:57:49 +0800 | [diff] [blame] | 59 | select DRIVERS_USB_ACPI |
Sean Rhodes | 7bbc9a5 | 2022-07-18 11:31:00 +0100 | [diff] [blame] | 60 | select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 61 | select FSP_COMPRESS_FSP_S_LZ4 |
Subrata Banik | 683c95e | 2020-12-19 19:36:45 +0530 | [diff] [blame] | 62 | select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 63 | select FSP_M_XIP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 64 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Subrata Banik | e4cf3fa | 2022-03-23 01:41:36 +0530 | [diff] [blame] | 65 | select FSP_USES_CB_DEBUG_EVENT_HANDLER |
Subrata Banik | 298b359 | 2021-09-14 12:38:08 +0530 | [diff] [blame] | 66 | select FSPS_HAS_ARCH_UPD |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 67 | select GENERIC_GPIO_LIB |
Subrata Banik | b4a169a | 2021-12-29 18:36:23 +0000 | [diff] [blame] | 68 | select HAVE_DEBUG_RAM_SETUP |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 69 | select HAVE_FSP_GOP |
Felix Singer | a182fae | 2021-12-31 00:30:55 +0100 | [diff] [blame] | 70 | select HAVE_HYPERTHREADING |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 71 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 72 | select HAVE_SMI_HANDLER |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 73 | select IDT_IN_EVERY_STAGE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 74 | select INTEL_GMA_ACPI |
| 75 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Meera Ravindranath | 81d367f | 2021-07-08 09:39:11 +0530 | [diff] [blame] | 76 | select INTEL_GMA_OPREGION_2_1 |
Subrata Banik | c8b840f | 2022-12-31 14:47:55 +0530 | [diff] [blame] | 77 | select INTEL_TXT_LIB |
Subrata Banik | a247319 | 2023-02-22 13:03:04 +0000 | [diff] [blame] | 78 | select MP_SERVICES_PPI_V2 |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 79 | select MRC_SETTINGS_PROTECT |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 80 | select PARALLEL_MP_AP_WORK |
Michał Żygowski | 073779b | 2022-06-29 11:32:01 +0200 | [diff] [blame] | 81 | select PLATFORM_USES_FSP2_2 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 82 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 83 | select SOC_INTEL_COMMON |
Zhixing Ma | 30e8fc1 | 2022-09-30 14:18:13 -0700 | [diff] [blame] | 84 | select CPU_INTEL_COMMON_VOLTAGE |
Subrata Banik | 0808992 | 2020-10-03 13:02:06 +0530 | [diff] [blame] | 85 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Lean Sheng Tan | ce68d68 | 2023-03-15 15:32:01 +0100 | [diff] [blame] | 86 | select SOC_INTEL_COMMON_BASECODE |
| 87 | select SOC_INTEL_COMMON_BASECODE_RAMTOP |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 88 | select SOC_INTEL_COMMON_BLOCK |
Subrata Banik | 0808992 | 2020-10-03 13:02:06 +0530 | [diff] [blame] | 89 | select SOC_INTEL_COMMON_BLOCK_ACPI |
ravindr1 | 7459657 | 2021-03-29 19:41:25 +0530 | [diff] [blame] | 90 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC |
Sridahr Siricilla | 73b90c6 | 2021-11-11 01:10:16 +0530 | [diff] [blame] | 91 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID |
Angel Pons | 98f672a | 2021-02-19 19:42:10 +0100 | [diff] [blame] | 92 | select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
Jeremy Soller | 5219ee1 | 2022-05-26 09:02:13 -0600 | [diff] [blame] | 93 | select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT |
Tim Wawrzynczak | 5faee2e | 2021-07-01 08:24:18 -0600 | [diff] [blame] | 94 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP |
| 95 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ |
Subrata Banik | 21974ab | 2020-10-31 21:40:43 +0530 | [diff] [blame] | 96 | select SOC_INTEL_COMMON_BLOCK_CAR |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 97 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Varshit B Pandya | 2938c46 | 2022-02-16 20:38:10 +0530 | [diff] [blame] | 98 | select SOC_INTEL_COMMON_BLOCK_CNVI |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 99 | select SOC_INTEL_COMMON_BLOCK_CPU |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 100 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Angel Pons | a4cd911 | 2021-02-19 19:23:38 +0100 | [diff] [blame] | 101 | select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 102 | select SOC_INTEL_COMMON_BLOCK_DTT |
| 103 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Subrata Banik | af2f8b9 | 2022-01-10 10:26:52 +0000 | [diff] [blame] | 104 | select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 105 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
Krishna Prasad Bhat | 01e426d | 2022-01-16 22:37:21 +0530 | [diff] [blame] | 106 | select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 107 | select SOC_INTEL_COMMON_BLOCK_HDA |
Subrata Banik | c176fc2 | 2022-04-25 16:59:35 +0530 | [diff] [blame] | 108 | select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC |
Michał Żygowski | 3d1e562 | 2022-04-08 17:09:49 +0200 | [diff] [blame] | 109 | select SOC_INTEL_COMMON_BLOCK_IPU if !SOC_INTEL_ALDERLAKE_PCH_S |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 110 | select SOC_INTEL_COMMON_BLOCK_IRQ |
Dinesh Gehlot | 930fded | 2023-02-24 05:09:04 +0000 | [diff] [blame] | 111 | select SOC_INTEL_COMMON_BLOCK_ME_SPEC_16 |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 112 | select SOC_INTEL_COMMON_BLOCK_MEMINIT |
Rizwan Qureshi | 307be99 | 2021-04-08 20:35:29 +0530 | [diff] [blame] | 113 | select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 |
Lean Sheng Tan | 7502000 | 2021-06-30 01:47:48 -0700 | [diff] [blame] | 114 | select SOC_INTEL_COMMON_BLOCK_PMC_EPOC |
Sumeet R Pawnikar | 77298c6 | 2021-03-10 21:09:37 +0530 | [diff] [blame] | 115 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 116 | select SOC_INTEL_COMMON_BLOCK_SA |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 117 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 118 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | b2e8bd8 | 2021-11-17 15:35:05 +0530 | [diff] [blame] | 119 | select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC |
Michał Żygowski | 5f05ee2 | 2023-01-18 12:18:00 +0100 | [diff] [blame] | 120 | select SOC_INTEL_COMMON_BLOCK_VTD |
Tim Wawrzynczak | 242da79 | 2020-11-10 10:13:54 -0700 | [diff] [blame] | 121 | select SOC_INTEL_COMMON_BLOCK_XHCI |
| 122 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 123 | select SOC_INTEL_COMMON_FSP_RESET |
Angel Pons | eb90c51 | 2022-07-18 14:41:24 +0200 | [diff] [blame] | 124 | select SOC_INTEL_COMMON_PCH_CLIENT |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 125 | select SOC_INTEL_COMMON_RESET |
Jeremy Compostella | c49efa3 | 2023-03-13 10:55:21 -0700 | [diff] [blame] | 126 | select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 127 | select SOC_INTEL_CSE_SET_EOP |
Subrata Banik | af27ac2 | 2022-02-18 00:44:15 +0530 | [diff] [blame] | 128 | select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION |
Sridahr Siricilla | 096ce14 | 2021-09-17 22:25:17 +0530 | [diff] [blame] | 129 | select HAVE_INTEL_COMPLIANCE_TEST_MODE |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 130 | select SSE2 |
| 131 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 132 | select TSC_MONOTONIC_TIMER |
| 133 | select UDELAY_TSC |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 134 | select UDK_202005_BINDING |
Michał Żygowski | 9b0f169 | 2022-05-05 13:21:01 +0200 | [diff] [blame] | 135 | select VBOOT_LIB |
Lean Sheng Tan | 8615245 | 2023-03-13 14:51:10 +0100 | [diff] [blame] | 136 | select X86_CLFLUSH_CAR |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 137 | |
Michał Żygowski | 9df95d9 | 2022-04-08 17:02:35 +0200 | [diff] [blame] | 138 | config SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT |
| 139 | bool |
| 140 | default y if !SOC_INTEL_ALDERLAKE_PCH_S |
| 141 | default n if SOC_INTEL_ALDERLAKE_PCH_S |
| 142 | select SOC_INTEL_COMMON_BLOCK_TCSS |
| 143 | select SOC_INTEL_COMMON_BLOCK_USB4 |
| 144 | select SOC_INTEL_COMMON_BLOCK_USB4_PCIE |
| 145 | select SOC_INTEL_COMMON_BLOCK_USB4_XHCI |
| 146 | |
Reka Norman | e790f92 | 2022-04-06 20:33:54 +1000 | [diff] [blame] | 147 | config ALDERLAKE_CONFIGURE_DESCRIPTOR |
| 148 | bool |
| 149 | help |
| 150 | Select this if the descriptor needs to be updated at runtime. This |
| 151 | can only be done if the descriptor region is writable, and should only |
| 152 | be used as a temporary workaround. |
| 153 | |
Subrata Banik | 095e2a7 | 2021-07-05 20:56:15 +0530 | [diff] [blame] | 154 | config ALDERLAKE_CAR_ENHANCED_NEM |
| 155 | bool |
| 156 | default y if !INTEL_CAR_NEM |
| 157 | select INTEL_CAR_NEM_ENHANCED |
| 158 | select CAR_HAS_SF_MASKS |
| 159 | select COS_MAPPED_TO_MSB |
| 160 | select CAR_HAS_L3_PROTECTED_WAYS |
| 161 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 162 | config MAX_CPUS |
| 163 | int |
Tim Crawford | 35860ff | 2023-03-06 11:28:40 -0700 | [diff] [blame] | 164 | default 32 if SOC_INTEL_RAPTORLAKE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 165 | default 24 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 166 | |
| 167 | config DCACHE_RAM_BASE |
| 168 | default 0xfef00000 |
| 169 | |
| 170 | config DCACHE_RAM_SIZE |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 171 | default 0xc0000 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 172 | help |
| 173 | The size of the cache-as-ram region required during bootblock |
| 174 | and/or romstage. |
| 175 | |
| 176 | config DCACHE_BSP_STACK_SIZE |
| 177 | hex |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 178 | default 0x80400 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 179 | help |
| 180 | The amount of anticipated stack usage in CAR by bootblock and |
| 181 | other stages. In the case of FSP_USES_CB_STACK default value will be |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 182 | sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 183 | (~1KiB). |
| 184 | |
| 185 | config FSP_TEMP_RAM_SIZE |
| 186 | hex |
| 187 | default 0x20000 |
| 188 | help |
| 189 | The amount of anticipated heap usage in CAR by FSP. |
| 190 | Refer to Platform FSP integration guide document to know |
| 191 | the exact FSP requirement for Heap setup. |
| 192 | |
Tim Wawrzynczak | 092813a | 2020-11-24 13:48:56 -0700 | [diff] [blame] | 193 | config CHIPSET_DEVICETREE |
| 194 | string |
Michał Kopeć | 75a49fe | 2022-04-08 11:28:45 +0200 | [diff] [blame] | 195 | default "soc/intel/alderlake/chipset_pch_s.cb" if SOC_INTEL_ALDERLAKE_PCH_S |
Tim Wawrzynczak | 092813a | 2020-11-24 13:48:56 -0700 | [diff] [blame] | 196 | default "soc/intel/alderlake/chipset.cb" |
| 197 | |
Subrata Banik | 683c95e | 2020-12-19 19:36:45 +0530 | [diff] [blame] | 198 | config EXT_BIOS_WIN_BASE |
| 199 | default 0xf8000000 |
| 200 | |
| 201 | config EXT_BIOS_WIN_SIZE |
| 202 | default 0x2000000 |
| 203 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 204 | config IFD_CHIPSET |
| 205 | string |
| 206 | default "adl" |
| 207 | |
| 208 | config IED_REGION_SIZE |
| 209 | hex |
| 210 | default 0x400000 |
| 211 | |
| 212 | config HEAP_SIZE |
| 213 | hex |
| 214 | default 0x10000 |
| 215 | |
Jeremy Compostella | 9df1197 | 2022-12-02 10:59:49 -0700 | [diff] [blame] | 216 | config GFX_GMA_DEFAULT_MMIO |
Jeremy Compostella | 0ad4003 | 2023-01-30 14:18:21 -0700 | [diff] [blame] | 217 | default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT |
Jeremy Compostella | 9df1197 | 2022-12-02 10:59:49 -0700 | [diff] [blame] | 218 | |
Tim Wawrzynczak | 8d11cdc | 2021-03-12 12:46:02 -0700 | [diff] [blame] | 219 | # Intel recommends reserving the following resources per PCIe TBT root port, |
| 220 | # from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5 |
| 221 | # - 42 buses |
| 222 | # - 194 MiB Non-prefetchable memory |
| 223 | # - 448 MiB Prefetchable memory |
Furquan Shaikh | d9f5d90 | 2021-08-24 13:53:43 -0700 | [diff] [blame] | 224 | if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
Tim Wawrzynczak | 8d11cdc | 2021-03-12 12:46:02 -0700 | [diff] [blame] | 225 | |
| 226 | config PCIEXP_HOTPLUG_BUSES |
| 227 | int |
| 228 | default 42 |
| 229 | |
| 230 | config PCIEXP_HOTPLUG_MEM |
| 231 | hex |
| 232 | default 0xc200000 |
| 233 | |
| 234 | config PCIEXP_HOTPLUG_PREFETCH_MEM |
| 235 | hex |
| 236 | default 0x1c000000 |
| 237 | |
Furquan Shaikh | d9f5d90 | 2021-08-24 13:53:43 -0700 | [diff] [blame] | 238 | endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
Tim Wawrzynczak | 8d11cdc | 2021-03-12 12:46:02 -0700 | [diff] [blame] | 239 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 240 | config MAX_PCH_ROOT_PORTS |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 241 | int |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 242 | default 10 if SOC_INTEL_ALDERLAKE_PCH_M |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 243 | default 12 if SOC_INTEL_ALDERLAKE_PCH_N |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 244 | default 12 if SOC_INTEL_ALDERLAKE_PCH_P |
Michał Żygowski | 27fdfc6 | 2022-04-07 15:03:09 +0200 | [diff] [blame] | 245 | default 28 if SOC_INTEL_ALDERLAKE_PCH_S |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 246 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 247 | config MAX_CPU_ROOT_PORTS |
| 248 | int |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 249 | default 1 if SOC_INTEL_ALDERLAKE_PCH_M |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 250 | default 0 if SOC_INTEL_ALDERLAKE_PCH_N |
Michał Żygowski | 27fdfc6 | 2022-04-07 15:03:09 +0200 | [diff] [blame] | 251 | default 3 if SOC_INTEL_ALDERLAKE_PCH_P || SOC_INTEL_ALDERLAKE_PCH_S |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 252 | |
MAULIK V VAGHELA | 3e4f28f | 2022-01-21 14:17:53 +0530 | [diff] [blame] | 253 | config MAX_TBT_ROOT_PORTS |
| 254 | int |
Michał Żygowski | 27fdfc6 | 2022-04-07 15:03:09 +0200 | [diff] [blame] | 255 | default 0 if SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_ALDERLAKE_PCH_S |
MAULIK V VAGHELA | 3e4f28f | 2022-01-21 14:17:53 +0530 | [diff] [blame] | 256 | default 2 if SOC_INTEL_ALDERLAKE_PCH_M |
| 257 | default 4 if SOC_INTEL_ALDERLAKE_PCH_P |
| 258 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 259 | config MAX_ROOT_PORTS |
| 260 | int |
| 261 | default MAX_PCH_ROOT_PORTS |
| 262 | |
Subrata Banik | cffc938 | 2021-01-29 18:41:35 +0530 | [diff] [blame] | 263 | config MAX_PCIE_CLOCK_SRC |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 264 | int |
Subrata Banik | cffc938 | 2021-01-29 18:41:35 +0530 | [diff] [blame] | 265 | default 6 if SOC_INTEL_ALDERLAKE_PCH_M |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 266 | default 5 if SOC_INTEL_ALDERLAKE_PCH_N |
Cliff Huang | 0d590b7 | 2022-04-28 18:20:27 -0700 | [diff] [blame] | 267 | default 10 if SOC_INTEL_ALDERLAKE_PCH_P |
Angel Pons | 122e1df | 2022-12-09 12:32:12 +0100 | [diff] [blame] | 268 | default 18 if SOC_INTEL_ALDERLAKE_PCH_S |
Cliff Huang | 0d590b7 | 2022-04-28 18:20:27 -0700 | [diff] [blame] | 269 | help |
| 270 | With external clock buffer, Alderlake-P can support up to three additional source clocks. |
| 271 | This is done by setting the corresponding GPIO pin(s) to native function to use as |
| 272 | SRCCLK_OE[6..9]. In addition, SRCCLK6 does not need to be set to free running clock. |
| 273 | If any of SRCCLKReq 6..9 is asserted, SRCCLK6 will be turned on. |
Subrata Banik | cffc938 | 2021-01-29 18:41:35 +0530 | [diff] [blame] | 274 | |
| 275 | config MAX_PCIE_CLOCK_REQ |
| 276 | int |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 277 | default 6 if SOC_INTEL_ALDERLAKE_PCH_M |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 278 | default 5 if SOC_INTEL_ALDERLAKE_PCH_N |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 279 | default 10 if SOC_INTEL_ALDERLAKE_PCH_P |
Michał Żygowski | 27fdfc6 | 2022-04-07 15:03:09 +0200 | [diff] [blame] | 280 | default 18 if SOC_INTEL_ALDERLAKE_PCH_S |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 281 | |
| 282 | config SMM_TSEG_SIZE |
| 283 | hex |
| 284 | default 0x800000 |
| 285 | |
| 286 | config SMM_RESERVED_SIZE |
| 287 | hex |
| 288 | default 0x200000 |
| 289 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 290 | config PCR_BASE_ADDRESS |
| 291 | hex |
Michał Żygowski | dccfb8a | 2022-04-07 15:09:19 +0200 | [diff] [blame] | 292 | default 0xe0000000 if SOC_INTEL_ALDERLAKE_PCH_S |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 293 | default 0xfd000000 |
| 294 | help |
| 295 | This option allows you to select MMIO Base Address of sideband bus. |
| 296 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 297 | config ECAM_MMCONF_BASE_ADDRESS |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 298 | default 0xc0000000 |
| 299 | |
| 300 | config CPU_BCLK_MHZ |
| 301 | int |
| 302 | default 100 |
| 303 | |
Sridhar Siricilla | d9c8269 | 2023-01-05 17:08:17 +0530 | [diff] [blame] | 304 | config SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR |
| 305 | int |
| 306 | default 127 |
| 307 | |
| 308 | config SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR |
| 309 | int |
| 310 | default 100 |
| 311 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 312 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 313 | int |
| 314 | default 120 |
| 315 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 316 | config CPU_XTAL_HZ |
| 317 | default 38400000 |
| 318 | |
Meera Ravindranath | d307d0d | 2022-07-21 20:45:32 +0530 | [diff] [blame] | 319 | config SOC_INTEL_UFS_CLK_FREQ_HZ |
| 320 | int |
| 321 | default 19200000 |
| 322 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 323 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 324 | int |
| 325 | default 133 |
| 326 | |
| 327 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 328 | int |
| 329 | default 7 |
| 330 | |
| 331 | config SOC_INTEL_I2C_DEV_MAX |
| 332 | int |
Varshit B Pandya | 339f0e7 | 2021-07-14 11:08:23 +0530 | [diff] [blame] | 333 | default 8 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 334 | |
Lean Sheng Tan | 1ec8f97 | 2022-09-07 16:07:33 +0200 | [diff] [blame] | 335 | config ENABLE_SATA_TEST_MODE |
| 336 | bool "Enable test mode for SATA margining" |
| 337 | default n |
| 338 | help |
| 339 | Enable SATA test mode in FSP-S. |
| 340 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 341 | config SOC_INTEL_UART_DEV_MAX |
| 342 | int |
| 343 | default 7 |
| 344 | |
| 345 | config CONSOLE_UART_BASE_ADDRESS |
| 346 | hex |
Bora Guvendik | 2a70419 | 2020-11-16 11:23:48 -0800 | [diff] [blame] | 347 | default 0xfe03e000 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 348 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 349 | |
Maulik V Vaghela | 996bab4 | 2021-02-05 12:03:19 +0530 | [diff] [blame] | 350 | config VBT_DATA_SIZE_KB |
| 351 | int |
| 352 | default 9 |
| 353 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 354 | # Clock divider parameters for 115200 baud rate |
Angel Pons | 054ff5e | 2022-06-26 10:19:53 +0200 | [diff] [blame] | 355 | # Baudrate = (UART source clock * M) /(N *16) |
Wonkyu Kim | 60d9b89 | 2022-10-10 23:01:38 -0700 | [diff] [blame] | 356 | # ADL UART source clock: 100MHz |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 357 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 358 | hex |
| 359 | default 0x25a |
| 360 | |
| 361 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 362 | hex |
| 363 | default 0x7fff |
| 364 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 365 | config VBOOT |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 366 | select VBOOT_MUST_REQUEST_DISPLAY |
| 367 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 368 | select VBOOT_VBNV_CMOS |
| 369 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Subrata Banik | 3423786 | 2021-06-17 23:36:02 +0530 | [diff] [blame] | 370 | select VBOOT_X86_SHA256_ACCELERATION |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 371 | |
MAULIK V VAGHELA | 84532da | 2021-08-25 16:41:23 +0530 | [diff] [blame] | 372 | # Default hash block size is 1KiB. Increasing it to 4KiB to improve |
| 373 | # hashing time as well as read time. This helps in improving |
| 374 | # boot time for Alder Lake. |
| 375 | config VBOOT_HASH_BLOCK_SIZE |
| 376 | hex |
| 377 | default 0x1000 |
| 378 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 379 | config CBFS_SIZE |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 380 | default 0x200000 |
| 381 | |
| 382 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 383 | hex |
Tarun Tuli | d244790 | 2023-01-24 13:31:10 +0000 | [diff] [blame] | 384 | default 0x16000 if CONSOLE_SERIAL |
Tarun Tuli | 2b03894 | 2023-01-24 13:50:17 +0000 | [diff] [blame] | 385 | default 0x4000 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 386 | |
Tarun Tuli | df74d9b | 2023-01-24 13:28:06 +0000 | [diff] [blame] | 387 | config CONSOLE_CBMEM_BUFFER_SIZE |
| 388 | hex |
Tarun Tuli | d244790 | 2023-01-24 13:31:10 +0000 | [diff] [blame] | 389 | default 0x100000 if CONSOLE_SERIAL |
Tarun Tuli | df74d9b | 2023-01-24 13:28:06 +0000 | [diff] [blame] | 390 | default 0x40000 |
| 391 | |
Lean Sheng Tan | bbd72d2 | 2022-08-02 12:29:42 +0200 | [diff] [blame] | 392 | config FSP_TYPE_IOT |
| 393 | bool |
| 394 | default n |
| 395 | help |
| 396 | This option allows to select FSP IOT type from 3rdparty/fsp repo |
| 397 | |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 398 | config FSP_HEADER_PATH |
| 399 | string "Location of FSP headers" |
Ronak Kanabar | ecdc714 | 2022-02-02 16:12:00 +0530 | [diff] [blame] | 400 | default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N |
Bora Guvendik | 2c805b9 | 2022-06-08 15:55:52 -0700 | [diff] [blame] | 401 | default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE |
Lean Sheng Tan | bbd72d2 | 2022-08-02 12:29:42 +0200 | [diff] [blame] | 402 | default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT |
| 403 | default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT |
Michał Żygowski | 073779b | 2022-06-29 11:32:01 +0200 | [diff] [blame] | 404 | default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P |
| 405 | default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 406 | default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" |
| 407 | |
| 408 | config FSP_FD_PATH |
| 409 | string |
| 410 | depends on FSP_USE_REPO |
Lean Sheng Tan | bbd72d2 | 2022-08-02 12:29:42 +0200 | [diff] [blame] | 411 | default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT |
| 412 | default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT |
Michał Żygowski | 073779b | 2022-06-29 11:32:01 +0200 | [diff] [blame] | 413 | default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P |
| 414 | default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 415 | |
| 416 | config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT |
| 417 | int "Debug Consent for ADL" |
Subrata Banik | 0cd553b | 2021-12-29 08:09:37 +0000 | [diff] [blame] | 418 | # USB DBC is more common for developers so make this default to 2 if |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 419 | # SOC_INTEL_DEBUG_CONSENT=y |
Kane Chen | 0e9a616 | 2021-11-23 14:42:48 +0800 | [diff] [blame] | 420 | default 2 if SOC_INTEL_DEBUG_CONSENT |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 421 | default 0 |
| 422 | help |
| 423 | This is to control debug interface on SOC. |
| 424 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 425 | PlatformDebugConsent in FspmUpd.h has the details. |
| 426 | |
| 427 | Desired platform debug type are |
Kane Chen | 0e9a616 | 2021-11-23 14:42:48 +0800 | [diff] [blame] | 428 | 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), |
| 429 | 7:Manual |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 430 | |
| 431 | config DATA_BUS_WIDTH |
| 432 | int |
| 433 | default 128 |
| 434 | |
| 435 | config DIMMS_PER_CHANNEL |
| 436 | int |
| 437 | default 2 |
| 438 | |
| 439 | config MRC_CHANNEL_WIDTH |
| 440 | int |
| 441 | default 16 |
| 442 | |
Sugnan Prabhu S | dcf0459 | 2021-12-03 19:07:04 +0530 | [diff] [blame] | 443 | config ACPI_ADL_IPU_ES_SUPPORT |
| 444 | def_bool n |
| 445 | help |
| 446 | Enables ACPI entry to provide silicon type information to IPU kernel driver. |
| 447 | |
Subrata Banik | a00db94 | 2022-10-12 14:24:41 +0530 | [diff] [blame] | 448 | config ALDERLAKE_ENABLE_SOC_WORKAROUND |
| 449 | bool |
| 450 | default y |
Meera Ravindranath | 9e4488a | 2022-10-10 10:48:18 +0530 | [diff] [blame] | 451 | select SOC_INTEL_UFS_LTR_DISQUALIFY |
Subrata Banik | a00db94 | 2022-10-12 14:24:41 +0530 | [diff] [blame] | 452 | select SOC_INTEL_UFS_OCP_TIMER_DISABLE |
| 453 | help |
| 454 | Selects the workarounds applicable for Alder Lake SoC. |
| 455 | |
Subrata Banik | 76d49a7 | 2023-01-16 16:33:18 +0530 | [diff] [blame] | 456 | config USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS |
| 457 | bool |
| 458 | help |
| 459 | Alder Lake SoC based OEM board design with UFS and non-UFS planned to use an |
| 460 | unified AP firmware which demanded to have a unified descriptor. It means UFS |
| 461 | controller needs to default fuse enabled to let UFS SKU to boot. |
| 462 | |
| 463 | On such design with non-UFS SKU is exhibiting S0ix failure due to UFS remain |
| 464 | enabled in the strap although FSP-S is making the UFS controller function |
| 465 | disabled. The potential root cause of this behaviour is although the UFS |
| 466 | controller is function disabled but MPHY clock is still in active state. |
| 467 | |
| 468 | A possible solution to this problem is to issue a warm reboot (if boot path is |
| 469 | S5->S0 or G3->S0) after disabling the UFS and let PMC to read the function |
| 470 | disable state of the UFS for disabling the MPHY clock. |
| 471 | |
| 472 | Mainboard users with such board design where OEM would like to use an unified AP |
| 473 | firmware to support both UFS and non-UFS sku booting might need to choose this |
| 474 | config to allow disabling UFS while booting on the non-UFS SKU. |
| 475 | Note: selection of this config would introduce an additional warm reset in |
| 476 | cold-reset scenarios due to function disabling of the UFS controller. |
| 477 | |
Furquan Shaikh | f888c68 | 2021-10-05 21:37:33 -0700 | [diff] [blame] | 478 | if STITCH_ME_BIN |
| 479 | |
| 480 | config CSE_BPDT_VERSION |
| 481 | default "1.7" |
| 482 | |
| 483 | endif |
| 484 | |
Sridhar Siricilla | b24c528 | 2022-02-23 12:19:04 +0530 | [diff] [blame] | 485 | config SI_DESC_REGION |
| 486 | string "Descriptor Region name" |
| 487 | default "SI_DESC" |
| 488 | help |
| 489 | Name of Descriptor Region in the FMAP |
| 490 | |
| 491 | config SI_DESC_REGION_SZ |
| 492 | int |
| 493 | default 4096 |
| 494 | help |
| 495 | Size of Descriptor Region in the FMAP |
| 496 | |
Kangheui Won | 9678722 | 2022-06-28 15:52:43 +1000 | [diff] [blame] | 497 | config BUILDING_WITH_DEBUG_FSP |
| 498 | bool "Debug FSP is used for the build" |
| 499 | default n |
| 500 | help |
| 501 | Set this option if debug build of FSP is used. |
| 502 | |
Tim Crawford | c6529c7 | 2022-11-01 11:42:28 -0600 | [diff] [blame] | 503 | config INTEL_GMA_BCLV_OFFSET |
| 504 | default 0xc8258 |
| 505 | |
| 506 | config INTEL_GMA_BCLV_WIDTH |
| 507 | default 32 |
| 508 | |
| 509 | config INTEL_GMA_BCLM_OFFSET |
| 510 | default 0xc8254 |
| 511 | |
| 512 | config INTEL_GMA_BCLM_WIDTH |
| 513 | default 32 |
| 514 | |
Kapil Porwal | 23ef60d | 2023-01-16 16:07:48 +0000 | [diff] [blame] | 515 | config FSP_PUBLISH_MBP_HOB |
| 516 | bool |
| 517 | default n if CHROMEOS && (SOC_INTEL_RAPTORLAKE || SOC_INTEL_ALDERLAKE_PCH_N) |
| 518 | default y |
| 519 | help |
| 520 | This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. |
| 521 | Disabling it for the platforms, which do not use MBP HOB, can improve the boot time. |
| 522 | |
| 523 | Note: It cannot be disabled for ADL-P based platforms because ADL-P FSP relies on |
| 524 | MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't |
| 525 | occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the |
| 526 | later platforms so creation of MBP HOB can be skipped for ADL-N and RPL based |
| 527 | platforms. |
| 528 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 529 | endif |