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review.coreboot.org / coreboot / ee735945754180544c8bd060d6fc0b9b2c507360 / . / src / soc / intel / alderlake / Kconfig
blob: b873a03de81fbb3a08b2df2e744a6c77e28f2d5d [file] [log] [blame]
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530[diff] [blame]1config SOC_INTEL_ALDERLAKE
2 bool
3 help
4 Intel Alderlake support
5
6if SOC_INTEL_ALDERLAKE
7
8config CPU_SPECIFIC_OPTIONS
9 def_bool y
10 select ARCH_BOOTBLOCK_X86_32
11 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
12 select BOOT_DEVICE_SUPPORTS_WRITES
13 select INTEL_DESCRIPTOR_MODE_CAPABLE
14 select IDT_IN_EVERY_STAGE
15 select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
16 select MICROCODE_BLOB_UNDISCLOSED
Subrata Banikee735942020-09-07 17:52:23 +0530[diff] [blame^]17 select PLATFORM_USES_FSP2_2
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530[diff] [blame]18 select SOC_INTEL_COMMON
19 select SOC_INTEL_COMMON_BLOCK
20 select SOC_INTEL_COMMON_BLOCK_CPU
21 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
22 select SOC_INTEL_COMMON_BLOCK_SA
23 select SOC_INTEL_COMMON_PCH_BASE
24 select SOC_INTEL_COMMON_RESET
25 select SOC_INTEL_COMMON_BLOCK_CAR
26 select SSE2
27 select SUPPORT_CPU_UCODE_IN_CBFS
28 select TSC_MONOTONIC_TIMER
29 select UDELAY_TSC
Subrata Banikee735942020-09-07 17:52:23 +0530[diff] [blame^]30 select UDK_202005_BINDING
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530[diff] [blame]31
32config DCACHE_RAM_BASE
33 default 0xfef00000
34
35config DCACHE_RAM_SIZE
36 default 0x80000
37 help
38 The size of the cache-as-ram region required during bootblock
39 and/or romstage.
40
41config DCACHE_BSP_STACK_SIZE
42 hex
43 default 0x40400
44 help
45 The amount of anticipated stack usage in CAR by bootblock and
46 other stages. In the case of FSP_USES_CB_STACK default value will be
47 sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement
48 (~1KiB).
49
50config FSP_TEMP_RAM_SIZE
51 hex
52 default 0x20000
53 help
54 The amount of anticipated heap usage in CAR by FSP.
55 Refer to Platform FSP integration guide document to know
56 the exact FSP requirement for Heap setup.
57
58config IFD_CHIPSET
59 string
60 default "adl"
61
62config IED_REGION_SIZE
63 hex
64 default 0x400000
65
66config HEAP_SIZE
67 hex
68 default 0x10000
69
70config PCR_BASE_ADDRESS
71 hex
72 default 0xfd000000
73 help
74 This option allows you to select MMIO Base Address of sideband bus.
75
76config MMCONF_BASE_ADDRESS
77 hex
78 default 0xc0000000
79
80config CPU_BCLK_MHZ
81 int
82 default 100
83
84config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
85 int
86 default 120
87
88config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
89 int
90 default 133
91
92config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
93 int
94 default 7
95
96config SOC_INTEL_I2C_DEV_MAX
97 int
98 default 6
99
100config SOC_INTEL_UART_DEV_MAX
101 int
102 default 7
103
104config CONSOLE_UART_BASE_ADDRESS
105 hex
106 default 0xfe032000
107 depends on INTEL_LPSS_UART_FOR_CONSOLE
108
109# Clock divider parameters for 115200 baud rate
110# Baudrate = (UART source clcok * M) /(N *16)
111# ADL UART source clock: 120MHz
112config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
113 hex
114 default 0x25a
115
116config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
117 hex
118 default 0x7fff
119
120config CHROMEOS
121 select CHROMEOS_RAMOOPS_DYNAMIC
122
123config C_ENV_BOOTBLOCK_SIZE
124 hex
125 default 0xC000
126
127config CBFS_SIZE
128 hex
129 default 0x200000
130
131config PRERAM_CBMEM_CONSOLE_SIZE
132 hex
133 default 0x1400
Subrata Banikee735942020-09-07 17:52:23 +0530[diff] [blame^]134config FSP_HEADER_PATH
135 string "Location of FSP headers"
136 default "src/vendorcode/intel/fsp/fsp2_0/alderlake/"
137
138config FSP_FD_PATH
139 string
140 depends on FSP_USE_REPO
141 default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd"
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530[diff] [blame]142endif