| commit | 298b35923d08747608224bc12d569cce731e5c35 | [log] [tgz] |
|---|---|---|
| author | Subrata Banik <subrata.banik@intel.com> | Tue Sep 14 12:38:08 2021 +0530 |
| committer | Subrata Banik <subrata.banik@intel.com> | Thu Sep 16 14:31:12 2021 +0000 |
| tree | dadcef41831d43283bb7994e7248403c9c9f12b8 | |
| parent | 8407c3464c9f1cbe13288a5eda9fa4be7e70020c [diff] |
drivers/intel/fsp2_0: Refactor MultiPhaseSiInit API calling method FspMultiPhaseSiInit API was introduced with FSP 2.2 specification onwards. EnableMultiPhaseSiliconInit is an arch UPD also introduced as part of FSP 2.2 specification to allow calling FspMultiPhaseSiInit API. However, some platforms adhere to the FSP specification but don't have arch UPD structure, for example : JSL, TGL and Xeon-SP. Out of these platforms, TGL supports calling of FspMultiPhaseSiInit API and considered EnableMultiPhaseSiliconInit as a platform-specific UPD rather than an arch UPD to allow calling into FspMultiPhaseSiInit API. It is important to ensure that the UPD setting and the callback for MultiPhaseInit are kept in sync, else it could result in broken behavior e.g. a hang is seen in FSP if EnableMultiPhaseSiliconInit UPD is set to 1 but the FspMultiPhaseSiInit API call is skipped. This patch provides an option for users to choose to bypass calling into MultiPhaseSiInit API and ensures the EnableMultiPhaseSiliconInit UPD is set to its default state as `disable` so that FSP-S don't consider MultiPhaseSiInit API is a mandatory entry point prior to calling other FSP API entry points. List of changes: 1. Add `FSPS_HAS_ARCH_UPD` Kconfig for SoC to select if `FSPS_ARCH_UPD` structure is part of `FSPS_UPD` structure. 2. Drop `soc_fsp_multi_phase_init_is_enable()` from JSL and Xeon-SP SoCs, a SoC override to callout that SoC doesn't support calling MultiPhase Si Init is no longer required. 3. Add `FSPS_USE_MULTI_PHASE_INIT` Kconfig for SoC to specify if SoC users want to enable `EnableMultiPhaseSiliconInit` arch UPD (using `fsp_fill_common_arch_params()`) and execute FspMultiPhaseSiInit() API. 4. Presently selects `FSPS_USE_MULTI_PHASE_INIT` from IA TCSS common code. 5. Add `fsp_is_multi_phase_init_enabled()` that check applicability of MultiPhase Si Init prior calling FspMultiPhaseSiInit() API to honor SoC users' decision. 6. Drop `arch_silicon_init_params()` from SoC as FSP driver (FSP 2.2) would check the applicability of MultiPhase Si Init prior calling FspMultiPhaseSiInit() API. Additionally, selects FSPS_HAS_ARCH_UPD for Alder Lake as Alder Lake FSPS_UPD structure has `FSPS_ARCH_UPD` structure and drops `arch_silicon_init_params()` from SoC `platform_fsp_silicon_init_params_cb()`. Skip EnableMultiPhaseSiliconInit hardcoding for Tiger Lake and uses the fsp_is_multi_phase_init_enabled() function to override EnableMultiPhaseSiliconInit UPD prior calling MultiPhaseSiInit FSP API. TEST=EnableMultiPhaseSiliconInit UPD is getting set or reset based on SoC user selects FSPS_USE_MULTI_PHASE_INIT Kconfig. Change-Id: I019fa8364605f5061d56e2d80b20e1a91857c423 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
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