soc/intel/adl: Update devicetree based on remapping for TBT PCIe
ADL has 4 TBT root ports which are PCIe compliant. TBT uses PCIe
coalescing logic where in case root port 0 is disabled, other enabled
root port is remapped to port 0.
coreboot handles this remapping scenarios for PCH and CPU PCIe root
ports and not for TBT root ports.
This patch uses the same function used for PCIe remapping to update
devicetree based on coalescing and SoC needs to pass correct function
number and number of slots.
BUG=b:210933428
BRANCH=None
TEST=Check if TBT remapping happens correctly and ACPI tables are
generated correctly.
Change-Id: Ied16191d6af41f8e2b31baee80cb475e7d557010
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 89d0c93..dc7d32b 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -207,6 +207,12 @@
default 0 if SOC_INTEL_ALDERLAKE_PCH_N
default 3 if SOC_INTEL_ALDERLAKE_PCH_P
+config MAX_TBT_ROOT_PORTS
+ int
+ default 0 if SOC_INTEL_ALDERLAKE_PCH_N
+ default 2 if SOC_INTEL_ALDERLAKE_PCH_M
+ default 4 if SOC_INTEL_ALDERLAKE_PCH_P
+
config MAX_ROOT_PORTS
int
default MAX_PCH_ROOT_PORTS