soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs
List of changes:
1. Create new Kconfig MAX_CPU_ROOT_PORTS and MAX_PCH_ROOT_PORTS as per
EDS.
2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards.
3. Rename PcieRpEnable to PchPcieRpEnable.
4. Enable CPU RPs as below in mainboard devicetree.cb
RP1: PEG60 : 0:6:0 : CPU SSD1
RP2: PEG10 : 0:1:0 : x8 CPU Slot
RP3: PEG62 : 0:6:2 : CPU SSD2
Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49136
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index c73df50..8009a42 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -119,10 +119,18 @@
hex
default 0x10000
-config MAX_ROOT_PORTS
+config MAX_PCH_ROOT_PORTS
int
default 12
+config MAX_CPU_ROOT_PORTS
+ int
+ default 3
+
+config MAX_ROOT_PORTS
+ int
+ default MAX_PCH_ROOT_PORTS
+
config MAX_PCIE_CLOCKS
int
default 12