| commit | 1ec8f97782060757dc8d2df2ff1c022039b225f8 | [log] [tgz] |
|---|---|---|
| author | Lean Sheng Tan <sheng.tan@9elements.com> | Wed Sep 07 16:07:33 2022 +0200 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Fri Sep 30 16:50:38 2022 +0000 |
| tree | cd0c75e355d023056b0923f086ebf37ee53f36ba | |
| parent | 7c3e48c5734aa3b5482bd36244d6c3b4a187eb3a [diff] [blame] |
soc/intel/adl: Add config option to enable FSP-S SATA test mode For further info on SATA test mode, please refer to this doc: https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/sata-mqst-setup-paper.pdf Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I6ef79fc5723348d5fd10b2ac0847191fa4f37f41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67410 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index c79eb08..a73657e 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig
@@ -317,6 +317,12 @@ help Select if using S3 instead of S0ix to disable D3Cold. +config ENABLE_SATA_TEST_MODE + bool "Enable test mode for SATA margining" + default n + help + Enable SATA test mode in FSP-S. + config SOC_INTEL_UART_DEV_MAX int default 7