soc/intel/adl: Move USB4 hotplug Kconfig to common
This change adds a new Kconfig `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES`
that can be selected by mainboard to reserve hotplug resources for
USB4 at the SoC level. `ADL_ENABLE_USB4_PCIE_RESOURCES` is dropped
from soc/intel/alderlake and instead the newly added Kconfig is now
used. This new Kconfig is added so that the same config can be used
across different platforms. In following changes, this Kconfig is
utilized by TGL as well.
Change-Id: Id7c359a0e255c43c2732f6cbe287bc7da14a46e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 1e16b42..e2116c7 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -148,11 +148,7 @@
# - 42 buses
# - 194 MiB Non-prefetchable memory
# - 448 MiB Prefetchable memory
-config ADL_ENABLE_USB4_PCIE_RESOURCES
- def_bool n
- select PCIEXP_HOTPLUG
-
-if ADL_ENABLE_USB4_PCIE_RESOURCES
+if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config PCIEXP_HOTPLUG_BUSES
int
@@ -166,7 +162,7 @@
hex
default 0x1c000000
-endif # ADL_ENABLE_USB4_PCIE_RESOURCES
+endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config MAX_PCH_ROOT_PORTS
int