Martin Roth | 7d86f34 | 2024-02-16 11:04:02 -0700 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 3 | config SOC_INTEL_ALDERLAKE |
| 4 | bool |
Angel Pons | a25eaff | 2020-09-23 15:37:15 +0200 | [diff] [blame] | 5 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 6 | select ARCH_X86 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 7 | select BOOT_DEVICE_SUPPORTS_WRITES |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 8 | select CACHE_MRC_SETTINGS |
| 9 | select CPU_INTEL_COMMON |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 10 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | 5307f12 | 2021-09-19 00:32:37 +0200 | [diff] [blame] | 11 | select CPU_SUPPORTS_INTEL_TME |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 12 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Matt DeVillier | decbf7b | 2023-01-18 18:58:38 -0600 | [diff] [blame] | 13 | select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 14 | select DISPLAY_FSP_VERSION_INFO |
Eric Lai | 4ea47c3 | 2020-12-21 16:57:49 +0800 | [diff] [blame] | 15 | select DRIVERS_USB_ACPI |
Sean Rhodes | 7bbc9a5 | 2022-07-18 11:31:00 +0100 | [diff] [blame] | 16 | select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 17 | select FSP_COMPRESS_FSP_S_LZ4 |
Subrata Banik | 683c95e | 2020-12-19 19:36:45 +0530 | [diff] [blame] | 18 | select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 19 | select FSP_M_XIP |
Subrata Banik | 65b64b3 | 2023-04-26 16:36:05 +0530 | [diff] [blame] | 20 | select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 21 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Subrata Banik | e4cf3fa | 2022-03-23 01:41:36 +0530 | [diff] [blame] | 22 | select FSP_USES_CB_DEBUG_EVENT_HANDLER |
Subrata Banik | 298b359 | 2021-09-14 12:38:08 +0530 | [diff] [blame] | 23 | select FSPS_HAS_ARCH_UPD |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 24 | select GENERIC_GPIO_LIB |
Subrata Banik | b4a169a | 2021-12-29 18:36:23 +0000 | [diff] [blame] | 25 | select HAVE_DEBUG_RAM_SETUP |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 26 | select HAVE_FSP_GOP |
Felix Singer | a182fae | 2021-12-31 00:30:55 +0100 | [diff] [blame] | 27 | select HAVE_HYPERTHREADING |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 28 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 29 | select HAVE_SMI_HANDLER |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 30 | select IDT_IN_EVERY_STAGE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 31 | select INTEL_GMA_ACPI |
| 32 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Meera Ravindranath | 81d367f | 2021-07-08 09:39:11 +0530 | [diff] [blame] | 33 | select INTEL_GMA_OPREGION_2_1 |
Subrata Banik | 913ea97 | 2023-09-20 19:28:41 +0000 | [diff] [blame] | 34 | select INTEL_GMA_VERSION_2 |
Subrata Banik | c8b840f | 2022-12-31 14:47:55 +0530 | [diff] [blame] | 35 | select INTEL_TXT_LIB |
Subrata Banik | a247319 | 2023-02-22 13:03:04 +0000 | [diff] [blame] | 36 | select MP_SERVICES_PPI_V2 |
Ronak Kanabar | 14feda4 | 2024-03-04 15:48:44 +0530 | [diff] [blame^] | 37 | select MRC_CACHE_USING_MRC_VERSION if SOC_INTEL_ALDERLAKE_PCH_N && !FSP_TYPE_IOT |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 38 | select MRC_SETTINGS_PROTECT |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 39 | select PARALLEL_MP_AP_WORK |
Michał Żygowski | 073779b | 2022-06-29 11:32:01 +0200 | [diff] [blame] | 40 | select PLATFORM_USES_FSP2_2 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 41 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 42 | select SOC_INTEL_COMMON |
Zhixing Ma | 30e8fc1 | 2022-09-30 14:18:13 -0700 | [diff] [blame] | 43 | select CPU_INTEL_COMMON_VOLTAGE |
Subrata Banik | 0808992 | 2020-10-03 13:02:06 +0530 | [diff] [blame] | 44 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Lean Sheng Tan | ce68d68 | 2023-03-15 15:32:01 +0100 | [diff] [blame] | 45 | select SOC_INTEL_COMMON_BASECODE |
| 46 | select SOC_INTEL_COMMON_BASECODE_RAMTOP |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 47 | select SOC_INTEL_COMMON_BLOCK |
Subrata Banik | 0808992 | 2020-10-03 13:02:06 +0530 | [diff] [blame] | 48 | select SOC_INTEL_COMMON_BLOCK_ACPI |
ravindr1 | 7459657 | 2021-03-29 19:41:25 +0530 | [diff] [blame] | 49 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC |
Sridahr Siricilla | 73b90c6 | 2021-11-11 01:10:16 +0530 | [diff] [blame] | 50 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID |
Angel Pons | 98f672a | 2021-02-19 19:42:10 +0100 | [diff] [blame] | 51 | select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
Jeremy Soller | 5219ee1 | 2022-05-26 09:02:13 -0600 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT |
Tim Wawrzynczak | 5faee2e | 2021-07-01 08:24:18 -0600 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP |
| 54 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ |
Subrata Banik | 21974ab | 2020-10-31 21:40:43 +0530 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_CAR |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Varshit B Pandya | 2938c46 | 2022-02-16 20:38:10 +0530 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_BLOCK_CNVI |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_BLOCK_CPU |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Angel Pons | a4cd911 | 2021-02-19 19:23:38 +0100 | [diff] [blame] | 60 | select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 61 | select SOC_INTEL_COMMON_BLOCK_DTT |
| 62 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Subrata Banik | af2f8b9 | 2022-01-10 10:26:52 +0000 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 64 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
Krishna Prasad Bhat | 01e426d | 2022-01-16 22:37:21 +0530 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 66 | select SOC_INTEL_COMMON_BLOCK_HDA |
Subrata Banik | c176fc2 | 2022-04-25 16:59:35 +0530 | [diff] [blame] | 67 | select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC |
Michał Żygowski | 3d1e562 | 2022-04-08 17:09:49 +0200 | [diff] [blame] | 68 | select SOC_INTEL_COMMON_BLOCK_IPU if !SOC_INTEL_ALDERLAKE_PCH_S |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 69 | select SOC_INTEL_COMMON_BLOCK_IRQ |
Dinesh Gehlot | 930fded | 2023-02-24 05:09:04 +0000 | [diff] [blame] | 70 | select SOC_INTEL_COMMON_BLOCK_ME_SPEC_16 |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 71 | select SOC_INTEL_COMMON_BLOCK_MEMINIT |
Michał Żygowski | ce14b61 | 2022-10-28 15:53:23 +0200 | [diff] [blame] | 72 | select SOC_INTEL_COMMON_BLOCK_OC_WDT |
Rizwan Qureshi | 307be99 | 2021-04-08 20:35:29 +0530 | [diff] [blame] | 73 | select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 |
Lean Sheng Tan | 7502000 | 2021-06-30 01:47:48 -0700 | [diff] [blame] | 74 | select SOC_INTEL_COMMON_BLOCK_PMC_EPOC |
Sumeet R Pawnikar | 77298c6 | 2021-03-10 21:09:37 +0530 | [diff] [blame] | 75 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 76 | select SOC_INTEL_COMMON_BLOCK_SA |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 77 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 78 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | b2e8bd8 | 2021-11-17 15:35:05 +0530 | [diff] [blame] | 79 | select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC |
Michał Żygowski | 5f05ee2 | 2023-01-18 12:18:00 +0100 | [diff] [blame] | 80 | select SOC_INTEL_COMMON_BLOCK_VTD |
Tim Wawrzynczak | 242da79 | 2020-11-10 10:13:54 -0700 | [diff] [blame] | 81 | select SOC_INTEL_COMMON_BLOCK_XHCI |
| 82 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 83 | select SOC_INTEL_COMMON_FSP_RESET |
Angel Pons | eb90c51 | 2022-07-18 14:41:24 +0200 | [diff] [blame] | 84 | select SOC_INTEL_COMMON_PCH_CLIENT |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 85 | select SOC_INTEL_COMMON_RESET |
Karthikeyan Ramasubramanian | 817c58c | 2024-05-08 13:18:36 -0600 | [diff] [blame] | 86 | select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON && !BOARD_GOOGLE_BROX_COMMON |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 87 | select SOC_INTEL_CSE_SET_EOP |
Subrata Banik | 93ca15c | 2023-10-16 14:06:27 +0530 | [diff] [blame] | 88 | select SOC_INTEL_GFX_MBUS_JOIN if MAINBOARD_HAS_CHROMEOS && BMP_LOGO |
Subrata Banik | af27ac2 | 2022-02-18 00:44:15 +0530 | [diff] [blame] | 89 | select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION |
Sridahr Siricilla | 096ce14 | 2021-09-17 22:25:17 +0530 | [diff] [blame] | 90 | select HAVE_INTEL_COMPLIANCE_TEST_MODE |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 91 | select SSE2 |
| 92 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 93 | select TSC_MONOTONIC_TIMER |
| 94 | select UDELAY_TSC |
Ronak Kanabar | 01515c5 | 2024-01-31 16:25:27 +0530 | [diff] [blame] | 95 | select UDK_202111_BINDING if SOC_INTEL_ALDERLAKE_PCH_N |
| 96 | select UDK_202005_BINDING if !SOC_INTEL_ALDERLAKE_PCH_N |
Michał Żygowski | 9b0f169 | 2022-05-05 13:21:01 +0200 | [diff] [blame] | 97 | select VBOOT_LIB |
Lean Sheng Tan | 8615245 | 2023-03-13 14:51:10 +0100 | [diff] [blame] | 98 | select X86_CLFLUSH_CAR |
Elyes Haouas | fefb8be | 2023-08-03 20:46:31 +0200 | [diff] [blame] | 99 | help |
| 100 | Intel Alderlake support. Mainboards should specify the PCH |
| 101 | type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead |
| 102 | of selecting this option directly. |
| 103 | |
| 104 | config SOC_INTEL_RAPTORLAKE |
| 105 | bool |
| 106 | select X86_INIT_NEED_1_SIPI |
| 107 | help |
| 108 | Intel Raptorlake support. Mainboards using RPL should select |
| 109 | SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together. |
| 110 | |
Kapil Porwal | 0a1d68f | 2024-02-21 16:05:36 +0000 | [diff] [blame] | 111 | config SOC_INTEL_TWINLAKE |
| 112 | bool |
| 113 | select SOC_INTEL_ALDERLAKE_PCH_N |
| 114 | help |
| 115 | Intel Twinlake support. Mainboards using TWL should select |
| 116 | SOC_INTEL_TWINLAKE. |
| 117 | |
Elyes Haouas | fefb8be | 2023-08-03 20:46:31 +0200 | [diff] [blame] | 118 | config SOC_INTEL_ALDERLAKE_PCH_N |
| 119 | bool |
Ronak Kanabar | bf1166e | 2024-06-03 15:15:16 +0530 | [diff] [blame] | 120 | select HAVE_INTEL_FSP_REPO if FSP_TYPE_IOT |
Elyes Haouas | fefb8be | 2023-08-03 20:46:31 +0200 | [diff] [blame] | 121 | select SOC_INTEL_ALDERLAKE |
Elyes Haouas | fefb8be | 2023-08-03 20:46:31 +0200 | [diff] [blame] | 122 | help |
| 123 | Choose this option if your mainboard has a PCH-N chipset. |
| 124 | |
| 125 | config SOC_INTEL_ALDERLAKE_PCH_P |
| 126 | bool |
| 127 | select SOC_INTEL_ALDERLAKE |
| 128 | select HAVE_INTEL_FSP_REPO |
| 129 | select PLATFORM_USES_FSP2_3 |
| 130 | help |
| 131 | Choose this option if your mainboard has a PCH-P chipset. |
| 132 | |
| 133 | config SOC_INTEL_ALDERLAKE_PCH_S |
| 134 | bool |
| 135 | select SOC_INTEL_ALDERLAKE |
Michał Żygowski | 82d2d4f | 2023-10-16 15:20:50 +0200 | [diff] [blame] | 136 | select HAVE_INTEL_FSP_REPO |
Elyes Haouas | fefb8be | 2023-08-03 20:46:31 +0200 | [diff] [blame] | 137 | select PLATFORM_USES_FSP2_3 |
| 138 | help |
| 139 | Choose this option if your mainboard has a PCH-S chipset. |
| 140 | |
| 141 | config SOC_INTEL_RAPTORLAKE_PCH_S |
| 142 | bool |
| 143 | select SOC_INTEL_ALDERLAKE_PCH_S |
| 144 | select SOC_INTEL_RAPTORLAKE |
| 145 | help |
| 146 | Choose this option if your mainboard has a Raptor Lake PCH-S chipset. |
| 147 | |
| 148 | if SOC_INTEL_ALDERLAKE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 149 | |
Felix Singer | c64bfdf | 2024-04-28 21:56:44 +0200 | [diff] [blame] | 150 | config DIMM_SPD_SIZE |
| 151 | default 512 |
| 152 | |
Michał Żygowski | 9df95d9 | 2022-04-08 17:02:35 +0200 | [diff] [blame] | 153 | config SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT |
| 154 | bool |
Michał Żygowski | 9df95d9 | 2022-04-08 17:02:35 +0200 | [diff] [blame] | 155 | default n if SOC_INTEL_ALDERLAKE_PCH_S |
Michał Żygowski | eeba3e7 | 2023-06-16 11:15:12 +0200 | [diff] [blame] | 156 | default y |
Michał Żygowski | 9df95d9 | 2022-04-08 17:02:35 +0200 | [diff] [blame] | 157 | select SOC_INTEL_COMMON_BLOCK_TCSS |
| 158 | select SOC_INTEL_COMMON_BLOCK_USB4 |
| 159 | select SOC_INTEL_COMMON_BLOCK_USB4_PCIE |
| 160 | select SOC_INTEL_COMMON_BLOCK_USB4_XHCI |
| 161 | |
Reka Norman | e790f92 | 2022-04-06 20:33:54 +1000 | [diff] [blame] | 162 | config ALDERLAKE_CONFIGURE_DESCRIPTOR |
| 163 | bool |
| 164 | help |
| 165 | Select this if the descriptor needs to be updated at runtime. This |
| 166 | can only be done if the descriptor region is writable, and should only |
| 167 | be used as a temporary workaround. |
| 168 | |
Subrata Banik | 095e2a7 | 2021-07-05 20:56:15 +0530 | [diff] [blame] | 169 | config ALDERLAKE_CAR_ENHANCED_NEM |
| 170 | bool |
| 171 | default y if !INTEL_CAR_NEM |
| 172 | select INTEL_CAR_NEM_ENHANCED |
| 173 | select CAR_HAS_SF_MASKS |
| 174 | select COS_MAPPED_TO_MSB |
| 175 | select CAR_HAS_L3_PROTECTED_WAYS |
| 176 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 177 | config MAX_CPUS |
| 178 | int |
Tim Crawford | 35860ff | 2023-03-06 11:28:40 -0700 | [diff] [blame] | 179 | default 32 if SOC_INTEL_RAPTORLAKE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 180 | default 24 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 181 | |
| 182 | config DCACHE_RAM_BASE |
| 183 | default 0xfef00000 |
| 184 | |
| 185 | config DCACHE_RAM_SIZE |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 186 | default 0xc0000 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 187 | help |
| 188 | The size of the cache-as-ram region required during bootblock |
| 189 | and/or romstage. |
| 190 | |
| 191 | config DCACHE_BSP_STACK_SIZE |
| 192 | hex |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 193 | default 0x80400 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 194 | help |
| 195 | The amount of anticipated stack usage in CAR by bootblock and |
| 196 | other stages. In the case of FSP_USES_CB_STACK default value will be |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 197 | sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 198 | (~1KiB). |
| 199 | |
| 200 | config FSP_TEMP_RAM_SIZE |
| 201 | hex |
| 202 | default 0x20000 |
| 203 | help |
| 204 | The amount of anticipated heap usage in CAR by FSP. |
| 205 | Refer to Platform FSP integration guide document to know |
| 206 | the exact FSP requirement for Heap setup. |
| 207 | |
Tim Wawrzynczak | 092813a | 2020-11-24 13:48:56 -0700 | [diff] [blame] | 208 | config CHIPSET_DEVICETREE |
| 209 | string |
Michał Kopeć | 75a49fe | 2022-04-08 11:28:45 +0200 | [diff] [blame] | 210 | default "soc/intel/alderlake/chipset_pch_s.cb" if SOC_INTEL_ALDERLAKE_PCH_S |
Tim Wawrzynczak | 092813a | 2020-11-24 13:48:56 -0700 | [diff] [blame] | 211 | default "soc/intel/alderlake/chipset.cb" |
| 212 | |
Subrata Banik | 683c95e | 2020-12-19 19:36:45 +0530 | [diff] [blame] | 213 | config EXT_BIOS_WIN_BASE |
| 214 | default 0xf8000000 |
| 215 | |
| 216 | config EXT_BIOS_WIN_SIZE |
| 217 | default 0x2000000 |
| 218 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 219 | config IFD_CHIPSET |
| 220 | string |
| 221 | default "adl" |
| 222 | |
| 223 | config IED_REGION_SIZE |
| 224 | hex |
| 225 | default 0x400000 |
| 226 | |
Jeremy Compostella | 9df1197 | 2022-12-02 10:59:49 -0700 | [diff] [blame] | 227 | config GFX_GMA_DEFAULT_MMIO |
Jeremy Compostella | 0ad4003 | 2023-01-30 14:18:21 -0700 | [diff] [blame] | 228 | default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT |
Jeremy Compostella | 9df1197 | 2022-12-02 10:59:49 -0700 | [diff] [blame] | 229 | |
Tim Wawrzynczak | 8d11cdc | 2021-03-12 12:46:02 -0700 | [diff] [blame] | 230 | # Intel recommends reserving the following resources per PCIe TBT root port, |
| 231 | # from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5 |
| 232 | # - 42 buses |
| 233 | # - 194 MiB Non-prefetchable memory |
| 234 | # - 448 MiB Prefetchable memory |
Furquan Shaikh | d9f5d90 | 2021-08-24 13:53:43 -0700 | [diff] [blame] | 235 | if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
Tim Wawrzynczak | 8d11cdc | 2021-03-12 12:46:02 -0700 | [diff] [blame] | 236 | |
| 237 | config PCIEXP_HOTPLUG_BUSES |
| 238 | int |
| 239 | default 42 |
| 240 | |
| 241 | config PCIEXP_HOTPLUG_MEM |
| 242 | hex |
| 243 | default 0xc200000 |
| 244 | |
| 245 | config PCIEXP_HOTPLUG_PREFETCH_MEM |
| 246 | hex |
| 247 | default 0x1c000000 |
| 248 | |
Furquan Shaikh | d9f5d90 | 2021-08-24 13:53:43 -0700 | [diff] [blame] | 249 | endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
Tim Wawrzynczak | 8d11cdc | 2021-03-12 12:46:02 -0700 | [diff] [blame] | 250 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 251 | config MAX_PCH_ROOT_PORTS |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 252 | int |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 253 | default 12 if SOC_INTEL_ALDERLAKE_PCH_N |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 254 | default 12 if SOC_INTEL_ALDERLAKE_PCH_P |
Michał Żygowski | 27fdfc6 | 2022-04-07 15:03:09 +0200 | [diff] [blame] | 255 | default 28 if SOC_INTEL_ALDERLAKE_PCH_S |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 256 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 257 | config MAX_CPU_ROOT_PORTS |
| 258 | int |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 259 | default 0 if SOC_INTEL_ALDERLAKE_PCH_N |
Michał Żygowski | 27fdfc6 | 2022-04-07 15:03:09 +0200 | [diff] [blame] | 260 | default 3 if SOC_INTEL_ALDERLAKE_PCH_P || SOC_INTEL_ALDERLAKE_PCH_S |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 261 | |
MAULIK V VAGHELA | 3e4f28f | 2022-01-21 14:17:53 +0530 | [diff] [blame] | 262 | config MAX_TBT_ROOT_PORTS |
| 263 | int |
Michał Żygowski | 27fdfc6 | 2022-04-07 15:03:09 +0200 | [diff] [blame] | 264 | default 0 if SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_ALDERLAKE_PCH_S |
MAULIK V VAGHELA | 3e4f28f | 2022-01-21 14:17:53 +0530 | [diff] [blame] | 265 | default 4 if SOC_INTEL_ALDERLAKE_PCH_P |
| 266 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 267 | config MAX_ROOT_PORTS |
| 268 | int |
| 269 | default MAX_PCH_ROOT_PORTS |
| 270 | |
Subrata Banik | cffc938 | 2021-01-29 18:41:35 +0530 | [diff] [blame] | 271 | config MAX_PCIE_CLOCK_SRC |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 272 | int |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 273 | default 5 if SOC_INTEL_ALDERLAKE_PCH_N |
Cliff Huang | 0d590b7 | 2022-04-28 18:20:27 -0700 | [diff] [blame] | 274 | default 10 if SOC_INTEL_ALDERLAKE_PCH_P |
Angel Pons | 122e1df | 2022-12-09 12:32:12 +0100 | [diff] [blame] | 275 | default 18 if SOC_INTEL_ALDERLAKE_PCH_S |
Cliff Huang | 0d590b7 | 2022-04-28 18:20:27 -0700 | [diff] [blame] | 276 | help |
| 277 | With external clock buffer, Alderlake-P can support up to three additional source clocks. |
| 278 | This is done by setting the corresponding GPIO pin(s) to native function to use as |
| 279 | SRCCLK_OE[6..9]. In addition, SRCCLK6 does not need to be set to free running clock. |
| 280 | If any of SRCCLKReq 6..9 is asserted, SRCCLK6 will be turned on. |
Subrata Banik | cffc938 | 2021-01-29 18:41:35 +0530 | [diff] [blame] | 281 | |
| 282 | config MAX_PCIE_CLOCK_REQ |
| 283 | int |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 284 | default 5 if SOC_INTEL_ALDERLAKE_PCH_N |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 285 | default 10 if SOC_INTEL_ALDERLAKE_PCH_P |
Michał Żygowski | 27fdfc6 | 2022-04-07 15:03:09 +0200 | [diff] [blame] | 286 | default 18 if SOC_INTEL_ALDERLAKE_PCH_S |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 287 | |
| 288 | config SMM_TSEG_SIZE |
| 289 | hex |
| 290 | default 0x800000 |
| 291 | |
| 292 | config SMM_RESERVED_SIZE |
| 293 | hex |
| 294 | default 0x200000 |
| 295 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 296 | config PCR_BASE_ADDRESS |
| 297 | hex |
Michał Żygowski | dccfb8a | 2022-04-07 15:09:19 +0200 | [diff] [blame] | 298 | default 0xe0000000 if SOC_INTEL_ALDERLAKE_PCH_S |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 299 | default 0xfd000000 |
| 300 | help |
| 301 | This option allows you to select MMIO Base Address of sideband bus. |
| 302 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 303 | config ECAM_MMCONF_BASE_ADDRESS |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 304 | default 0xc0000000 |
| 305 | |
| 306 | config CPU_BCLK_MHZ |
| 307 | int |
| 308 | default 100 |
| 309 | |
Sridhar Siricilla | d9c8269 | 2023-01-05 17:08:17 +0530 | [diff] [blame] | 310 | config SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR |
| 311 | int |
| 312 | default 127 |
| 313 | |
| 314 | config SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR |
| 315 | int |
| 316 | default 100 |
| 317 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 318 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 319 | int |
| 320 | default 120 |
| 321 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 322 | config CPU_XTAL_HZ |
| 323 | default 38400000 |
| 324 | |
Meera Ravindranath | d307d0d | 2022-07-21 20:45:32 +0530 | [diff] [blame] | 325 | config SOC_INTEL_UFS_CLK_FREQ_HZ |
| 326 | int |
| 327 | default 19200000 |
| 328 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 329 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 330 | int |
| 331 | default 133 |
| 332 | |
| 333 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 334 | int |
| 335 | default 7 |
| 336 | |
| 337 | config SOC_INTEL_I2C_DEV_MAX |
| 338 | int |
Varshit B Pandya | 339f0e7 | 2021-07-14 11:08:23 +0530 | [diff] [blame] | 339 | default 8 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 340 | |
Lean Sheng Tan | 1ec8f97 | 2022-09-07 16:07:33 +0200 | [diff] [blame] | 341 | config ENABLE_SATA_TEST_MODE |
| 342 | bool "Enable test mode for SATA margining" |
| 343 | default n |
| 344 | help |
| 345 | Enable SATA test mode in FSP-S. |
| 346 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 347 | config SOC_INTEL_UART_DEV_MAX |
| 348 | int |
| 349 | default 7 |
| 350 | |
| 351 | config CONSOLE_UART_BASE_ADDRESS |
| 352 | hex |
Bora Guvendik | 2a70419 | 2020-11-16 11:23:48 -0800 | [diff] [blame] | 353 | default 0xfe03e000 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 354 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 355 | |
| 356 | # Clock divider parameters for 115200 baud rate |
Angel Pons | 054ff5e | 2022-06-26 10:19:53 +0200 | [diff] [blame] | 357 | # Baudrate = (UART source clock * M) /(N *16) |
Wonkyu Kim | 60d9b89 | 2022-10-10 23:01:38 -0700 | [diff] [blame] | 358 | # ADL UART source clock: 100MHz |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 359 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 360 | hex |
| 361 | default 0x25a |
| 362 | |
| 363 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 364 | hex |
| 365 | default 0x7fff |
| 366 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 367 | config VBOOT |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 368 | select VBOOT_MUST_REQUEST_DISPLAY |
| 369 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 370 | select VBOOT_VBNV_CMOS |
| 371 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Subrata Banik | 3423786 | 2021-06-17 23:36:02 +0530 | [diff] [blame] | 372 | select VBOOT_X86_SHA256_ACCELERATION |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 373 | |
MAULIK V VAGHELA | 84532da | 2021-08-25 16:41:23 +0530 | [diff] [blame] | 374 | # Default hash block size is 1KiB. Increasing it to 4KiB to improve |
| 375 | # hashing time as well as read time. This helps in improving |
| 376 | # boot time for Alder Lake. |
| 377 | config VBOOT_HASH_BLOCK_SIZE |
| 378 | hex |
| 379 | default 0x1000 |
| 380 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 381 | config CBFS_SIZE |
Felix Singer | d486fc3 | 2023-07-03 11:13:19 +0000 | [diff] [blame] | 382 | default 0x400000 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 383 | |
| 384 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 385 | hex |
Tarun Tuli | 2b03894 | 2023-01-24 13:50:17 +0000 | [diff] [blame] | 386 | default 0x4000 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 387 | |
Tarun Tuli | df74d9b | 2023-01-24 13:28:06 +0000 | [diff] [blame] | 388 | config CONSOLE_CBMEM_BUFFER_SIZE |
| 389 | hex |
Subrata Banik | 5259568 | 2023-07-17 13:05:37 +0530 | [diff] [blame] | 390 | default 0x100000 if BUILDING_WITH_DEBUG_FSP |
Tarun Tuli | df74d9b | 2023-01-24 13:28:06 +0000 | [diff] [blame] | 391 | default 0x40000 |
| 392 | |
Lean Sheng Tan | bbd72d2 | 2022-08-02 12:29:42 +0200 | [diff] [blame] | 393 | config FSP_TYPE_IOT |
| 394 | bool |
| 395 | default n |
| 396 | help |
| 397 | This option allows to select FSP IOT type from 3rdparty/fsp repo |
| 398 | |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 399 | config FSP_HEADER_PATH |
| 400 | string "Location of FSP headers" |
Kapil Porwal | 0a1d68f | 2024-02-21 16:05:36 +0000 | [diff] [blame] | 401 | default "src/vendorcode/intel/fsp/fsp2_0/twinlake/" if SOC_INTEL_TWINLAKE && !FSP_USE_REPO |
Sean Rhodes | e3d9b0a | 2023-08-09 10:58:32 +0100 | [diff] [blame] | 402 | default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N && !FSP_USE_REPO |
Kulkarni, Srinivas | 7c6f1d5 | 2023-12-13 13:46:58 +0530 | [diff] [blame] | 403 | default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE && !FSP_USE_REPO |
Michał Żygowski | 5001461 | 2023-10-16 15:17:20 +0200 | [diff] [blame] | 404 | default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/Include/" if SOC_INTEL_RAPTORLAKE_PCH_S && FSP_TYPE_IOT |
Matt DeVillier | a9a8e77 | 2023-09-29 10:50:04 -0500 | [diff] [blame] | 405 | default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE |
| 406 | default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && SOC_INTEL_RAPTORLAKE |
Lean Sheng Tan | bbd72d2 | 2022-08-02 12:29:42 +0200 | [diff] [blame] | 407 | default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT |
| 408 | default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT |
Bora Guvendik | d353d7e | 2023-09-20 13:52:06 -0700 | [diff] [blame] | 409 | default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && !SOC_INTEL_RAPTORLAKE |
| 410 | default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE |
Michał Żygowski | 073779b | 2022-06-29 11:32:01 +0200 | [diff] [blame] | 411 | default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S |
Ronak Kanabar | bf1166e | 2024-06-03 15:15:16 +0530 | [diff] [blame] | 412 | default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Include/" if SOC_INTEL_ALDERLAKE_PCH_N && FSP_TYPE_IOT |
Michał Żygowski | 01025d3 | 2023-07-12 13:22:09 +0200 | [diff] [blame] | 413 | default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" if !FSP_USE_REPO |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 414 | |
| 415 | config FSP_FD_PATH |
| 416 | string |
| 417 | depends on FSP_USE_REPO |
Michał Żygowski | eeba3e7 | 2023-06-16 11:15:12 +0200 | [diff] [blame] | 418 | default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if SOC_INTEL_RAPTORLAKE_PCH_S && FSP_TYPE_IOT |
Matt DeVillier | a9a8e77 | 2023-09-29 10:50:04 -0500 | [diff] [blame] | 419 | default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE |
| 420 | default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S && SOC_INTEL_RAPTORLAKE |
Lean Sheng Tan | bbd72d2 | 2022-08-02 12:29:42 +0200 | [diff] [blame] | 421 | default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT |
| 422 | default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT |
Bora Guvendik | d353d7e | 2023-09-20 13:52:06 -0700 | [diff] [blame] | 423 | default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && !SOC_INTEL_RAPTORLAKE |
| 424 | default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE |
Michał Żygowski | 073779b | 2022-06-29 11:32:01 +0200 | [diff] [blame] | 425 | default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S |
Ronak Kanabar | bf1166e | 2024-06-03 15:15:16 +0530 | [diff] [blame] | 426 | default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_N && FSP_TYPE_IOT |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 427 | |
| 428 | config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT |
| 429 | int "Debug Consent for ADL" |
Subrata Banik | 0cd553b | 2021-12-29 08:09:37 +0000 | [diff] [blame] | 430 | # USB DBC is more common for developers so make this default to 2 if |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 431 | # SOC_INTEL_DEBUG_CONSENT=y |
Kane Chen | 0e9a616 | 2021-11-23 14:42:48 +0800 | [diff] [blame] | 432 | default 2 if SOC_INTEL_DEBUG_CONSENT |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 433 | default 0 |
| 434 | help |
| 435 | This is to control debug interface on SOC. |
| 436 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 437 | PlatformDebugConsent in FspmUpd.h has the details. |
| 438 | |
| 439 | Desired platform debug type are |
Kane Chen | 0e9a616 | 2021-11-23 14:42:48 +0800 | [diff] [blame] | 440 | 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), |
| 441 | 7:Manual |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 442 | |
| 443 | config DATA_BUS_WIDTH |
| 444 | int |
| 445 | default 128 |
| 446 | |
| 447 | config DIMMS_PER_CHANNEL |
| 448 | int |
| 449 | default 2 |
| 450 | |
| 451 | config MRC_CHANNEL_WIDTH |
| 452 | int |
| 453 | default 16 |
| 454 | |
Subrata Banik | a00db94 | 2022-10-12 14:24:41 +0530 | [diff] [blame] | 455 | config ALDERLAKE_ENABLE_SOC_WORKAROUND |
| 456 | bool |
| 457 | default y |
Meera Ravindranath | 9e4488a | 2022-10-10 10:48:18 +0530 | [diff] [blame] | 458 | select SOC_INTEL_UFS_LTR_DISQUALIFY |
Subrata Banik | a00db94 | 2022-10-12 14:24:41 +0530 | [diff] [blame] | 459 | select SOC_INTEL_UFS_OCP_TIMER_DISABLE |
| 460 | help |
| 461 | Selects the workarounds applicable for Alder Lake SoC. |
| 462 | |
Subrata Banik | 76d49a7 | 2023-01-16 16:33:18 +0530 | [diff] [blame] | 463 | config USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS |
| 464 | bool |
| 465 | help |
| 466 | Alder Lake SoC based OEM board design with UFS and non-UFS planned to use an |
| 467 | unified AP firmware which demanded to have a unified descriptor. It means UFS |
| 468 | controller needs to default fuse enabled to let UFS SKU to boot. |
| 469 | |
| 470 | On such design with non-UFS SKU is exhibiting S0ix failure due to UFS remain |
| 471 | enabled in the strap although FSP-S is making the UFS controller function |
| 472 | disabled. The potential root cause of this behaviour is although the UFS |
| 473 | controller is function disabled but MPHY clock is still in active state. |
| 474 | |
| 475 | A possible solution to this problem is to issue a warm reboot (if boot path is |
| 476 | S5->S0 or G3->S0) after disabling the UFS and let PMC to read the function |
| 477 | disable state of the UFS for disabling the MPHY clock. |
| 478 | |
| 479 | Mainboard users with such board design where OEM would like to use an unified AP |
| 480 | firmware to support both UFS and non-UFS sku booting might need to choose this |
| 481 | config to allow disabling UFS while booting on the non-UFS SKU. |
| 482 | Note: selection of this config would introduce an additional warm reset in |
| 483 | cold-reset scenarios due to function disabling of the UFS controller. |
| 484 | |
Furquan Shaikh | f888c68 | 2021-10-05 21:37:33 -0700 | [diff] [blame] | 485 | if STITCH_ME_BIN |
| 486 | |
| 487 | config CSE_BPDT_VERSION |
| 488 | default "1.7" |
| 489 | |
| 490 | endif |
| 491 | |
Sridhar Siricilla | b24c528 | 2022-02-23 12:19:04 +0530 | [diff] [blame] | 492 | config SI_DESC_REGION |
| 493 | string "Descriptor Region name" |
| 494 | default "SI_DESC" |
| 495 | help |
| 496 | Name of Descriptor Region in the FMAP |
| 497 | |
| 498 | config SI_DESC_REGION_SZ |
| 499 | int |
| 500 | default 4096 |
| 501 | help |
| 502 | Size of Descriptor Region in the FMAP |
| 503 | |
Kangheui Won | 9678722 | 2022-06-28 15:52:43 +1000 | [diff] [blame] | 504 | config BUILDING_WITH_DEBUG_FSP |
| 505 | bool "Debug FSP is used for the build" |
| 506 | default n |
| 507 | help |
| 508 | Set this option if debug build of FSP is used. |
| 509 | |
Tim Crawford | c6529c7 | 2022-11-01 11:42:28 -0600 | [diff] [blame] | 510 | config INTEL_GMA_BCLV_OFFSET |
| 511 | default 0xc8258 |
| 512 | |
| 513 | config INTEL_GMA_BCLV_WIDTH |
| 514 | default 32 |
| 515 | |
| 516 | config INTEL_GMA_BCLM_OFFSET |
| 517 | default 0xc8254 |
| 518 | |
| 519 | config INTEL_GMA_BCLM_WIDTH |
| 520 | default 32 |
| 521 | |
Kapil Porwal | 23ef60d | 2023-01-16 16:07:48 +0000 | [diff] [blame] | 522 | config FSP_PUBLISH_MBP_HOB |
| 523 | bool |
Kilari Raasi | 8ec17cf | 2024-03-27 15:00:31 +0530 | [diff] [blame] | 524 | default n if CHROMEOS && (SOC_INTEL_ALDERLAKE_PCH_N) |
Kapil Porwal | 23ef60d | 2023-01-16 16:07:48 +0000 | [diff] [blame] | 525 | default y |
| 526 | help |
| 527 | This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. |
| 528 | Disabling it for the platforms, which do not use MBP HOB, can improve the boot time. |
| 529 | |
| 530 | Note: It cannot be disabled for ADL-P based platforms because ADL-P FSP relies on |
| 531 | MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't |
| 532 | occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the |
Kilari Raasi | 8ec17cf | 2024-03-27 15:00:31 +0530 | [diff] [blame] | 533 | later platforms so creation of MBP HOB can be skipped for ADL-N based platforms. |
Kapil Porwal | 23ef60d | 2023-01-16 16:07:48 +0000 | [diff] [blame] | 534 | |
Michał Żygowski | 95be012 | 2022-10-29 21:32:54 +0200 | [diff] [blame] | 535 | config INCLUDE_HSPHY_IN_FMAP |
| 536 | bool "Include PCIe 5.0 HSPHY firmware in flash" |
| 537 | default n |
| 538 | help |
| 539 | Set this option to cache the PCIe 5.0 HSPHY firmware after it is |
| 540 | fetched from ME during boot. By default coreboot will fetch the |
| 541 | HSPHY FW from ME, but if for some reason ME is not enabled or |
| 542 | visible, the cached blob will be attempted to initialize the PCIe |
| 543 | 5.0 root port. Select it if ME is soft disabled or disabled with HAP |
| 544 | bit. If possible, the HSPHY FW will be saved to flashmap region if |
| 545 | the firmware file is not provided directly in the HSPHY_FW_FILE |
| 546 | Kconfig. |
| 547 | |
| 548 | config HSPHY_FW_FILE |
| 549 | string "HSPHY firmware file path" |
| 550 | depends on INCLUDE_HSPHY_IN_FMAP |
| 551 | help |
| 552 | Path pointing to the PCIe 5.0 HSPHY file. The file can be extracted |
| 553 | from full firmware image or ME region using UEFITool. If left empty, |
| 554 | HSPHY loading procedure will try to save the firmware to the flashmap |
| 555 | region if fetched successfully from ME. |
| 556 | |
| 557 | config HSPHY_FW_MAX_SIZE |
| 558 | hex |
| 559 | default 0x8000 |
| 560 | |
Subrata Banik | 4f7d05d | 2023-09-26 20:22:42 +0530 | [diff] [blame] | 561 | config HAVE_BMP_LOGO_COMPRESS_LZMA |
| 562 | default n |
| 563 | |
Marx Wang | 961ed9f | 2024-02-20 23:15:42 +0800 | [diff] [blame] | 564 | config SOC_INTEL_COMMON_BLOCK_ACPI_SLP_S0_FREQ_HZ |
| 565 | default 0x2005 |
| 566 | help |
| 567 | slp_s0_residency granularity in 122us ticks (i.e. ~8.2KHz). |
| 568 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 569 | endif |