Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 1 | config SOC_INTEL_ALDERLAKE |
| 2 | bool |
| 3 | help |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 4 | Intel Alderlake support. Mainboards should specify the PCH |
| 5 | type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead |
| 6 | of selecting this option directly. |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 7 | |
Bora Guvendik | 2c805b9 | 2022-06-08 15:55:52 -0700 | [diff] [blame] | 8 | config SOC_INTEL_RAPTORLAKE |
| 9 | bool |
| 10 | help |
| 11 | Intel Raptorlake support. Mainboards using RPL should select |
| 12 | SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together. |
| 13 | |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 14 | config SOC_INTEL_ALDERLAKE_PCH_M |
| 15 | bool |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 16 | select SOC_INTEL_ALDERLAKE |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 17 | help |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 18 | Choose this option if your mainboard has a PCH-M chipset. |
| 19 | |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 20 | config SOC_INTEL_ALDERLAKE_PCH_N |
| 21 | bool |
| 22 | select SOC_INTEL_ALDERLAKE |
Michał Żygowski | 6297df8 | 2022-06-30 16:22:35 +0200 | [diff] [blame] | 23 | select MICROCODE_BLOB_UNDISCLOSED |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 24 | help |
| 25 | Choose this option if your mainboard has a PCH-N chipset. |
| 26 | |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 27 | config SOC_INTEL_ALDERLAKE_PCH_P |
| 28 | bool |
| 29 | select SOC_INTEL_ALDERLAKE |
Michał Żygowski | 073779b | 2022-06-29 11:32:01 +0200 | [diff] [blame] | 30 | select HAVE_INTEL_FSP_REPO |
| 31 | select PLATFORM_USES_FSP2_3 |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 32 | help |
| 33 | Choose this option if your mainboard has a PCH-P chipset. |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 34 | |
Michał Żygowski | a1636d7 | 2022-04-07 14:56:10 +0200 | [diff] [blame] | 35 | config SOC_INTEL_ALDERLAKE_PCH_S |
| 36 | bool |
| 37 | select SOC_INTEL_ALDERLAKE |
Michał Żygowski | 073779b | 2022-06-29 11:32:01 +0200 | [diff] [blame] | 38 | select HAVE_INTEL_FSP_REPO |
| 39 | select PLATFORM_USES_FSP2_3 |
Michał Żygowski | a1636d7 | 2022-04-07 14:56:10 +0200 | [diff] [blame] | 40 | help |
| 41 | Choose this option if your mainboard has a PCH-S chipset. |
| 42 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 43 | if SOC_INTEL_ALDERLAKE |
| 44 | |
| 45 | config CPU_SPECIFIC_OPTIONS |
| 46 | def_bool y |
Angel Pons | a25eaff | 2020-09-23 15:37:15 +0200 | [diff] [blame] | 47 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Sugnan Prabhu S | dcf0459 | 2021-12-03 19:07:04 +0530 | [diff] [blame] | 48 | select ACPI_ADL_IPU_ES_SUPPORT |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 49 | select ARCH_X86 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 50 | select BOOT_DEVICE_SUPPORTS_WRITES |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 51 | select CACHE_MRC_SETTINGS |
| 52 | select CPU_INTEL_COMMON |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 53 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | 5307f12 | 2021-09-19 00:32:37 +0200 | [diff] [blame] | 54 | select CPU_SUPPORTS_INTEL_TME |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 55 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 56 | select DISPLAY_FSP_VERSION_INFO |
Eric Lai | 4ea47c3 | 2020-12-21 16:57:49 +0800 | [diff] [blame] | 57 | select DRIVERS_USB_ACPI |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 58 | select FSP_COMPRESS_FSP_S_LZ4 |
Subrata Banik | 683c95e | 2020-12-19 19:36:45 +0530 | [diff] [blame] | 59 | select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 60 | select FSP_M_XIP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 61 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Subrata Banik | e4cf3fa | 2022-03-23 01:41:36 +0530 | [diff] [blame] | 62 | select FSP_USES_CB_DEBUG_EVENT_HANDLER |
Subrata Banik | 298b359 | 2021-09-14 12:38:08 +0530 | [diff] [blame] | 63 | select FSPS_HAS_ARCH_UPD |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 64 | select GENERIC_GPIO_LIB |
Subrata Banik | b4a169a | 2021-12-29 18:36:23 +0000 | [diff] [blame] | 65 | select HAVE_DEBUG_RAM_SETUP |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 66 | select HAVE_FSP_GOP |
Felix Singer | a182fae | 2021-12-31 00:30:55 +0100 | [diff] [blame] | 67 | select HAVE_HYPERTHREADING |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 68 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 69 | select HAVE_SMI_HANDLER |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 70 | select IDT_IN_EVERY_STAGE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 71 | select INTEL_GMA_ACPI |
| 72 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Meera Ravindranath | 81d367f | 2021-07-08 09:39:11 +0530 | [diff] [blame] | 73 | select INTEL_GMA_OPREGION_2_1 |
Subrata Banik | 0aed4e5 | 2020-10-12 17:27:31 +0530 | [diff] [blame] | 74 | select INTEL_TME |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 75 | select MRC_SETTINGS_PROTECT |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 76 | select PARALLEL_MP_AP_WORK |
Michał Żygowski | 073779b | 2022-06-29 11:32:01 +0200 | [diff] [blame] | 77 | select PLATFORM_USES_FSP2_2 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 78 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 79 | select SOC_INTEL_COMMON |
Subrata Banik | 0808992 | 2020-10-03 13:02:06 +0530 | [diff] [blame] | 80 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 81 | select SOC_INTEL_COMMON_BLOCK |
Subrata Banik | 0808992 | 2020-10-03 13:02:06 +0530 | [diff] [blame] | 82 | select SOC_INTEL_COMMON_BLOCK_ACPI |
ravindr1 | 7459657 | 2021-03-29 19:41:25 +0530 | [diff] [blame] | 83 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC |
Sridahr Siricilla | 73b90c6 | 2021-11-11 01:10:16 +0530 | [diff] [blame] | 84 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID |
Angel Pons | 98f672a | 2021-02-19 19:42:10 +0100 | [diff] [blame] | 85 | select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
Tim Wawrzynczak | 5faee2e | 2021-07-01 08:24:18 -0600 | [diff] [blame] | 86 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP |
| 87 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ |
Subrata Banik | 21974ab | 2020-10-31 21:40:43 +0530 | [diff] [blame] | 88 | select SOC_INTEL_COMMON_BLOCK_CAR |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 89 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Varshit B Pandya | 2938c46 | 2022-02-16 20:38:10 +0530 | [diff] [blame] | 90 | select SOC_INTEL_COMMON_BLOCK_CNVI |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 91 | select SOC_INTEL_COMMON_BLOCK_CPU |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 92 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Angel Pons | a4cd911 | 2021-02-19 19:23:38 +0100 | [diff] [blame] | 93 | select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 94 | select SOC_INTEL_COMMON_BLOCK_DTT |
| 95 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Subrata Banik | af2f8b9 | 2022-01-10 10:26:52 +0000 | [diff] [blame] | 96 | select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 97 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
Krishna Prasad Bhat | 01e426d | 2022-01-16 22:37:21 +0530 | [diff] [blame] | 98 | select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 99 | select SOC_INTEL_COMMON_BLOCK_HDA |
Subrata Banik | c176fc2 | 2022-04-25 16:59:35 +0530 | [diff] [blame] | 100 | select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC |
Michał Żygowski | 3d1e562 | 2022-04-08 17:09:49 +0200 | [diff] [blame] | 101 | select SOC_INTEL_COMMON_BLOCK_IPU if !SOC_INTEL_ALDERLAKE_PCH_S |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 102 | select SOC_INTEL_COMMON_BLOCK_IRQ |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 103 | select SOC_INTEL_COMMON_BLOCK_MEMINIT |
Rizwan Qureshi | 307be99 | 2021-04-08 20:35:29 +0530 | [diff] [blame] | 104 | select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 |
Lean Sheng Tan | 7502000 | 2021-06-30 01:47:48 -0700 | [diff] [blame] | 105 | select SOC_INTEL_COMMON_BLOCK_PMC_EPOC |
Sumeet R Pawnikar | 77298c6 | 2021-03-10 21:09:37 +0530 | [diff] [blame] | 106 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 107 | select SOC_INTEL_COMMON_BLOCK_SA |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 108 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 109 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | b2e8bd8 | 2021-11-17 15:35:05 +0530 | [diff] [blame] | 110 | select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC |
Tim Wawrzynczak | 242da79 | 2020-11-10 10:13:54 -0700 | [diff] [blame] | 111 | select SOC_INTEL_COMMON_BLOCK_XHCI |
| 112 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Sridhar Siricilla | f5e94b6 | 2022-03-08 23:39:20 +0530 | [diff] [blame] | 113 | select SOC_INTEL_COMMON_BASECODE |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 114 | select SOC_INTEL_COMMON_FSP_RESET |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 115 | select SOC_INTEL_COMMON_PCH_BASE |
| 116 | select SOC_INTEL_COMMON_RESET |
MAULIK V VAGHELA | ed6f7e4 | 2022-02-22 19:59:42 +0530 | [diff] [blame] | 117 | select SOC_INTEL_CSE_SEND_EOP_EARLY |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 118 | select SOC_INTEL_CSE_SET_EOP |
Bora Guvendik | 40e461a | 2022-04-13 16:26:56 -0700 | [diff] [blame] | 119 | select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY if SOC_INTEL_CSE_LITE_SKU |
Subrata Banik | af27ac2 | 2022-02-18 00:44:15 +0530 | [diff] [blame] | 120 | select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 121 | select SSE2 |
| 122 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 123 | select TSC_MONOTONIC_TIMER |
| 124 | select UDELAY_TSC |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 125 | select UDK_202005_BINDING |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 126 | |
Michał Żygowski | 9df95d9 | 2022-04-08 17:02:35 +0200 | [diff] [blame] | 127 | config SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT |
| 128 | bool |
| 129 | default y if !SOC_INTEL_ALDERLAKE_PCH_S |
| 130 | default n if SOC_INTEL_ALDERLAKE_PCH_S |
| 131 | select SOC_INTEL_COMMON_BLOCK_TCSS |
| 132 | select SOC_INTEL_COMMON_BLOCK_USB4 |
| 133 | select SOC_INTEL_COMMON_BLOCK_USB4_PCIE |
| 134 | select SOC_INTEL_COMMON_BLOCK_USB4_XHCI |
| 135 | |
Reka Norman | e790f92 | 2022-04-06 20:33:54 +1000 | [diff] [blame] | 136 | config ALDERLAKE_CONFIGURE_DESCRIPTOR |
| 137 | bool |
| 138 | help |
| 139 | Select this if the descriptor needs to be updated at runtime. This |
| 140 | can only be done if the descriptor region is writable, and should only |
| 141 | be used as a temporary workaround. |
| 142 | |
Subrata Banik | 095e2a7 | 2021-07-05 20:56:15 +0530 | [diff] [blame] | 143 | config ALDERLAKE_CAR_ENHANCED_NEM |
| 144 | bool |
| 145 | default y if !INTEL_CAR_NEM |
| 146 | select INTEL_CAR_NEM_ENHANCED |
| 147 | select CAR_HAS_SF_MASKS |
| 148 | select COS_MAPPED_TO_MSB |
| 149 | select CAR_HAS_L3_PROTECTED_WAYS |
| 150 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 151 | config MAX_CPUS |
| 152 | int |
| 153 | default 24 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 154 | |
| 155 | config DCACHE_RAM_BASE |
| 156 | default 0xfef00000 |
| 157 | |
| 158 | config DCACHE_RAM_SIZE |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 159 | default 0xc0000 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 160 | help |
| 161 | The size of the cache-as-ram region required during bootblock |
| 162 | and/or romstage. |
| 163 | |
| 164 | config DCACHE_BSP_STACK_SIZE |
| 165 | hex |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 166 | default 0x80400 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 167 | help |
| 168 | The amount of anticipated stack usage in CAR by bootblock and |
| 169 | other stages. In the case of FSP_USES_CB_STACK default value will be |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 170 | sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 171 | (~1KiB). |
| 172 | |
| 173 | config FSP_TEMP_RAM_SIZE |
| 174 | hex |
| 175 | default 0x20000 |
| 176 | help |
| 177 | The amount of anticipated heap usage in CAR by FSP. |
| 178 | Refer to Platform FSP integration guide document to know |
| 179 | the exact FSP requirement for Heap setup. |
| 180 | |
Tim Wawrzynczak | 092813a | 2020-11-24 13:48:56 -0700 | [diff] [blame] | 181 | config CHIPSET_DEVICETREE |
| 182 | string |
Michał Kopeć | 75a49fe | 2022-04-08 11:28:45 +0200 | [diff] [blame] | 183 | default "soc/intel/alderlake/chipset_pch_s.cb" if SOC_INTEL_ALDERLAKE_PCH_S |
Tim Wawrzynczak | 092813a | 2020-11-24 13:48:56 -0700 | [diff] [blame] | 184 | default "soc/intel/alderlake/chipset.cb" |
| 185 | |
Subrata Banik | 683c95e | 2020-12-19 19:36:45 +0530 | [diff] [blame] | 186 | config EXT_BIOS_WIN_BASE |
| 187 | default 0xf8000000 |
| 188 | |
| 189 | config EXT_BIOS_WIN_SIZE |
| 190 | default 0x2000000 |
| 191 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 192 | config IFD_CHIPSET |
| 193 | string |
| 194 | default "adl" |
| 195 | |
| 196 | config IED_REGION_SIZE |
| 197 | hex |
| 198 | default 0x400000 |
| 199 | |
| 200 | config HEAP_SIZE |
| 201 | hex |
| 202 | default 0x10000 |
| 203 | |
Tim Wawrzynczak | 8d11cdc | 2021-03-12 12:46:02 -0700 | [diff] [blame] | 204 | # Intel recommends reserving the following resources per PCIe TBT root port, |
| 205 | # from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5 |
| 206 | # - 42 buses |
| 207 | # - 194 MiB Non-prefetchable memory |
| 208 | # - 448 MiB Prefetchable memory |
Furquan Shaikh | d9f5d90 | 2021-08-24 13:53:43 -0700 | [diff] [blame] | 209 | if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
Tim Wawrzynczak | 8d11cdc | 2021-03-12 12:46:02 -0700 | [diff] [blame] | 210 | |
| 211 | config PCIEXP_HOTPLUG_BUSES |
| 212 | int |
| 213 | default 42 |
| 214 | |
| 215 | config PCIEXP_HOTPLUG_MEM |
| 216 | hex |
| 217 | default 0xc200000 |
| 218 | |
| 219 | config PCIEXP_HOTPLUG_PREFETCH_MEM |
| 220 | hex |
| 221 | default 0x1c000000 |
| 222 | |
Furquan Shaikh | d9f5d90 | 2021-08-24 13:53:43 -0700 | [diff] [blame] | 223 | endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
Tim Wawrzynczak | 8d11cdc | 2021-03-12 12:46:02 -0700 | [diff] [blame] | 224 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 225 | config MAX_PCH_ROOT_PORTS |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 226 | int |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 227 | default 10 if SOC_INTEL_ALDERLAKE_PCH_M |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 228 | default 12 if SOC_INTEL_ALDERLAKE_PCH_N |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 229 | default 12 if SOC_INTEL_ALDERLAKE_PCH_P |
Michał Żygowski | 27fdfc6 | 2022-04-07 15:03:09 +0200 | [diff] [blame] | 230 | default 28 if SOC_INTEL_ALDERLAKE_PCH_S |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 231 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 232 | config MAX_CPU_ROOT_PORTS |
| 233 | int |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 234 | default 1 if SOC_INTEL_ALDERLAKE_PCH_M |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 235 | default 0 if SOC_INTEL_ALDERLAKE_PCH_N |
Michał Żygowski | 27fdfc6 | 2022-04-07 15:03:09 +0200 | [diff] [blame] | 236 | default 3 if SOC_INTEL_ALDERLAKE_PCH_P || SOC_INTEL_ALDERLAKE_PCH_S |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 237 | |
MAULIK V VAGHELA | 3e4f28f | 2022-01-21 14:17:53 +0530 | [diff] [blame] | 238 | config MAX_TBT_ROOT_PORTS |
| 239 | int |
Michał Żygowski | 27fdfc6 | 2022-04-07 15:03:09 +0200 | [diff] [blame] | 240 | default 0 if SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_ALDERLAKE_PCH_S |
MAULIK V VAGHELA | 3e4f28f | 2022-01-21 14:17:53 +0530 | [diff] [blame] | 241 | default 2 if SOC_INTEL_ALDERLAKE_PCH_M |
| 242 | default 4 if SOC_INTEL_ALDERLAKE_PCH_P |
| 243 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 244 | config MAX_ROOT_PORTS |
| 245 | int |
| 246 | default MAX_PCH_ROOT_PORTS |
| 247 | |
Subrata Banik | cffc938 | 2021-01-29 18:41:35 +0530 | [diff] [blame] | 248 | config MAX_PCIE_CLOCK_SRC |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 249 | int |
Subrata Banik | cffc938 | 2021-01-29 18:41:35 +0530 | [diff] [blame] | 250 | default 6 if SOC_INTEL_ALDERLAKE_PCH_M |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 251 | default 5 if SOC_INTEL_ALDERLAKE_PCH_N |
Michał Żygowski | 27fdfc6 | 2022-04-07 15:03:09 +0200 | [diff] [blame] | 252 | default 18 if SOC_INTEL_ALDERLAKE_PCH_S |
Cliff Huang | 0d590b7 | 2022-04-28 18:20:27 -0700 | [diff] [blame] | 253 | default 10 if SOC_INTEL_ALDERLAKE_PCH_P |
| 254 | help |
| 255 | With external clock buffer, Alderlake-P can support up to three additional source clocks. |
| 256 | This is done by setting the corresponding GPIO pin(s) to native function to use as |
| 257 | SRCCLK_OE[6..9]. In addition, SRCCLK6 does not need to be set to free running clock. |
| 258 | If any of SRCCLKReq 6..9 is asserted, SRCCLK6 will be turned on. |
Subrata Banik | cffc938 | 2021-01-29 18:41:35 +0530 | [diff] [blame] | 259 | |
| 260 | config MAX_PCIE_CLOCK_REQ |
| 261 | int |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 262 | default 6 if SOC_INTEL_ALDERLAKE_PCH_M |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 263 | default 5 if SOC_INTEL_ALDERLAKE_PCH_N |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 264 | default 10 if SOC_INTEL_ALDERLAKE_PCH_P |
Michał Żygowski | 27fdfc6 | 2022-04-07 15:03:09 +0200 | [diff] [blame] | 265 | default 18 if SOC_INTEL_ALDERLAKE_PCH_S |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 266 | |
| 267 | config SMM_TSEG_SIZE |
| 268 | hex |
| 269 | default 0x800000 |
| 270 | |
| 271 | config SMM_RESERVED_SIZE |
| 272 | hex |
| 273 | default 0x200000 |
| 274 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 275 | config PCR_BASE_ADDRESS |
| 276 | hex |
Michał Żygowski | dccfb8a | 2022-04-07 15:09:19 +0200 | [diff] [blame] | 277 | default 0xe0000000 if SOC_INTEL_ALDERLAKE_PCH_S |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 278 | default 0xfd000000 |
| 279 | help |
| 280 | This option allows you to select MMIO Base Address of sideband bus. |
| 281 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 282 | config ECAM_MMCONF_BASE_ADDRESS |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 283 | default 0xc0000000 |
| 284 | |
| 285 | config CPU_BCLK_MHZ |
| 286 | int |
| 287 | default 100 |
| 288 | |
| 289 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 290 | int |
| 291 | default 120 |
| 292 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 293 | config CPU_XTAL_HZ |
| 294 | default 38400000 |
| 295 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 296 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 297 | int |
| 298 | default 133 |
| 299 | |
| 300 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 301 | int |
| 302 | default 7 |
| 303 | |
| 304 | config SOC_INTEL_I2C_DEV_MAX |
| 305 | int |
Varshit B Pandya | 339f0e7 | 2021-07-14 11:08:23 +0530 | [diff] [blame] | 306 | default 8 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 307 | |
Sean Rhodes | 0a16291 | 2022-05-21 10:38:09 +0100 | [diff] [blame] | 308 | config SOC_INTEL_ALDERLAKE_S3 |
| 309 | bool |
| 310 | default n |
| 311 | help |
| 312 | Select if using S3 instead of S0ix to disable D3Cold. |
| 313 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 314 | config SOC_INTEL_UART_DEV_MAX |
| 315 | int |
| 316 | default 7 |
| 317 | |
| 318 | config CONSOLE_UART_BASE_ADDRESS |
| 319 | hex |
Bora Guvendik | 2a70419 | 2020-11-16 11:23:48 -0800 | [diff] [blame] | 320 | default 0xfe03e000 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 321 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 322 | |
Maulik V Vaghela | 996bab4 | 2021-02-05 12:03:19 +0530 | [diff] [blame] | 323 | config VBT_DATA_SIZE_KB |
| 324 | int |
| 325 | default 9 |
| 326 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 327 | # Clock divider parameters for 115200 baud rate |
Angel Pons | 054ff5e | 2022-06-26 10:19:53 +0200 | [diff] [blame] | 328 | # Baudrate = (UART source clock * M) /(N *16) |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 329 | # ADL UART source clock: 120MHz |
| 330 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 331 | hex |
| 332 | default 0x25a |
| 333 | |
| 334 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 335 | hex |
| 336 | default 0x7fff |
| 337 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 338 | config VBOOT |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 339 | select VBOOT_MUST_REQUEST_DISPLAY |
| 340 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 341 | select VBOOT_VBNV_CMOS |
| 342 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Subrata Banik | 3423786 | 2021-06-17 23:36:02 +0530 | [diff] [blame] | 343 | select VBOOT_X86_SHA256_ACCELERATION |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 344 | |
MAULIK V VAGHELA | 84532da | 2021-08-25 16:41:23 +0530 | [diff] [blame] | 345 | # Default hash block size is 1KiB. Increasing it to 4KiB to improve |
| 346 | # hashing time as well as read time. This helps in improving |
| 347 | # boot time for Alder Lake. |
| 348 | config VBOOT_HASH_BLOCK_SIZE |
| 349 | hex |
| 350 | default 0x1000 |
| 351 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 352 | config CBFS_SIZE |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 353 | default 0x200000 |
| 354 | |
| 355 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 356 | hex |
Subrata Banik | bf75055 | 2021-07-10 20:30:57 +0530 | [diff] [blame] | 357 | default 0x2000 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 358 | |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 359 | config FSP_HEADER_PATH |
| 360 | string "Location of FSP headers" |
Ronak Kanabar | ecdc714 | 2022-02-02 16:12:00 +0530 | [diff] [blame] | 361 | default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N |
Bora Guvendik | 2c805b9 | 2022-06-08 15:55:52 -0700 | [diff] [blame] | 362 | default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE |
Michał Żygowski | 073779b | 2022-06-29 11:32:01 +0200 | [diff] [blame] | 363 | default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P |
| 364 | default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 365 | default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" |
| 366 | |
| 367 | config FSP_FD_PATH |
| 368 | string |
| 369 | depends on FSP_USE_REPO |
Michał Żygowski | 073779b | 2022-06-29 11:32:01 +0200 | [diff] [blame] | 370 | default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P |
| 371 | default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 372 | |
| 373 | config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT |
| 374 | int "Debug Consent for ADL" |
Subrata Banik | 0cd553b | 2021-12-29 08:09:37 +0000 | [diff] [blame] | 375 | # USB DBC is more common for developers so make this default to 2 if |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 376 | # SOC_INTEL_DEBUG_CONSENT=y |
Kane Chen | 0e9a616 | 2021-11-23 14:42:48 +0800 | [diff] [blame] | 377 | default 2 if SOC_INTEL_DEBUG_CONSENT |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 378 | default 0 |
| 379 | help |
| 380 | This is to control debug interface on SOC. |
| 381 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 382 | PlatformDebugConsent in FspmUpd.h has the details. |
| 383 | |
| 384 | Desired platform debug type are |
Kane Chen | 0e9a616 | 2021-11-23 14:42:48 +0800 | [diff] [blame] | 385 | 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), |
| 386 | 7:Manual |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 387 | |
| 388 | config DATA_BUS_WIDTH |
| 389 | int |
| 390 | default 128 |
| 391 | |
| 392 | config DIMMS_PER_CHANNEL |
| 393 | int |
| 394 | default 2 |
| 395 | |
| 396 | config MRC_CHANNEL_WIDTH |
| 397 | int |
| 398 | default 16 |
| 399 | |
Sugnan Prabhu S | dcf0459 | 2021-12-03 19:07:04 +0530 | [diff] [blame] | 400 | config ACPI_ADL_IPU_ES_SUPPORT |
| 401 | def_bool n |
| 402 | help |
| 403 | Enables ACPI entry to provide silicon type information to IPU kernel driver. |
| 404 | |
Subrata Banik | ceaf9d1 | 2022-06-05 19:33:33 +0530 | [diff] [blame] | 405 | choice |
| 406 | prompt "Multiprocessor (MP) Initialization configuration to use" |
| 407 | default USE_FSP_MP_INIT |
| 408 | |
| 409 | config USE_FSP_MP_INIT |
| 410 | bool "Use FSP MP init" |
| 411 | select MP_SERVICES_PPI_V2 |
| 412 | help |
| 413 | Upon selection, coreboot brings APs from reset and the FSP runs feature programming. |
| 414 | |
| 415 | config USE_COREBOOT_MP_INIT |
| 416 | bool "Use coreboot MP init" |
| 417 | select RELOAD_MICROCODE_PATCH |
| 418 | help |
| 419 | Upon selection, coreboot performs MP Init. |
| 420 | |
| 421 | endchoice |
| 422 | |
Furquan Shaikh | f888c68 | 2021-10-05 21:37:33 -0700 | [diff] [blame] | 423 | if STITCH_ME_BIN |
| 424 | |
| 425 | config CSE_BPDT_VERSION |
| 426 | default "1.7" |
| 427 | |
| 428 | endif |
| 429 | |
Sridhar Siricilla | b24c528 | 2022-02-23 12:19:04 +0530 | [diff] [blame] | 430 | config SI_DESC_REGION |
| 431 | string "Descriptor Region name" |
| 432 | default "SI_DESC" |
| 433 | help |
| 434 | Name of Descriptor Region in the FMAP |
| 435 | |
| 436 | config SI_DESC_REGION_SZ |
| 437 | int |
| 438 | default 4096 |
| 439 | help |
| 440 | Size of Descriptor Region in the FMAP |
| 441 | |
Kangheui Won | 9678722 | 2022-06-28 15:52:43 +1000 | [diff] [blame] | 442 | config BUILDING_WITH_DEBUG_FSP |
| 443 | bool "Debug FSP is used for the build" |
| 444 | default n |
| 445 | help |
| 446 | Set this option if debug build of FSP is used. |
| 447 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 448 | endif |