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Subrata Banikb3ced6a2020-08-04 13:34:03 +05301config SOC_INTEL_ALDERLAKE
2 bool
3 help
4 Intel Alderlake support
5
Varshit Pandyab5df56f2021-01-18 09:44:35 +05306config SOC_INTEL_ALDERLAKE_PCH_M
7 bool
8 help
9 Choose this option if you have PCH-M chipset.
10
Subrata Banikb3ced6a2020-08-04 13:34:03 +053011if SOC_INTEL_ALDERLAKE
12
13config CPU_SPECIFIC_OPTIONS
14 def_bool y
Angel Ponsa25eaff2020-09-23 15:37:15 +020015 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Angel Pons8e035e32021-06-22 12:58:20 +020016 select ARCH_X86
Subrata Banikb3ced6a2020-08-04 13:34:03 +053017 select BOOT_DEVICE_SUPPORTS_WRITES
Subrata Banik292afef2020-09-09 13:34:18 +053018 select CACHE_MRC_SETTINGS
19 select CPU_INTEL_COMMON
Subrata Banik2871e0e2020-09-27 11:30:58 +053020 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
Michael Niewöhnerfe6070f2020-10-04 15:16:04 +020021 select CPU_SUPPORTS_PM_TIMER_EMULATION
Eric Lai4ea47c32020-12-21 16:57:49 +080022 select DRIVERS_USB_ACPI
Subrata Banik2871e0e2020-09-27 11:30:58 +053023 select FSP_COMPRESS_FSP_S_LZ4
Subrata Banik683c95e2020-12-19 19:36:45 +053024 select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
Subrata Banik292afef2020-09-09 13:34:18 +053025 select FSP_M_XIP
Subrata Banik4ed9f9a2020-10-31 22:01:55 +053026 select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
Subrata Banik2871e0e2020-09-27 11:30:58 +053027 select GENERIC_GPIO_LIB
28 select HAVE_FSP_GOP
Subrata Banikb3ced6a2020-08-04 13:34:03 +053029 select INTEL_DESCRIPTOR_MODE_CAPABLE
Subrata Banik2871e0e2020-09-27 11:30:58 +053030 select HAVE_SMI_HANDLER
Subrata Banikb3ced6a2020-08-04 13:34:03 +053031 select IDT_IN_EVERY_STAGE
32 select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
Subrata Banik2871e0e2020-09-27 11:30:58 +053033 select INTEL_GMA_ACPI
34 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
35 select IOAPIC
Subrata Banik0aed4e52020-10-12 17:27:31 +053036 select INTEL_TME
Aamir Bohra30cca6c2021-02-04 20:57:51 +053037 select MP_SERVICES_PPI_V2
Subrata Banik292afef2020-09-09 13:34:18 +053038 select MRC_SETTINGS_PROTECT
Subrata Banik2871e0e2020-09-27 11:30:58 +053039 select PARALLEL_MP_AP_WORK
Subrata Banikb3ced6a2020-08-04 13:34:03 +053040 select MICROCODE_BLOB_UNDISCLOSED
Subrata Banikee735942020-09-07 17:52:23 +053041 select PLATFORM_USES_FSP2_2
Subrata Banik2871e0e2020-09-27 11:30:58 +053042 select REG_SCRIPT
43 select PMC_GLOBAL_RESET_ENABLE_LOCK
44 select PMC_LOW_POWER_MODE_PROGRAM
Lean Sheng Tan508dc162021-06-16 01:32:22 -070045 select PMC_EPOC
Subrata Banikb3ced6a2020-08-04 13:34:03 +053046 select SOC_INTEL_COMMON
Subrata Banik08089922020-10-03 13:02:06 +053047 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
Subrata Banikb3ced6a2020-08-04 13:34:03 +053048 select SOC_INTEL_COMMON_BLOCK
Subrata Banik08089922020-10-03 13:02:06 +053049 select SOC_INTEL_COMMON_BLOCK_ACPI
ravindr174596572021-03-29 19:41:25 +053050 select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
Angel Pons98f672a2021-02-19 19:42:10 +010051 select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
Subrata Banik21974ab2020-10-31 21:40:43 +053052 select SOC_INTEL_COMMON_BLOCK_CAR
Subrata Banik292afef2020-09-09 13:34:18 +053053 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
Subrata Banikb3ced6a2020-08-04 13:34:03 +053054 select SOC_INTEL_COMMON_BLOCK_CPU
Subrata Banik2871e0e2020-09-27 11:30:58 +053055 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
Angel Ponsa4cd9112021-02-19 19:23:38 +010056 select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
Subrata Banik2871e0e2020-09-27 11:30:58 +053057 select SOC_INTEL_COMMON_BLOCK_DTT
58 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
Subrata Banikb3ced6a2020-08-04 13:34:03 +053059 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
Subrata Banik2871e0e2020-09-27 11:30:58 +053060 select SOC_INTEL_COMMON_BLOCK_HDA
Tim Wawrzynczak0c057c22021-03-04 10:56:28 -070061 select SOC_INTEL_COMMON_BLOCK_IPU
Tim Wawrzynczak43607e42021-05-18 09:04:42 -060062 select SOC_INTEL_COMMON_BLOCK_IRQ
Furquan Shaikha1c247b2020-12-31 22:50:14 -080063 select SOC_INTEL_COMMON_BLOCK_MEMINIT
Rizwan Qureshi307be992021-04-08 20:35:29 +053064 select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
Sumeet R Pawnikar77298c62021-03-10 21:09:37 +053065 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
Subrata Banikb3ced6a2020-08-04 13:34:03 +053066 select SOC_INTEL_COMMON_BLOCK_SA
Subrata Banik2871e0e2020-09-27 11:30:58 +053067 select SOC_INTEL_COMMON_BLOCK_SMM
68 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
Eric Lai4ea47c32020-12-21 16:57:49 +080069 select SOC_INTEL_COMMON_BLOCK_USB4
70 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
71 select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
Tim Wawrzynczak242da792020-11-10 10:13:54 -070072 select SOC_INTEL_COMMON_BLOCK_XHCI
73 select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
Subrata Banik4ed9f9a2020-10-31 22:01:55 +053074 select SOC_INTEL_COMMON_FSP_RESET
Subrata Banikb3ced6a2020-08-04 13:34:03 +053075 select SOC_INTEL_COMMON_PCH_BASE
76 select SOC_INTEL_COMMON_RESET
Tim Wawrzynczakc0e82e72021-06-17 12:42:35 -060077 select SOC_INTEL_CSE_SET_EOP
Subrata Banikb3ced6a2020-08-04 13:34:03 +053078 select SSE2
79 select SUPPORT_CPU_UCODE_IN_CBFS
80 select TSC_MONOTONIC_TIMER
81 select UDELAY_TSC
Subrata Banikee735942020-09-07 17:52:23 +053082 select UDK_202005_BINDING
Subrata Banik2871e0e2020-09-27 11:30:58 +053083 select DISPLAY_FSP_VERSION_INFO
84 select HECI_DISABLE_USING_SMM
85
86config MAX_CPUS
87 int
88 default 24
Subrata Banikb3ced6a2020-08-04 13:34:03 +053089
90config DCACHE_RAM_BASE
91 default 0xfef00000
92
93config DCACHE_RAM_SIZE
Subrata Banik191bd822020-11-21 19:30:57 +053094 default 0xc0000
Subrata Banikb3ced6a2020-08-04 13:34:03 +053095 help
96 The size of the cache-as-ram region required during bootblock
97 and/or romstage.
98
99config DCACHE_BSP_STACK_SIZE
100 hex
Subrata Banik191bd822020-11-21 19:30:57 +0530101 default 0x80400
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530102 help
103 The amount of anticipated stack usage in CAR by bootblock and
104 other stages. In the case of FSP_USES_CB_STACK default value will be
Subrata Banik191bd822020-11-21 19:30:57 +0530105 sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530106 (~1KiB).
107
108config FSP_TEMP_RAM_SIZE
109 hex
110 default 0x20000
111 help
112 The amount of anticipated heap usage in CAR by FSP.
113 Refer to Platform FSP integration guide document to know
114 the exact FSP requirement for Heap setup.
115
Tim Wawrzynczak092813a2020-11-24 13:48:56 -0700116config CHIPSET_DEVICETREE
117 string
118 default "soc/intel/alderlake/chipset.cb"
119
Subrata Banik683c95e2020-12-19 19:36:45 +0530120config EXT_BIOS_WIN_BASE
121 default 0xf8000000
122
123config EXT_BIOS_WIN_SIZE
124 default 0x2000000
125
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530126config IFD_CHIPSET
127 string
128 default "adl"
129
130config IED_REGION_SIZE
131 hex
132 default 0x400000
133
134config HEAP_SIZE
135 hex
136 default 0x10000
137
Tim Wawrzynczak8d11cdc2021-03-12 12:46:02 -0700138# Intel recommends reserving the following resources per PCIe TBT root port,
139# from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5
140# - 42 buses
141# - 194 MiB Non-prefetchable memory
142# - 448 MiB Prefetchable memory
143config ADL_ENABLE_USB4_PCIE_RESOURCES
144 def_bool n
145 select PCIEXP_HOTPLUG
146
147if ADL_ENABLE_USB4_PCIE_RESOURCES
148
149config PCIEXP_HOTPLUG_BUSES
150 int
151 default 42
152
153config PCIEXP_HOTPLUG_MEM
154 hex
155 default 0xc200000
156
157config PCIEXP_HOTPLUG_PREFETCH_MEM
158 hex
159 default 0x1c000000
160
161endif # ADL_ENABLE_USB4_PCIE_RESOURCES
162
Subrata Banik85144d92021-01-09 16:17:45 +0530163config MAX_PCH_ROOT_PORTS
Subrata Banik2871e0e2020-09-27 11:30:58 +0530164 int
Varshit Pandyab5df56f2021-01-18 09:44:35 +0530165 default 10 if SOC_INTEL_ALDERLAKE_PCH_M
Subrata Banik2871e0e2020-09-27 11:30:58 +0530166 default 12
167
Subrata Banik85144d92021-01-09 16:17:45 +0530168config MAX_CPU_ROOT_PORTS
169 int
Varshit Pandyab5df56f2021-01-18 09:44:35 +0530170 default 1 if SOC_INTEL_ALDERLAKE_PCH_M
Subrata Banik85144d92021-01-09 16:17:45 +0530171 default 3
172
173config MAX_ROOT_PORTS
174 int
175 default MAX_PCH_ROOT_PORTS
176
Subrata Banikcffc9382021-01-29 18:41:35 +0530177config MAX_PCIE_CLOCK_SRC
Subrata Banik2871e0e2020-09-27 11:30:58 +0530178 int
Subrata Banikcffc9382021-01-29 18:41:35 +0530179 default 6 if SOC_INTEL_ALDERLAKE_PCH_M
180 default 7
181
182config MAX_PCIE_CLOCK_REQ
183 int
184 default 6 if SOC_INTEL_ALDERLAKE_PCH_M
185 default 10
Subrata Banik2871e0e2020-09-27 11:30:58 +0530186
187config SMM_TSEG_SIZE
188 hex
189 default 0x800000
190
191config SMM_RESERVED_SIZE
192 hex
193 default 0x200000
194
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530195config PCR_BASE_ADDRESS
196 hex
197 default 0xfd000000
198 help
199 This option allows you to select MMIO Base Address of sideband bus.
200
201config MMCONF_BASE_ADDRESS
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530202 default 0xc0000000
203
204config CPU_BCLK_MHZ
205 int
206 default 100
207
208config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
209 int
210 default 120
211
Michael Niewöhnerdadcbfb2020-10-04 14:48:05 +0200212config CPU_XTAL_HZ
213 default 38400000
214
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530215config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
216 int
217 default 133
218
219config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
220 int
221 default 7
222
223config SOC_INTEL_I2C_DEV_MAX
224 int
225 default 6
226
227config SOC_INTEL_UART_DEV_MAX
228 int
229 default 7
230
231config CONSOLE_UART_BASE_ADDRESS
232 hex
Bora Guvendik2a704192020-11-16 11:23:48 -0800233 default 0xfe03e000
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530234 depends on INTEL_LPSS_UART_FOR_CONSOLE
235
Maulik V Vaghela996bab42021-02-05 12:03:19 +0530236config VBT_DATA_SIZE_KB
237 int
238 default 9
239
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530240# Clock divider parameters for 115200 baud rate
241# Baudrate = (UART source clcok * M) /(N *16)
242# ADL UART source clock: 120MHz
243config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
244 hex
245 default 0x25a
246
247config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
248 hex
249 default 0x7fff
250
Subrata Banik292afef2020-09-09 13:34:18 +0530251config VBOOT
252 select VBOOT_SEPARATE_VERSTAGE
253 select VBOOT_MUST_REQUEST_DISPLAY
254 select VBOOT_STARTS_IN_BOOTBLOCK
255 select VBOOT_VBNV_CMOS
256 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
Subrata Banik34237862021-06-17 23:36:02 +0530257 select VBOOT_X86_SHA256_ACCELERATION
Subrata Banik292afef2020-09-09 13:34:18 +0530258
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530259config CBFS_SIZE
260 hex
261 default 0x200000
262
263config PRERAM_CBMEM_CONSOLE_SIZE
264 hex
Subrata Banikbf750552021-07-10 20:30:57 +0530265 default 0x2000
Subrata Banik2871e0e2020-09-27 11:30:58 +0530266
Subrata Banikee735942020-09-07 17:52:23 +0530267config FSP_HEADER_PATH
268 string "Location of FSP headers"
269 default "src/vendorcode/intel/fsp/fsp2_0/alderlake/"
270
271config FSP_FD_PATH
272 string
273 depends on FSP_USE_REPO
274 default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd"
Subrata Banik292afef2020-09-09 13:34:18 +0530275
276config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT
277 int "Debug Consent for ADL"
278 # USB DBC is more common for developers so make this default to 3 if
279 # SOC_INTEL_DEBUG_CONSENT=y
280 default 3 if SOC_INTEL_DEBUG_CONSENT
281 default 0
282 help
283 This is to control debug interface on SOC.
284 Setting non-zero value will allow to use DBC or DCI to debug SOC.
285 PlatformDebugConsent in FspmUpd.h has the details.
286
287 Desired platform debug type are
288 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
289 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
290 6:Enable (2-wire DCI OOB), 7:Manual
Furquan Shaikha1c247b2020-12-31 22:50:14 -0800291
292config DATA_BUS_WIDTH
293 int
294 default 128
295
296config DIMMS_PER_CHANNEL
297 int
298 default 2
299
300config MRC_CHANNEL_WIDTH
301 int
302 default 16
303
Francois Toguocea4f922021-04-16 21:20:39 -0700304config SOC_INTEL_CRASHLOG
305 def_bool n
306 select SOC_INTEL_COMMON_BLOCK_CRASHLOG
307 select ACPI_BERT
308 help
309 Enables CrashLog.
310
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530311endif