Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2 | |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 3 | #include <assert.h> |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 4 | #include <stdint.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 7 | #include <console/console.h> |
| 8 | #include <commonlib/helpers.h> |
| 9 | #include <delay.h> |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 10 | #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 11 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 12 | #else |
| 13 | #include <southbridge/intel/i82801jx/i82801jx.h> |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 14 | #endif |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 15 | #include <string.h> |
Angel Pons | 41e66ac | 2020-09-15 13:17:23 +0200 | [diff] [blame] | 16 | #include "raminit.h" |
Martin Roth | cbe3892 | 2016-01-05 19:40:41 -0700 | [diff] [blame] | 17 | #include "x4x.h" |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 18 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 19 | #define ME_UMA_SIZEMB 0 |
| 20 | |
Elyes HAOUAS | e951e8e | 2019-06-15 11:03:00 +0200 | [diff] [blame] | 21 | u32 fsb_to_mhz(u32 speed) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 22 | { |
| 23 | return (speed * 267) + 800; |
| 24 | } |
| 25 | |
Elyes HAOUAS | e951e8e | 2019-06-15 11:03:00 +0200 | [diff] [blame] | 26 | u32 ddr_to_mhz(u32 speed) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 27 | { |
| 28 | static const u16 mhz[] = { 0, 0, 667, 800, 1067, 1333 }; |
| 29 | |
Jacob Garber | 5033d6c | 2019-06-11 15:23:23 -0600 | [diff] [blame] | 30 | if (speed <= 1 || speed >= ARRAY_SIZE(mhz)) |
| 31 | die("RAM init: invalid memory speed %u\n", speed); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 32 | |
| 33 | return mhz[speed]; |
| 34 | } |
| 35 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 36 | static void program_crossclock(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 37 | { |
| 38 | u8 i, j; |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 39 | u32 reg32; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 40 | mchbar_setbits16(0xc1c, 1 << 15); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 41 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 42 | static const u32 clkxtab[6][3][13] = { |
Arthur Heymans | 8a3514d | 2016-10-27 23:56:08 +0200 | [diff] [blame] | 43 | /* MEMCLK 400 N/A */ |
| 44 | {{}, {}, {} }, |
| 45 | /* MEMCLK 533 N/A */ |
| 46 | {{}, {}, {} }, |
| 47 | /* MEMCLK 667 |
| 48 | * FSB 800 */ |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 49 | {{0x1f1f1f1f, 0x0d07070b, 0x00000000, 0x10000000, |
Arthur Heymans | 8a3514d | 2016-10-27 23:56:08 +0200 | [diff] [blame] | 50 | 0x20010208, 0x04080000, 0x10010002, 0x00000000, |
| 51 | 0x00000000, 0x02000000, 0x04000100, 0x08000000, |
| 52 | 0x10200204}, |
| 53 | /* FSB 1067 */ |
| 54 | {0x6d5b1f1f, 0x0f0f0f0f, 0x00000000, 0x20000000, |
| 55 | 0x80020410, 0x02040008, 0x10000100, 0x00000000, |
| 56 | 0x00000000, 0x04000000, 0x08000102, 0x20000000, |
| 57 | 0x40010208}, |
| 58 | /* FSB 1333 */ |
| 59 | {0x05050303, 0xffffffff, 0xffff0000, 0x00000000, |
| 60 | 0x08020000, 0x00000000, 0x00020001, 0x00000000, |
| 61 | 0x00000000, 0x00000000, 0x08010204, 0x00000000, |
| 62 | 0x04010000} }, |
| 63 | /* MEMCLK 800 |
| 64 | * FSB 800 */ |
| 65 | {{0xffffffff, 0x05030305, 0x0000ffff, 0x0000000, |
| 66 | 0x08010204, 0x00000000, 0x08010204, 0x0000000, |
| 67 | 0x00000000, 0x00000000, 0x00020001, 0x0000000, |
| 68 | 0x04080102}, |
| 69 | /* FSB 1067 */ |
| 70 | {0x07070707, 0x06030303, 0x00000000, 0x00000000, |
| 71 | 0x08010200, 0x00000000, 0x04000102, 0x00000000, |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 72 | 0x00000000, 0x00000000, 0x00020100, 0x00000000, |
| 73 | 0x04080100}, |
Arthur Heymans | 8a3514d | 2016-10-27 23:56:08 +0200 | [diff] [blame] | 74 | /* FSB 1333 */ |
| 75 | {0x0d0b0707, 0x3e1f1f2f, 0x01010000, 0x00000000, |
| 76 | 0x10020400, 0x02000000, 0x00040100, 0x00000000, |
| 77 | 0x00000000, 0x04080000, 0x00100102, 0x00000000, |
| 78 | 0x08100200} }, |
| 79 | /* MEMCLK 1067 */ |
| 80 | {{}, |
| 81 | /* FSB 1067 */ |
| 82 | {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000, |
| 83 | 0x04080102, 0x00000000, 0x08010204, 0x00000000, |
| 84 | 0x00000000, 0x00000000, 0x00020001, 0x00000000, |
| 85 | 0x02040801}, |
| 86 | /* FSB 1333 */ |
| 87 | {0x0f0f0f0f, 0x5b1f1f6d, 0x00000000, 0x00000000, |
| 88 | 0x08010204, 0x04000000, 0x00080102, 0x00000000, |
| 89 | 0x00000000, 0x02000408, 0x00100001, 0x00000000, |
| 90 | 0x04080102} }, |
| 91 | /* MEMCLK 1333 */ |
| 92 | {{}, {}, |
| 93 | /* FSB 1333 */ |
| 94 | {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000, |
| 95 | 0x04080102, 0x00000000, 0x04080102, 0x00000000, |
| 96 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 97 | 0x02040801} } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 98 | }; |
| 99 | |
| 100 | i = (u8)s->selected_timings.mem_clk; |
| 101 | j = (u8)s->selected_timings.fsb_clk; |
| 102 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 103 | mchbar_write32(0xc04, clkxtab[i][j][0]); |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 104 | reg32 = clkxtab[i][j][1]; |
| 105 | if (s->spd_type == DDR3 && s->max_fsb == FSB_CLOCK_1333MHz |
| 106 | && s->selected_timings.mem_clk == MEM_CLOCK_800MHz) { |
| 107 | reg32 &= ~(0xff << 24); |
| 108 | reg32 |= 0x3d << 24; |
| 109 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 110 | mchbar_write32(0xc50, reg32); |
| 111 | mchbar_write32(0xc54, clkxtab[i][j][2]); |
| 112 | mchbar_setbits8(0xc08, 1 << 7); |
| 113 | mchbar_write32(0x6d8, clkxtab[i][j][3]); |
| 114 | mchbar_write32(0x6e0, clkxtab[i][j][3]); |
| 115 | mchbar_write32(0x6dc, clkxtab[i][j][4]); |
| 116 | mchbar_write32(0x6e4, clkxtab[i][j][4]); |
| 117 | mchbar_write32(0x6e8, clkxtab[i][j][5]); |
| 118 | mchbar_write32(0x6f0, clkxtab[i][j][5]); |
| 119 | mchbar_write32(0x6ec, clkxtab[i][j][6]); |
| 120 | mchbar_write32(0x6f4, clkxtab[i][j][6]); |
| 121 | mchbar_write32(0x6f8, clkxtab[i][j][7]); |
| 122 | mchbar_write32(0x6fc, clkxtab[i][j][8]); |
| 123 | mchbar_write32(0x708, clkxtab[i][j][11]); |
| 124 | mchbar_write32(0x70c, clkxtab[i][j][12]); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 125 | } |
| 126 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 127 | static void setioclk_dram(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 128 | { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 129 | mchbar_write32(0x1bc, 0x08060402); |
| 130 | mchbar_setbits16(0x1c0, 1 << 9); |
| 131 | mchbar_setbits16(0x1c0, 1 << 8); |
| 132 | mchbar_setbits16(0x1c0, 1 << 5); |
| 133 | mchbar_clrbits16(0x1c0, 1 << 0); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 134 | switch (s->selected_timings.mem_clk) { |
| 135 | default: |
| 136 | case MEM_CLOCK_800MHz: |
| 137 | case MEM_CLOCK_1066MHz: |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 138 | mchbar_setbits8(0x5d9, 1 << 1); |
| 139 | mchbar_setbits8(0x9d9, 1 << 1); |
| 140 | mchbar_clrsetbits8(0x189, 0xf0, 0xc0); |
| 141 | mchbar_clrsetbits8(0x189, 0xf0, 0xe0); |
| 142 | mchbar_clrsetbits8(0x189, 0xf0, 0xa0); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 143 | break; |
| 144 | case MEM_CLOCK_667MHz: |
| 145 | case MEM_CLOCK_1333MHz: |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 146 | mchbar_clrbits8(0x5d9, 1 << 1); |
| 147 | mchbar_clrbits8(0x9d9, 1 << 1); |
| 148 | mchbar_clrsetbits8(0x189, 0xf0, 0x40); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 149 | break; |
| 150 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 151 | mchbar_setbits32(0x594, 1 << 31); |
| 152 | mchbar_setbits32(0x994, 1 << 31); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 153 | } |
| 154 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 155 | static void launch_dram(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 156 | { |
| 157 | u8 i; |
Arthur Heymans | 7a3a319 | 2017-05-15 10:26:29 +0200 | [diff] [blame] | 158 | u32 launch1; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 159 | u32 launch2 = 0; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 160 | |
Arthur Heymans | 7a3a319 | 2017-05-15 10:26:29 +0200 | [diff] [blame] | 161 | static const u32 ddr3_launch1_tab[2][3] = { |
| 162 | /* 1N */ |
| 163 | {0x58000007, /* DDR3 800 */ |
| 164 | 0x58000007, /* DDR3 1067 */ |
| 165 | 0x58100107}, /* DDR3 1333 */ |
| 166 | /* 2N */ |
| 167 | {0x58001117, /* DDR3 800 */ |
| 168 | 0x58001117, /* DDR3 1067 */ |
| 169 | 0x58001117} /* DDR3 1333 */ |
| 170 | }; |
| 171 | |
| 172 | static const u32 ddr3_launch2_tab[2][3][6] = { |
| 173 | { /* 1N */ |
| 174 | /* DDR3 800 */ |
| 175 | {0x08030000, /* CL = 5 */ |
| 176 | 0x0C040100}, /* CL = 6 */ |
| 177 | /* DDR3 1066 */ |
| 178 | {0x00000000, /* CL = 5 */ |
| 179 | 0x00000000, /* CL = 6 */ |
| 180 | 0x10050100, /* CL = 7 */ |
| 181 | 0x14260200}, /* CL = 8 */ |
| 182 | /* DDR3 1333 */ |
| 183 | {0x00000000, /* CL = 5 */ |
| 184 | 0x00000000, /* CL = 6 */ |
| 185 | 0x00000000, /* CL = 7 */ |
| 186 | 0x14060000, /* CL = 8 */ |
| 187 | 0x18070100, /* CL = 9 */ |
| 188 | 0x1C280200}, /* CL = 10 */ |
| 189 | |
| 190 | }, |
| 191 | { /* 2N */ |
| 192 | /* DDR3 800 */ |
| 193 | {0x00040101, /* CL = 5 */ |
| 194 | 0x00250201}, /* CL = 6 */ |
| 195 | /* DDR3 1066 */ |
| 196 | {0x00000000, /* CL = 5 */ |
| 197 | 0x00050101, /* CL = 6 */ |
| 198 | 0x04260201, /* CL = 7 */ |
| 199 | 0x08470301}, /* CL = 8 */ |
| 200 | /* DDR3 1333 */ |
| 201 | {0x00000000, /* CL = 5 */ |
| 202 | 0x00000000, /* CL = 6 */ |
| 203 | 0x00000000, /* CL = 7 */ |
| 204 | 0x08070100, /* CL = 8 */ |
| 205 | 0x0C280200, /* CL = 9 */ |
| 206 | 0x10490300} /* CL = 10 */ |
| 207 | } |
| 208 | }; |
| 209 | |
| 210 | if (s->spd_type == DDR2) { |
| 211 | launch1 = 0x58001117; |
| 212 | if (s->selected_timings.CAS == 5) |
| 213 | launch2 = 0x00220201; |
| 214 | else if (s->selected_timings.CAS == 6) |
| 215 | launch2 = 0x00230302; |
| 216 | else |
| 217 | die("Unsupported CAS\n"); |
| 218 | } else { /* DDR3 */ |
| 219 | /* Default 2N mode */ |
| 220 | s->nmode = 2; |
| 221 | |
| 222 | if (s->selected_timings.mem_clk <= MEM_CLOCK_1066MHz) |
| 223 | s->nmode = 1; |
Elyes HAOUAS | 6538d91 | 2021-01-16 15:01:23 +0100 | [diff] [blame] | 224 | /* 2N on DDR3 1066 with 2 dimms per channel */ |
Arthur Heymans | 7a3a319 | 2017-05-15 10:26:29 +0200 | [diff] [blame] | 225 | if ((s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) && |
| 226 | (BOTH_DIMMS_ARE_POPULATED(s->dimms, 0) || |
| 227 | BOTH_DIMMS_ARE_POPULATED(s->dimms, 1))) |
| 228 | s->nmode = 2; |
| 229 | launch1 = ddr3_launch1_tab[s->nmode - 1] |
| 230 | [s->selected_timings.mem_clk - MEM_CLOCK_800MHz]; |
| 231 | launch2 = ddr3_launch2_tab[s->nmode - 1] |
| 232 | [s->selected_timings.mem_clk - MEM_CLOCK_800MHz] |
| 233 | [s->selected_timings.CAS - 5]; |
| 234 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 235 | |
| 236 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 237 | mchbar_write32(0x400 * i + 0x220, launch1); |
| 238 | mchbar_write32(0x400 * i + 0x224, launch2); |
| 239 | mchbar_write32(0x400 * i + 0x21c, 0); |
| 240 | mchbar_setbits32(0x400 * i + 0x248, 1 << 23); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 241 | } |
| 242 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 243 | mchbar_clrsetbits32(0x2c0, 0x58 << 24, 0x48 << 24); |
| 244 | mchbar_setbits32(0x2c0, 0xf << 5); |
| 245 | mchbar_clrsetbits32(0x2c4, 0xf, 0xc); |
Arthur Heymans | 7a3a319 | 2017-05-15 10:26:29 +0200 | [diff] [blame] | 246 | if (s->spd_type == DDR3) |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 247 | mchbar_setbits32(0x2c4, 1 << 8); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 248 | } |
| 249 | |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 250 | static void write_txdll_tap_pi(u8 ch, u16 reg, u8 tap, u8 pi) |
| 251 | { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 252 | mchbar_clrsetbits8(0x400 * ch + reg, 0x7f, pi << 4 | tap); |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 253 | } |
| 254 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 255 | static void clkset0(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 256 | { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 257 | mchbar_clrsetbits16(0x400 * ch + 0x5a0, 0xc440, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 258 | (setting->clk_delay << 14) | |
| 259 | (setting->db_sel << 6) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 260 | (setting->db_en << 10)); |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 261 | write_txdll_tap_pi(ch, 0x581, setting->tap, setting->pi); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 262 | } |
| 263 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 264 | static void clkset1(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 265 | { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 266 | mchbar_clrsetbits32(0x400 * ch + 0x5a0, 0x30880, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 267 | (setting->clk_delay << 16) | |
| 268 | (setting->db_sel << 7) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 269 | (setting->db_en << 11)); |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 270 | write_txdll_tap_pi(ch, 0x582, setting->tap, setting->pi); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 271 | } |
| 272 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 273 | static void ctrlset0(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 274 | { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 275 | mchbar_clrsetbits32(0x400 * ch + 0x59c, 0x3300000, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 276 | (setting->clk_delay << 24) | |
| 277 | (setting->db_sel << 20) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 278 | (setting->db_en << 21)); |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 279 | write_txdll_tap_pi(ch, 0x584, setting->tap, setting->pi); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 280 | } |
| 281 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 282 | static void ctrlset1(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 283 | { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 284 | mchbar_clrsetbits32(0x400 * ch + 0x59c, 0x18c00000, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 285 | (setting->clk_delay << 27) | |
| 286 | (setting->db_sel << 22) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 287 | (setting->db_en << 23)); |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 288 | write_txdll_tap_pi(ch, 0x585, setting->tap, setting->pi); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 289 | } |
| 290 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 291 | static void ctrlset2(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 292 | { |
Angel Pons | 22fd0dc | 2021-01-13 14:27:14 +0100 | [diff] [blame] | 293 | /* |
| 294 | * MRC uses an incorrect mask when programming this register, but |
| 295 | * the reset default value is zero and it is only programmed once. |
| 296 | * As it makes no difference, we can safely use the correct mask. |
| 297 | */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 298 | mchbar_clrsetbits32(0x400 * ch + 0x598, 0xf000, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 299 | (setting->clk_delay << 14) | |
| 300 | (setting->db_sel << 12) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 301 | (setting->db_en << 13)); |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 302 | write_txdll_tap_pi(ch, 0x586, setting->tap, setting->pi); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 303 | } |
| 304 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 305 | static void ctrlset3(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 306 | { |
Angel Pons | 22fd0dc | 2021-01-13 14:27:14 +0100 | [diff] [blame] | 307 | /* |
| 308 | * MRC uses an incorrect mask when programming this register, but |
| 309 | * the reset default value is zero and it is only programmed once. |
| 310 | * As it makes no difference, we can safely use the correct mask. |
| 311 | */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 312 | mchbar_clrsetbits32(0x400 * ch + 0x598, 0xf00, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 313 | (setting->clk_delay << 10) | |
| 314 | (setting->db_sel << 8) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 315 | (setting->db_en << 9)); |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 316 | write_txdll_tap_pi(ch, 0x587, setting->tap, setting->pi); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 317 | } |
| 318 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 319 | static void cmdset(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 320 | { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 321 | mchbar_clrsetbits8(0x400 * ch + 0x598, 0x30, setting->clk_delay << 4); |
| 322 | mchbar_clrsetbits8(0x400 * ch + 0x594, 0x60, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 323 | (setting->db_sel << 5) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 324 | (setting->db_en << 6)); |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 325 | write_txdll_tap_pi(ch, 0x580, setting->tap, setting->pi); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 326 | } |
| 327 | |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 328 | /** |
| 329 | * All finer DQ and DQS DLL settings are set to the same value |
| 330 | * for each rank in a channel, while coarse is common. |
| 331 | */ |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 332 | void dqsset(u8 ch, u8 lane, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 333 | { |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 334 | int rank; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 335 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 336 | mchbar_clrsetbits32(0x400 * ch + 0x5fc, 1 << (lane * 4 + 1), |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 337 | setting->coarse << (lane * 4 + 1)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 338 | |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 339 | for (rank = 0; rank < 4; rank++) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 340 | mchbar_clrsetbits32(0x400 * ch + 0x5b4 + rank * 4, 0x201 << lane, |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 341 | (setting->db_en << (9 + lane)) | |
| 342 | (setting->db_sel << lane)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 343 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 344 | mchbar_clrsetbits32(0x400 * ch + 0x5c8 + rank * 4, 0x3 << (16 + lane * 2), |
| 345 | setting->clk_delay << (16 + lane * 2)); |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 346 | |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 347 | write_txdll_tap_pi(ch, 0x520 + lane * 4 + rank, setting->tap, setting->pi); |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 348 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 349 | } |
| 350 | |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 351 | void dqset(u8 ch, u8 lane, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 352 | { |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 353 | int rank; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 354 | mchbar_clrsetbits32(0x400 * ch + 0x5fc, 1 << (lane * 4), |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 355 | setting->coarse << (lane * 4)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 356 | |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 357 | for (rank = 0; rank < 4; rank++) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 358 | mchbar_clrsetbits32(0x400 * ch + 0x5a4 + rank * 4, 0x201 << lane, |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 359 | (setting->db_en << (9 + lane)) | |
| 360 | (setting->db_sel << lane)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 361 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 362 | mchbar_clrsetbits32(0x400 * ch + 0x5c8 + rank * 4, 0x3 << (lane * 2), |
| 363 | setting->clk_delay << (2 * lane)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 364 | |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 365 | write_txdll_tap_pi(ch, 0x500 + lane * 4 + rank, setting->tap, setting->pi); |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 366 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 367 | } |
| 368 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 369 | void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting) |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 370 | { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 371 | u16 saved_tap = mchbar_read16(0x540 + 0x400 * channel + lane * 4); |
| 372 | u16 saved_pi = mchbar_read16(0x542 + 0x400 * channel + lane * 4); |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 373 | printk(RAM_SPEW, "RT DQS: ch%d, r%d, L%d: %d.%d\n", channel, rank, lane, |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 374 | dqs_setting->tap, |
| 375 | dqs_setting->pi); |
| 376 | |
| 377 | saved_tap &= ~(0xf << (rank * 4)); |
| 378 | saved_tap |= dqs_setting->tap << (rank * 4); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 379 | mchbar_write16(0x540 + 0x400 * channel + lane * 4, saved_tap); |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 380 | |
| 381 | saved_pi &= ~(0x7 << (rank * 3)); |
| 382 | saved_pi |= dqs_setting->pi << (rank * 3); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 383 | mchbar_write16(0x542 + 0x400 * channel + lane * 4, saved_pi); |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 384 | } |
| 385 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 386 | static void program_timings(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 387 | { |
| 388 | u8 i; |
| 389 | u8 twl, ta1, ta2, ta3, ta4; |
| 390 | u8 reg8; |
| 391 | u8 flag1 = 0; |
| 392 | u8 flag2 = 0; |
| 393 | u16 reg16; |
| 394 | u32 reg32; |
| 395 | u16 ddr, fsb; |
| 396 | u8 trpmod = 0; |
| 397 | u8 bankmod = 1; |
| 398 | u8 pagemod = 0; |
Arthur Heymans | eee4f6b | 2017-01-03 00:49:45 +0100 | [diff] [blame] | 399 | u8 adjusted_cas; |
| 400 | |
| 401 | adjusted_cas = s->selected_timings.CAS - 3; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 402 | |
Elyes HAOUAS | e951e8e | 2019-06-15 11:03:00 +0200 | [diff] [blame] | 403 | u16 fsb_to_ps[3] = { |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 404 | 5000, /* 800 */ |
| 405 | 3750, /* 1067 */ |
| 406 | 3000 /* 1333 */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 407 | }; |
| 408 | |
Elyes HAOUAS | e951e8e | 2019-06-15 11:03:00 +0200 | [diff] [blame] | 409 | u16 ddr_to_ps[6] = { |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 410 | 5000, /* 400 */ |
| 411 | 3750, /* 533 */ |
| 412 | 3000, /* 667 */ |
| 413 | 2500, /* 800 */ |
| 414 | 1875, /* 1067 */ |
| 415 | 1500 /* 1333 */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 416 | }; |
| 417 | |
| 418 | u16 lut1[6] = { |
| 419 | 0, |
| 420 | 0, |
| 421 | 2600, |
| 422 | 3120, |
| 423 | 4171, |
| 424 | 5200 |
| 425 | }; |
| 426 | |
Elyes HAOUAS | 68ec3eb | 2019-06-22 09:21:18 +0200 | [diff] [blame] | 427 | static const u8 ddr3_turnaround_tab[3][6][4] = { |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 428 | { /* DDR3 800 */ |
Angel Pons | 06d224f | 2021-01-13 13:05:26 +0100 | [diff] [blame] | 429 | {0x9, 0x7, 0x9, 0x7}, /* CL = 5 */ |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 430 | {0x9, 0x7, 0x8, 0x8}, /* CL = 6 */ |
| 431 | }, |
| 432 | { /* DDR3 1066 */ |
| 433 | {0x0, 0x0, 0x0, 0x0}, /* CL = 5 - Not supported */ |
Angel Pons | 06d224f | 2021-01-13 13:05:26 +0100 | [diff] [blame] | 434 | {0x9, 0x7, 0x9, 0x7}, /* CL = 6 */ |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 435 | {0x9, 0x7, 0x8, 0x8}, /* CL = 7 */ |
Angel Pons | 06d224f | 2021-01-13 13:05:26 +0100 | [diff] [blame] | 436 | {0x9, 0x7, 0x7, 0x9} /* CL = 8 */ |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 437 | }, |
| 438 | { /* DDR3 1333 */ |
| 439 | {0x0, 0x0, 0x0, 0x0}, /* CL = 5 - Not supported */ |
| 440 | {0x0, 0x0, 0x0, 0x0}, /* CL = 6 - Not supported */ |
| 441 | {0x0, 0x0, 0x0, 0x0}, /* CL = 7 - Not supported */ |
Angel Pons | 06d224f | 2021-01-13 13:05:26 +0100 | [diff] [blame] | 442 | {0x9, 0x7, 0x8, 0x9}, /* CL = 8 */ |
| 443 | {0x9, 0x7, 0x7, 0xa}, /* CL = 9 */ |
| 444 | {0x9, 0x7, 0x6, 0xb}, /* CL = 10 */ |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 445 | } |
| 446 | }; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 447 | |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 448 | /* [DDR freq][0x26F & 1][pagemod] */ |
Elyes HAOUAS | 68ec3eb | 2019-06-22 09:21:18 +0200 | [diff] [blame] | 449 | static const u8 ddr2_x252_tab[2][2][2] = { |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 450 | { /* DDR2 667 */ |
| 451 | {12, 16}, |
| 452 | {14, 18} |
| 453 | }, |
| 454 | { /* DDR2 800 */ |
| 455 | {14, 18}, |
| 456 | {16, 20} |
| 457 | } |
| 458 | }; |
| 459 | |
Elyes HAOUAS | 68ec3eb | 2019-06-22 09:21:18 +0200 | [diff] [blame] | 460 | static const u8 ddr3_x252_tab[3][2][2] = { |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 461 | { /* DDR3 800 */ |
| 462 | {16, 20}, |
| 463 | {18, 22} |
| 464 | }, |
| 465 | { /* DDR3 1067 */ |
| 466 | {20, 26}, |
| 467 | {26, 26} |
| 468 | }, |
| 469 | { /* DDR3 1333 */ |
| 470 | {20, 30}, |
| 471 | {22, 32}, |
| 472 | } |
| 473 | }; |
| 474 | |
| 475 | if (s->spd_type == DDR2) { |
| 476 | ta1 = 6; |
| 477 | ta2 = 6; |
| 478 | ta3 = 5; |
| 479 | ta4 = 8; |
| 480 | } else { |
| 481 | int ddr3_idx = s->selected_timings.mem_clk - MEM_CLOCK_800MHz; |
| 482 | int cas_idx = s->selected_timings.CAS - 5; |
| 483 | ta1 = ddr3_turnaround_tab[ddr3_idx][cas_idx][0]; |
| 484 | ta2 = ddr3_turnaround_tab[ddr3_idx][cas_idx][1]; |
| 485 | ta3 = ddr3_turnaround_tab[ddr3_idx][cas_idx][2]; |
| 486 | ta4 = ddr3_turnaround_tab[ddr3_idx][cas_idx][3]; |
| 487 | } |
| 488 | |
| 489 | if (s->spd_type == DDR2) |
| 490 | twl = s->selected_timings.CAS - 1; |
| 491 | else /* DDR3 */ |
| 492 | twl = s->selected_timings.mem_clk - MEM_CLOCK_800MHz + 5; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 493 | |
| 494 | FOR_EACH_POPULATED_DIMM(s->dimms, i) { |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 495 | if (s->dimms[i].n_banks == N_BANKS_8) { |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 496 | trpmod = 1; |
| 497 | bankmod = 0; |
| 498 | } |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 499 | if (s->dimms[i].page_size == 2048) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 500 | pagemod = 1; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 501 | } |
| 502 | |
| 503 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 504 | mchbar_setbits8(0x400 * i + 0x26f, 0x3); |
| 505 | mchbar_clrsetbits8(0x400 * i + 0x228, 0x7, 0x2); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 506 | /* tWL - x ?? */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 507 | mchbar_clrsetbits8(0x400 * i + 0x240, 0xf << 4, 0 << 4); |
| 508 | mchbar_clrsetbits8(0x400 * i + 0x240, 0xf, adjusted_cas); |
| 509 | mchbar_clrsetbits16(0x400 * i + 0x265, 0x3f << 8, (adjusted_cas + 9) << 8); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 510 | |
| 511 | reg16 = (s->selected_timings.tRAS << 11) | |
| 512 | ((twl + 4 + s->selected_timings.tWR) << 6) | |
| 513 | ((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 514 | mchbar_write16(0x400 * i + 0x250, reg16); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 515 | |
| 516 | reg32 = (bankmod << 21) | |
| 517 | (s->selected_timings.tRRD << 17) | |
| 518 | (s->selected_timings.tRP << 13) | |
| 519 | ((s->selected_timings.tRP + trpmod) << 9) | |
| 520 | s->selected_timings.tRFC; |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 521 | if (bankmod == 0) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 522 | reg8 = mchbar_read8(0x400 * i + 0x26f) >> 1 & 1; |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 523 | if (s->spd_type == DDR2) |
| 524 | reg32 |= ddr2_x252_tab[s->selected_timings.mem_clk |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 525 | - MEM_CLOCK_667MHz][reg8][pagemod] << 22; |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 526 | else |
| 527 | reg32 |= ddr3_x252_tab[s->selected_timings.mem_clk |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 528 | - MEM_CLOCK_800MHz][reg8][pagemod] << 22; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 529 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 530 | mchbar_write32(0x400 * i + 0x252, reg32); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 531 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 532 | mchbar_write16(0x400 * i + 0x256, s->selected_timings.tRCD << 12 | 4 << 8 | |
| 533 | ta2 << 4 | ta4); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 534 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 535 | mchbar_write32(0x400 * i + 0x258, s->selected_timings.tRCD << 17 | |
| 536 | (twl + 4 + s->selected_timings.tWTR) << 12 | |
| 537 | ta3 << 8 | 4 << 4 | ta1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 538 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 539 | mchbar_write16(0x400 * i + 0x25b, (s->selected_timings.tRP + trpmod) << 9 | |
| 540 | s->selected_timings.tRFC); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 541 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 542 | mchbar_clrsetbits16(0x400 * i + 0x260, 0x1ff << 1, |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 543 | (s->spd_type == DDR2 ? 100 : 256) << 1); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 544 | mchbar_write8(0x400 * i + 0x264, 0xff); |
| 545 | mchbar_clrsetbits8(0x400 * i + 0x25d, 0x3f, s->selected_timings.tRAS); |
| 546 | mchbar_write16(0x400 * i + 0x244, 0x2310); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 547 | |
| 548 | switch (s->selected_timings.mem_clk) { |
| 549 | case MEM_CLOCK_667MHz: |
| 550 | reg8 = 0; |
| 551 | break; |
| 552 | default: |
| 553 | reg8 = 1; |
| 554 | break; |
| 555 | } |
| 556 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 557 | mchbar_clrsetbits8(0x400 * i + 0x246, 0x1f, (reg8 << 2) | 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 558 | |
Elyes HAOUAS | e951e8e | 2019-06-15 11:03:00 +0200 | [diff] [blame] | 559 | fsb = fsb_to_ps[s->selected_timings.fsb_clk]; |
| 560 | ddr = ddr_to_ps[s->selected_timings.mem_clk]; |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 561 | reg32 = (u32)((s->selected_timings.CAS + 7 + reg8) * ddr); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 562 | reg32 = (u32)((reg32 / fsb) << 8); |
| 563 | reg32 |= 0x0e000000; |
Elyes HAOUAS | e951e8e | 2019-06-15 11:03:00 +0200 | [diff] [blame] | 564 | if ((fsb_to_mhz(s->selected_timings.fsb_clk) / |
| 565 | ddr_to_mhz(s->selected_timings.mem_clk)) > 2) { |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 566 | reg32 |= 1 << 24; |
| 567 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 568 | mchbar_clrsetbits32(0x400 * i + 0x248, 0x0f001f00, reg32); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 569 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 570 | if (twl > 2) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 571 | flag1 = 1; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 572 | |
| 573 | if (s->selected_timings.mem_clk >= MEM_CLOCK_800MHz) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 574 | flag2 = 1; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 575 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 576 | reg16 = (u8)(twl - 1 - flag1 - flag2); |
| 577 | reg16 |= reg16 << 4; |
| 578 | if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 579 | if (reg16) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 580 | reg16--; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 581 | } |
| 582 | reg16 |= flag1 << 8; |
| 583 | reg16 |= flag2 << 9; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 584 | mchbar_clrsetbits16(0x400 * i + 0x24d, 0x1ff, reg16); |
| 585 | mchbar_write16(0x400 * i + 0x25e, 0x15a5); |
| 586 | mchbar_clrbits32(0x400 * i + 0x265, 0x1f); |
| 587 | mchbar_clrsetbits32(0x400 * i + 0x269, 0x000fffff, |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 588 | (0x3f << 14) | lut1[s->selected_timings.mem_clk]); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 589 | mchbar_setbits8(0x400 * i + 0x274, 1); |
| 590 | mchbar_clrbits8(0x400 * i + 0x24c, 3); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 591 | |
| 592 | reg16 = 0; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 593 | if (s->spd_type == DDR2) { |
| 594 | switch (s->selected_timings.mem_clk) { |
| 595 | default: |
| 596 | case MEM_CLOCK_667MHz: |
| 597 | reg16 = 0x99; |
| 598 | break; |
| 599 | case MEM_CLOCK_800MHz: |
| 600 | if (s->selected_timings.CAS == 5) |
| 601 | reg16 = 0x19a; |
| 602 | else if (s->selected_timings.CAS == 6) |
| 603 | reg16 = 0x9a; |
| 604 | break; |
| 605 | } |
| 606 | } else { /* DDR3 */ |
| 607 | switch (s->selected_timings.mem_clk) { |
| 608 | default: |
| 609 | case MEM_CLOCK_800MHz: |
| 610 | case MEM_CLOCK_1066MHz: |
| 611 | reg16 = 1; |
| 612 | break; |
| 613 | case MEM_CLOCK_1333MHz: |
| 614 | reg16 = 2; |
| 615 | break; |
| 616 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 617 | } |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 618 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 619 | reg16 &= 0x7; |
| 620 | reg16 += twl + 9; |
| 621 | reg16 <<= 10; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 622 | mchbar_clrsetbits16(0x400 * i + 0x24d, 0x1f << 10, reg16); |
| 623 | mchbar_clrsetbits8(0x400 * i + 0x267, 0x3f, 0x13); |
| 624 | mchbar_clrsetbits8(0x400 * i + 0x268, 0xff, 0x4a); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 625 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 626 | reg16 = (mchbar_read16(0x400 * i + 0x269) & 0xc000) >> 2; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 627 | reg16 += 2 << 12; |
| 628 | reg16 |= (0x15 << 6) | 0x1f; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 629 | mchbar_clrsetbits16(0x400 * i + 0x26d, 0x7fff, reg16); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 630 | |
| 631 | reg32 = (1 << 25) | (6 << 27); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 632 | mchbar_clrsetbits32(0x400 * i + 0x269, 0xfa300000, reg32); |
| 633 | mchbar_clrbits8(0x400 * i + 0x271, 1 << 7); |
| 634 | mchbar_clrbits8(0x400 * i + 0x274, 3 << 1); |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 635 | } /* END EACH POPULATED CHANNEL */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 636 | |
| 637 | reg16 = 0x1f << 5; |
| 638 | reg16 |= 0xe << 10; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 639 | mchbar_clrsetbits16(0x125, 0x1ff << 5, reg16); |
| 640 | mchbar_clrsetbits16(0x127, 0x7ff, 0x540); |
| 641 | mchbar_setbits8(0x129, 0x1f); |
| 642 | mchbar_setbits8(0x12c, 0xa0); |
| 643 | mchbar_clrsetbits32(0x241, 0x1ffff, 0x11); |
| 644 | mchbar_clrsetbits32(0x641, 0x1ffff, 0x11); |
| 645 | mchbar_clrbits8(0x246, 1 << 4); |
| 646 | mchbar_clrbits8(0x646, 1 << 4); |
| 647 | mchbar_write32(0x120, 2 << 29 | 1 << 28 | 1 << 23 | 0xd7f5f); |
| 648 | reg8 = (u8)(mchbar_read32(0x252) >> 13 & 0xf); |
| 649 | mchbar_clrsetbits8(0x12d, 0xf << 4, reg8 << 4); |
| 650 | reg8 = (u8)(mchbar_read32(0x258) >> 17 & 0xf); |
| 651 | mchbar_clrsetbits8(0x12d, 0xf << 0, reg8 << 0); |
| 652 | mchbar_write8(0x12f, 0x4c); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 653 | reg32 = (1 << 31) | (0x80 << 14) | (1 << 13) | (0xa << 9); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 654 | if (s->spd_type == DDR3) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 655 | mchbar_write8(0x114, 0x42); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 656 | reg16 = (512 - MAX(5, s->selected_timings.tRFC + 10000 |
Elyes HAOUAS | e951e8e | 2019-06-15 11:03:00 +0200 | [diff] [blame] | 657 | / ddr_to_ps[s->selected_timings.mem_clk])) |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 658 | / 2; |
| 659 | reg16 &= 0x1ff; |
| 660 | reg32 = (reg16 << 22) | (0x80 << 14) | (0xa << 9); |
| 661 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 662 | mchbar_clrsetbits32(0x6c0, 0xffffff00, reg32); |
| 663 | mchbar_clrsetbits8(0x6c4, 0x7, 0x2); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 664 | } |
| 665 | |
Nico Huber | a20a02e | 2021-03-28 18:27:08 +0200 | [diff] [blame] | 666 | const unsigned int sync_dll_max_taps = 16; |
| 667 | |
| 668 | static void sync_dll_load_tap(unsigned int tap) |
| 669 | { |
| 670 | mchbar_clrsetbits8(0x1c8, 0x1f, tap & 0x1f); |
| 671 | mchbar_setbits8(0x180, 1 << 4); |
| 672 | do {} while (mchbar_read8(0x180) & (1 << 4)); |
| 673 | } |
| 674 | |
| 675 | static bool sync_dll_test_tap(unsigned int tap, uint32_t val) |
| 676 | { |
| 677 | if (tap >= sync_dll_max_taps) |
| 678 | return false; |
| 679 | sync_dll_load_tap(tap); |
| 680 | return mchbar_read32(0x184) == val; |
| 681 | } |
| 682 | |
Nico Huber | 2bb361f | 2021-03-28 18:07:00 +0200 | [diff] [blame] | 683 | static void sync_dll_search_tap(unsigned int *tap, uint32_t val) |
Nico Huber | a20a02e | 2021-03-28 18:27:08 +0200 | [diff] [blame] | 684 | { |
| 685 | for (; *tap < sync_dll_max_taps; ++*tap) |
| 686 | if (sync_dll_test_tap(*tap, val)) |
| 687 | return; |
| 688 | } |
| 689 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 690 | static void program_dll(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 691 | { |
Nico Huber | 2bb361f | 2021-03-28 18:07:00 +0200 | [diff] [blame] | 692 | u8 i, r, reg8, clk, async = 0; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 693 | u16 reg16 = 0; |
| 694 | u32 reg32 = 0; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 695 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 696 | const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04, 0x08, 0x10 }; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 697 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 698 | mchbar_clrsetbits16(0x180, 0x7e06, 0xc04); |
| 699 | mchbar_clrsetbits16(0x182, 0x3ff, 0xc8); |
| 700 | mchbar_clrsetbits16(0x18a, 0x1f1f, 0x0f0f); |
| 701 | mchbar_clrsetbits16(0x1b4, 0x8020, 0x100); |
| 702 | mchbar_clrsetbits8(0x194, 0x77, 0x33); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 703 | switch (s->selected_timings.mem_clk) { |
| 704 | default: |
| 705 | case MEM_CLOCK_667MHz: |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 706 | case MEM_CLOCK_1333MHz: |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 707 | reg16 = (0xa << 9) | 0xa; |
| 708 | break; |
| 709 | case MEM_CLOCK_800MHz: |
| 710 | reg16 = (0x9 << 9) | 0x9; |
| 711 | break; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 712 | case MEM_CLOCK_1066MHz: |
| 713 | reg16 = (0x7 << 9) | 0x7; |
| 714 | break; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 715 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 716 | mchbar_clrsetbits16(0x19c, 0xf << 9 | 0xf, reg16); |
| 717 | mchbar_clrsetbits16(0x19c, 0x2030, 0x2010); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 718 | udelay(1); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 719 | mchbar_clrbits16(0x198, 1 << 8); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 720 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 721 | mchbar_clrsetbits16(0x1c8, 0x1f, 0xd); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 722 | |
| 723 | udelay(1); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 724 | mchbar_clrbits8(0x190, 1); |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 725 | udelay(1); /* 533ns */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 726 | mchbar_clrbits32(0x198, 0x11554000); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 727 | udelay(1); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 728 | mchbar_clrbits32(0x198, 0x1455); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 729 | udelay(1); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 730 | mchbar_clrbits8(0x583, 0x1c); |
| 731 | mchbar_clrbits8(0x983, 0x1c); |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 732 | udelay(1); /* 533ns */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 733 | mchbar_clrbits8(0x583, 0x3); |
| 734 | mchbar_clrbits8(0x983, 0x3); |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 735 | udelay(1); /* 533ns */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 736 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 737 | /* ME related */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 738 | mchbar_clrsetbits32(0x1a0, 0x7ffffff, s->spd_type == DDR2 ? 0x551803 : 0x555801); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 739 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 740 | mchbar_clrbits16(0x1b4, 0x800); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 741 | if (s->spd_type == DDR2) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 742 | mchbar_setbits8(0x1a8, 0xf0); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 743 | } else { /* DDR3 */ |
| 744 | reg8 = 0x9; /* 0x9 << 4 ?? */ |
| 745 | if (s->dimms[0].ranks == 2) |
| 746 | reg8 &= ~0x80; |
| 747 | if (s->dimms[3].ranks == 2) |
| 748 | reg8 &= ~0x10; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 749 | mchbar_clrsetbits8(0x1a8, 0xf0, reg8); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 750 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 751 | |
| 752 | FOR_EACH_CHANNEL(i) { |
| 753 | reg16 = 0; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 754 | if ((s->spd_type == DDR3) && (i == 0)) |
| 755 | reg16 = (0x3 << 12); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 756 | mchbar_clrsetbits16(0x400 * i + 0x59c, 0x3 << 12, reg16); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 757 | |
| 758 | reg32 = 0; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 759 | FOR_EACH_RANK_IN_CHANNEL(r) { |
| 760 | if (!RANK_IS_POPULATED(s->dimms, i, r)) |
| 761 | reg32 |= 0x111 << r; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 762 | } |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 763 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 764 | mchbar_clrsetbits32(0x400 * i + 0x59c, 0xfff, reg32); |
| 765 | mchbar_clrbits8(0x400 * i + 0x594, 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 766 | |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 767 | if (s->spd_type == DDR2) { |
| 768 | if (!CHANNEL_IS_POPULATED(s->dimms, i)) { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 769 | printk(BIOS_DEBUG, "No dimms in channel %d\n", i); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 770 | reg8 = 0x3f; |
| 771 | } else if (ONLY_DIMMA_IS_POPULATED(s->dimms, i)) { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 772 | printk(BIOS_DEBUG, "DimmA populated only in channel %d\n", i); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 773 | reg8 = 0x38; |
| 774 | } else if (ONLY_DIMMB_IS_POPULATED(s->dimms, i)) { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 775 | printk(BIOS_DEBUG, "DimmB populated only in channel %d\n", i); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 776 | reg8 = 0x7; |
| 777 | } else if (BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 778 | printk(BIOS_DEBUG, "Both dimms populated in channel %d\n", i); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 779 | reg8 = 0; |
| 780 | } else { |
| 781 | die("Unhandled case\n"); |
| 782 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 783 | mchbar_clrsetbits32(0x400 * i + 0x5a0, 0x3f000000, reg8 << 24); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 784 | |
| 785 | } else { /* DDR3 */ |
| 786 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 787 | mchbar_clrbits8(0x400 * i + 0x5a0 + 3, rank2clken[r + i * 4]); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 788 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 789 | } |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 790 | } /* END EACH CHANNEL */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 791 | |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 792 | if (s->spd_type == DDR2) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 793 | mchbar_setbits8(0x1a8, 1 << 0); |
| 794 | mchbar_clrbits8(0x1a8, 1 << 2); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 795 | } else { /* DDR3 */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 796 | mchbar_clrbits8(0x1a8, 1 << 0); |
| 797 | mchbar_setbits8(0x1a8, 1 << 2); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 798 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 799 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 800 | /* Update DLL timing */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 801 | mchbar_clrbits8(0x1a4, 1 << 7); |
| 802 | mchbar_setbits8(0x1a4, 1 << 6); |
| 803 | mchbar_setbits16(0x5f0, 1 << 10); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 804 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 805 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 806 | mchbar_setbits16(0x400 * i + 0x5f0, 0x3fc); |
| 807 | mchbar_clrbits32(0x400 * i + 0x5fc, 0xcccccccc); |
| 808 | mchbar_clrsetbits8(0x400 * i + 0x5d9, 0xf0, s->spd_type == DDR2 ? 0x70 : 0x60); |
| 809 | mchbar_clrsetbits16(0x400 * i + 0x590, ~0, |
| 810 | s->spd_type == DDR2 ? 0x5555 : 0xa955); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 811 | } |
| 812 | |
| 813 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Jonathan Neuschäfer | 7be74db | 2018-02-12 12:00:40 +0100 | [diff] [blame] | 814 | const struct dll_setting *setting; |
| 815 | |
Elyes HAOUAS | 0ce41f1 | 2018-11-13 10:03:31 +0100 | [diff] [blame] | 816 | switch (s->selected_timings.mem_clk) { |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 817 | default: /* Should not happen */ |
| 818 | case MEM_CLOCK_667MHz: |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 819 | setting = default_ddr2_667_ctrl; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 820 | break; |
| 821 | case MEM_CLOCK_800MHz: |
| 822 | if (s->spd_type == DDR2) |
| 823 | setting = default_ddr2_800_ctrl; |
| 824 | else |
| 825 | setting = default_ddr3_800_ctrl[s->nmode - 1]; |
| 826 | break; |
| 827 | case MEM_CLOCK_1066MHz: |
| 828 | setting = default_ddr3_1067_ctrl[s->nmode - 1]; |
| 829 | break; |
| 830 | case MEM_CLOCK_1333MHz: |
| 831 | setting = default_ddr3_1333_ctrl[s->nmode - 1]; |
| 832 | break; |
| 833 | } |
Jonathan Neuschäfer | 7be74db | 2018-02-12 12:00:40 +0100 | [diff] [blame] | 834 | |
| 835 | clkset0(i, &setting[CLKSET0]); |
| 836 | clkset1(i, &setting[CLKSET1]); |
| 837 | ctrlset0(i, &setting[CTRL0]); |
| 838 | ctrlset1(i, &setting[CTRL1]); |
| 839 | ctrlset2(i, &setting[CTRL2]); |
| 840 | ctrlset3(i, &setting[CTRL3]); |
| 841 | cmdset(i, &setting[CMD]); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 842 | } |
| 843 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 844 | /* XXX if not async mode */ |
Nico Huber | 2bb361f | 2021-03-28 18:07:00 +0200 | [diff] [blame] | 845 | unsigned int tap; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 846 | mchbar_clrbits16(0x180, 1 << 15 | 1 << 9); |
| 847 | mchbar_setbits8(0x180, 1 << 2); |
Nico Huber | 2bb361f | 2021-03-28 18:07:00 +0200 | [diff] [blame] | 848 | for (tap = 0; tap < sync_dll_max_taps; ++tap) { |
| 849 | sync_dll_search_tap(&tap, 0xffffffff); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 850 | |
Nico Huber | 2bb361f | 2021-03-28 18:07:00 +0200 | [diff] [blame] | 851 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) |
| 852 | break; |
| 853 | |
| 854 | ++tap; /* other clock speeds need a second match */ |
| 855 | if (sync_dll_test_tap(tap, 0xffffffff)) |
| 856 | break; |
| 857 | } |
| 858 | |
| 859 | /* look for a real edge if we started with a match */ |
| 860 | if (tap <= 1) { |
| 861 | unsigned int tap2 = tap + 1; |
| 862 | sync_dll_search_tap(&tap2, 0); |
| 863 | |
| 864 | for (++tap2; tap2 < sync_dll_max_taps; ++tap2) { |
| 865 | sync_dll_search_tap(&tap2, 0xffffffff); |
| 866 | |
| 867 | ++tap2; /* we need a second match */ |
| 868 | if (sync_dll_test_tap(tap2, 0xffffffff)) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 869 | break; |
Nico Huber | 2bb361f | 2021-03-28 18:07:00 +0200 | [diff] [blame] | 870 | } |
| 871 | |
| 872 | if (tap2 < sync_dll_max_taps) { |
| 873 | tap = tap2; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 874 | } else { |
Nico Huber | 2bb361f | 2021-03-28 18:07:00 +0200 | [diff] [blame] | 875 | /* Using 0 instead of the original `tap` seems |
| 876 | inconsistent, but is what the code always did. */ |
Nico Huber | a20a02e | 2021-03-28 18:27:08 +0200 | [diff] [blame] | 877 | sync_dll_load_tap(0); |
Nico Huber | 2bb361f | 2021-03-28 18:07:00 +0200 | [diff] [blame] | 878 | tap = 0; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 879 | } |
| 880 | } |
| 881 | |
Nico Huber | 2bb361f | 2021-03-28 18:07:00 +0200 | [diff] [blame] | 882 | if (tap >= sync_dll_max_taps) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 883 | mchbar_clrsetbits8(0x1c8, 0x1f, 0); |
Nico Huber | 2bb361f | 2021-03-28 18:07:00 +0200 | [diff] [blame] | 884 | tap = 0; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 885 | async = 1; |
Angel Pons | 6b17794 | 2021-01-13 17:00:48 +0100 | [diff] [blame] | 886 | printk(BIOS_NOTICE, "HMC failed, using async mode\n"); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 887 | } |
| 888 | |
Nico Huber | b6a2ebe | 2021-03-28 18:52:14 +0200 | [diff] [blame] | 889 | mchbar_clrbits8(0x180, 1 << 7); |
| 890 | |
Nico Huber | 2bb361f | 2021-03-28 18:07:00 +0200 | [diff] [blame] | 891 | if (s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) |
| 892 | sync_dll_load_tap((tap + 3) % 12); |
| 893 | |
| 894 | if (s->spd_type == DDR2 && |
| 895 | s->selected_timings.fsb_clk == FSB_CLOCK_800MHz && |
| 896 | s->selected_timings.mem_clk == MEM_CLOCK_667MHz) |
| 897 | sync_dll_load_tap((tap + 10) % 14); |
Nico Huber | b6a2ebe | 2021-03-28 18:52:14 +0200 | [diff] [blame] | 898 | |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 899 | switch (s->selected_timings.mem_clk) { |
| 900 | case MEM_CLOCK_667MHz: |
| 901 | clk = 0x1a; |
| 902 | if (async != 1) { |
| 903 | if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) |
| 904 | clk = 0x10; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 905 | } |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 906 | break; |
| 907 | case MEM_CLOCK_800MHz: |
| 908 | case MEM_CLOCK_1066MHz: |
| 909 | if (async != 1) |
| 910 | clk = 0x10; |
| 911 | else |
| 912 | clk = 0x1a; |
| 913 | break; |
| 914 | case MEM_CLOCK_1333MHz: |
| 915 | clk = 0x18; |
| 916 | break; |
| 917 | default: |
| 918 | clk = 0x1a; |
| 919 | break; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 920 | } |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 921 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 922 | reg8 = mchbar_read8(0x188) & ~1; |
| 923 | mchbar_write8(0x188, reg8); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 924 | reg8 &= ~0x3e; |
| 925 | reg8 |= clk; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 926 | mchbar_write8(0x188, reg8); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 927 | reg8 |= 1; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 928 | mchbar_write8(0x188, reg8); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 929 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 930 | if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 931 | mchbar_setbits8(0x18c, 1); |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 932 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 933 | |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 934 | static void select_default_dq_dqs_settings(struct sysinfo *s) |
| 935 | { |
| 936 | int ch, lane; |
| 937 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 938 | FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(s->dimms, ch, lane) { |
| 939 | switch (s->selected_timings.mem_clk) { |
| 940 | case MEM_CLOCK_667MHz: |
| 941 | memcpy(s->dqs_settings[ch], |
| 942 | default_ddr2_667_dqs, |
| 943 | sizeof(s->dqs_settings[ch])); |
| 944 | memcpy(s->dq_settings[ch], |
| 945 | default_ddr2_667_dq, |
| 946 | sizeof(s->dq_settings[ch])); |
| 947 | s->rt_dqs[ch][lane].tap = 7; |
| 948 | s->rt_dqs[ch][lane].pi = 2; |
| 949 | break; |
| 950 | case MEM_CLOCK_800MHz: |
| 951 | if (s->spd_type == DDR2) { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 952 | memcpy(s->dqs_settings[ch], |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 953 | default_ddr2_800_dqs, |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 954 | sizeof(s->dqs_settings[ch])); |
| 955 | memcpy(s->dq_settings[ch], |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 956 | default_ddr2_800_dq, |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 957 | sizeof(s->dq_settings[ch])); |
| 958 | s->rt_dqs[ch][lane].tap = 7; |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 959 | s->rt_dqs[ch][lane].pi = 0; |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 960 | } else { /* DDR3 */ |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 961 | memcpy(s->dqs_settings[ch], |
| 962 | default_ddr3_800_dqs[s->nmode - 1], |
| 963 | sizeof(s->dqs_settings[ch])); |
| 964 | memcpy(s->dq_settings[ch], |
| 965 | default_ddr3_800_dq[s->nmode - 1], |
| 966 | sizeof(s->dq_settings[ch])); |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 967 | s->rt_dqs[ch][lane].tap = 6; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 968 | s->rt_dqs[ch][lane].pi = 3; |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 969 | } |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 970 | break; |
| 971 | case MEM_CLOCK_1066MHz: |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 972 | memcpy(s->dqs_settings[ch], |
| 973 | default_ddr3_1067_dqs[s->nmode - 1], |
| 974 | sizeof(s->dqs_settings[ch])); |
| 975 | memcpy(s->dq_settings[ch], |
| 976 | default_ddr3_1067_dq[s->nmode - 1], |
| 977 | sizeof(s->dq_settings[ch])); |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 978 | s->rt_dqs[ch][lane].tap = 5; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 979 | s->rt_dqs[ch][lane].pi = 3; |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 980 | break; |
| 981 | case MEM_CLOCK_1333MHz: |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 982 | memcpy(s->dqs_settings[ch], |
| 983 | default_ddr3_1333_dqs[s->nmode - 1], |
| 984 | sizeof(s->dqs_settings[ch])); |
| 985 | memcpy(s->dq_settings[ch], |
| 986 | default_ddr3_1333_dq[s->nmode - 1], |
| 987 | sizeof(s->dq_settings[ch])); |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 988 | s->rt_dqs[ch][lane].tap = 7; |
| 989 | s->rt_dqs[ch][lane].pi = 0; |
| 990 | break; |
| 991 | default: /* not supported */ |
| 992 | break; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 993 | } |
| 994 | } |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 995 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 996 | |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 997 | /* |
| 998 | * It looks like only the RT DQS register for the first rank |
| 999 | * is used for all ranks. Just set all the 'unused' RT DQS registers |
| 1000 | * to the same as rank 0, out of precaution. |
| 1001 | */ |
| 1002 | static void set_all_dq_dqs_dll_settings(struct sysinfo *s) |
| 1003 | { |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1004 | /* Program DQ/DQS dll settings */ |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 1005 | int ch, lane, rank; |
| 1006 | |
| 1007 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 1008 | FOR_EACH_BYTELANE(lane) { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 1009 | FOR_EACH_RANK_IN_CHANNEL(rank) { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 1010 | rt_set_dqs(ch, lane, rank, &s->rt_dqs[ch][lane]); |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 1011 | } |
| 1012 | dqsset(ch, lane, &s->dqs_settings[ch][lane]); |
| 1013 | dqset(ch, lane, &s->dq_settings[ch][lane]); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1014 | } |
| 1015 | } |
| 1016 | } |
| 1017 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1018 | static void prog_rcomp(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1019 | { |
Arthur Heymans | 0d1c9b0 | 2017-05-15 10:40:42 +0200 | [diff] [blame] | 1020 | u8 i, j, k, reg8; |
Angel Pons | 7d3bd6b | 2021-01-13 17:57:39 +0100 | [diff] [blame] | 1021 | const u32 ddr2_x32a[8] = { 0x04040404, 0x06050505, 0x09090807, 0x0d0c0b0a, |
| 1022 | 0x04040404, 0x08070605, 0x0c0b0a09, 0x100f0e0d }; |
| 1023 | const u16 ddr2_x378[5] = { 0xaaaa, 0x7777, 0x7777, 0x7777, 0x7777 }; |
Angel Pons | a0b97f3 | 2021-01-13 17:50:27 +0100 | [diff] [blame] | 1024 | const u32 ddr2_x382[5] = { 0x02020202, 0x02020202, 0x02020202, 0x04030303, 0x04030303 }; |
| 1025 | const u32 ddr2_x386[5] = { 0x03020202, 0x03020202, 0x03020202, 0x05040404, 0x05040404 }; |
| 1026 | const u32 ddr2_x38a[5] = { 0x04040303, 0x04040303, 0x04040303, 0x07070605, 0x07070605 }; |
| 1027 | const u32 ddr2_x38e[5] = { 0x06060505, 0x06060505, 0x06060505, 0x09090808, 0x09090808 }; |
| 1028 | const u32 ddr2_x392[5] = { 0x02020202, 0x02020202, 0x02020202, 0x03030202, 0x03030202 }; |
| 1029 | const u32 ddr2_x396[5] = { 0x03030202, 0x03030202, 0x03030202, 0x05040303, 0x05040303 }; |
| 1030 | const u32 ddr2_x39a[5] = { 0x04040403, 0x04040403, 0x04040403, 0x07070605, 0x07070605 }; |
| 1031 | const u32 ddr2_x39e[5] = { 0x06060505, 0x06060505, 0x06060505, 0x08080808, 0x08080808 }; |
Arthur Heymans | 0d1c9b0 | 2017-05-15 10:40:42 +0200 | [diff] [blame] | 1032 | |
Angel Pons | 7d3bd6b | 2021-01-13 17:57:39 +0100 | [diff] [blame] | 1033 | const u32 ddr3_x32a[8] = { 0x06060606, 0x06060606, 0x0b090807, 0x12110f0d, |
| 1034 | 0x06060606, 0x08070606, 0x0d0b0a09, 0x16161511 }; |
| 1035 | const u16 ddr3_x378[5] = { 0xbbbb, 0x6666, 0x6666, 0x6666, 0x6666 }; |
| 1036 | const u32 ddr3_x382[5] = { 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434 }; |
| 1037 | const u32 ddr3_x386[5] = { 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434 }; |
| 1038 | const u32 ddr3_x38a[5] = { 0x06060605, 0x07060504, 0x07060504, 0x34343434, 0x34343434 }; |
| 1039 | const u32 ddr3_x38e[5] = { 0x09080707, 0x09090808, 0x09090808, 0x34343434, 0x34343434 }; |
| 1040 | const u32 ddr3_x392[5] = { 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434 }; |
| 1041 | const u32 ddr3_x396[5] = { 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434 }; |
| 1042 | const u32 ddr3_x39a[5] = { 0x07060606, 0x08070605, 0x08070605, 0x34343434, 0x34343434 }; |
| 1043 | const u32 ddr3_x39e[5] = { 0x09090807, 0x0b0b0a09, 0x0b0b0a09, 0x34343434, 0x34343434 }; |
Arthur Heymans | 0d1c9b0 | 2017-05-15 10:40:42 +0200 | [diff] [blame] | 1044 | |
| 1045 | const u16 *x378; |
| 1046 | const u32 *x32a, *x382, *x386, *x38a, *x38e; |
| 1047 | const u32 *x392, *x396, *x39a, *x39e; |
| 1048 | |
Angel Pons | a0b97f3 | 2021-01-13 17:50:27 +0100 | [diff] [blame] | 1049 | const u16 addr[5] = { 0x374, 0x3a2, 0x3d0, 0x3fe, 0x42c }; |
Angel Pons | 7d3bd6b | 2021-01-13 17:57:39 +0100 | [diff] [blame] | 1050 | const u8 bit[5] = { 0, 1, 1, 0, 0 }; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1051 | |
Arthur Heymans | 0d1c9b0 | 2017-05-15 10:40:42 +0200 | [diff] [blame] | 1052 | if (s->spd_type == DDR2) { |
| 1053 | x32a = ddr2_x32a; |
| 1054 | x378 = ddr2_x378; |
| 1055 | x382 = ddr2_x382; |
| 1056 | x386 = ddr2_x386; |
| 1057 | x38a = ddr2_x38a; |
| 1058 | x38e = ddr2_x38e; |
| 1059 | x392 = ddr2_x392; |
| 1060 | x396 = ddr2_x396; |
| 1061 | x39a = ddr2_x39a; |
| 1062 | x39e = ddr2_x39e; |
| 1063 | } else { /* DDR3 */ |
| 1064 | x32a = ddr3_x32a; |
| 1065 | x378 = ddr3_x378; |
| 1066 | x382 = ddr3_x382; |
| 1067 | x386 = ddr3_x386; |
| 1068 | x38a = ddr3_x38a; |
| 1069 | x38e = ddr3_x38e; |
| 1070 | x392 = ddr3_x392; |
| 1071 | x396 = ddr3_x396; |
| 1072 | x39a = ddr3_x39a; |
| 1073 | x39e = ddr3_x39e; |
| 1074 | } |
| 1075 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1076 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Angel Pons | 244391a | 2021-01-13 17:28:31 +0100 | [diff] [blame] | 1077 | /* RCOMP data group is special, program it separately */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1078 | mchbar_clrsetbits32(0x400 * i + 0x31c, 0xff000, 0xaa000); |
| 1079 | mchbar_clrsetbits16(0x400 * i + 0x320, 0xffff, 0x6666); |
Angel Pons | 244391a | 2021-01-13 17:28:31 +0100 | [diff] [blame] | 1080 | for (k = 0; k < 8; k++) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1081 | mchbar_clrsetbits32(0x400 * i + 0x32a + (k << 2), 0x3f3f3f3f, x32a[k]); |
| 1082 | mchbar_clrsetbits32(0x400 * i + 0x34a + (k << 2), 0x3f3f3f3f, x32a[k]); |
Angel Pons | 244391a | 2021-01-13 17:28:31 +0100 | [diff] [blame] | 1083 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1084 | mchbar_clrsetbits8(0x400 * i + 0x31c, 1, 0); |
Angel Pons | 244391a | 2021-01-13 17:28:31 +0100 | [diff] [blame] | 1085 | |
| 1086 | /* Now program the other RCOMP groups */ |
Angel Pons | a0b97f3 | 2021-01-13 17:50:27 +0100 | [diff] [blame] | 1087 | for (j = 0; j < ARRAY_SIZE(addr); j++) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1088 | mchbar_clrsetbits16(0x400 * i + addr[j] + 0, 0xf000, 0xa000); |
| 1089 | mchbar_clrsetbits16(0x400 * i + addr[j] + 4, 0xffff, x378[j]); |
Angel Pons | 7d3bd6b | 2021-01-13 17:57:39 +0100 | [diff] [blame] | 1090 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1091 | mchbar_clrsetbits32(0x400 * i + addr[j] + 0x0e, 0x3f3f3f3f, x382[j]); |
| 1092 | mchbar_clrsetbits32(0x400 * i + addr[j] + 0x12, 0x3f3f3f3f, x386[j]); |
| 1093 | mchbar_clrsetbits32(0x400 * i + addr[j] + 0x16, 0x3f3f3f3f, x38a[j]); |
| 1094 | mchbar_clrsetbits32(0x400 * i + addr[j] + 0x1a, 0x3f3f3f3f, x38e[j]); |
| 1095 | mchbar_clrsetbits32(0x400 * i + addr[j] + 0x1e, 0x3f3f3f3f, x392[j]); |
| 1096 | mchbar_clrsetbits32(0x400 * i + addr[j] + 0x22, 0x3f3f3f3f, x396[j]); |
| 1097 | mchbar_clrsetbits32(0x400 * i + addr[j] + 0x26, 0x3f3f3f3f, x39a[j]); |
| 1098 | mchbar_clrsetbits32(0x400 * i + addr[j] + 0x2a, 0x3f3f3f3f, x39e[j]); |
Angel Pons | 244391a | 2021-01-13 17:28:31 +0100 | [diff] [blame] | 1099 | |
| 1100 | /* Override command group strength multiplier */ |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 1101 | if (s->spd_type == DDR3 && BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1102 | mchbar_clrsetbits16(0x378 + 0x400 * i, 0xffff, 0xcccc); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1103 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1104 | mchbar_clrsetbits8(0x400 * i + addr[j], 1, bit[j]); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1105 | } |
Arthur Heymans | 0d1c9b0 | 2017-05-15 10:40:42 +0200 | [diff] [blame] | 1106 | reg8 = (s->spd_type == DDR2) ? 0x12 : 0x36; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1107 | mchbar_clrsetbits8(0x400 * i + 0x45a, 0x3f, reg8); |
| 1108 | mchbar_clrsetbits8(0x400 * i + 0x45e, 0x3f, reg8); |
| 1109 | mchbar_clrsetbits8(0x400 * i + 0x462, 0x3f, reg8); |
| 1110 | mchbar_clrsetbits8(0x400 * i + 0x466, 0x3f, reg8); |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1111 | } /* END EACH POPULATED CHANNEL */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1112 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1113 | mchbar_clrsetbits32(0x134, 0x63c00, 0x63c00); |
| 1114 | mchbar_clrsetbits16(0x174, 0x63ff, 0x63ff); |
| 1115 | mchbar_write16(0x178, 0x0135); |
| 1116 | mchbar_clrsetbits32(0x130, 0x7bdffe0, 0x7a9ffa0); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1117 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1118 | if (!CHANNEL_IS_POPULATED(s->dimms, 0)) |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1119 | mchbar_clrbits32(0x130, 1 << 27); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1120 | if (!CHANNEL_IS_POPULATED(s->dimms, 1)) |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1121 | mchbar_clrbits32(0x130, 1 << 28); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1122 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1123 | mchbar_setbits8(0x130, 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1124 | } |
| 1125 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1126 | static void program_odt(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1127 | { |
| 1128 | u8 i; |
Angel Pons | b35adab | 2021-01-13 18:08:58 +0100 | [diff] [blame] | 1129 | static const u16 ddr2_odt[16][2] = { |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1130 | { 0x0000, 0x0000 }, /* NC_NC */ |
| 1131 | { 0x0000, 0x0001 }, /* x8SS_NC */ |
| 1132 | { 0x0000, 0x0011 }, /* x8DS_NC */ |
| 1133 | { 0x0000, 0x0001 }, /* x16SS_NC */ |
| 1134 | { 0x0004, 0x0000 }, /* NC_x8SS */ |
| 1135 | { 0x0101, 0x0404 }, /* x8SS_x8SS */ |
| 1136 | { 0x0101, 0x4444 }, /* x8DS_x8SS */ |
| 1137 | { 0x0101, 0x0404 }, /* x16SS_x8SS */ |
| 1138 | { 0x0044, 0x0000 }, /* NC_x8DS */ |
| 1139 | { 0x1111, 0x0404 }, /* x8SS_x8DS */ |
| 1140 | { 0x1111, 0x4444 }, /* x8DS_x8DS */ |
| 1141 | { 0x1111, 0x0404 }, /* x16SS_x8DS */ |
| 1142 | { 0x0004, 0x0000 }, /* NC_x16SS */ |
| 1143 | { 0x0101, 0x0404 }, /* x8SS_x16SS */ |
| 1144 | { 0x0101, 0x4444 }, /* x8DS_x16SS */ |
| 1145 | { 0x0101, 0x0404 }, /* x16SS_x16SS */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1146 | }; |
| 1147 | |
Arthur Heymans | e6cc21e | 2017-05-15 10:43:20 +0200 | [diff] [blame] | 1148 | static const u16 ddr3_odt[16][2] = { |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1149 | { 0x0000, 0x0000 }, /* NC_NC */ |
| 1150 | { 0x0000, 0x0001 }, /* x8SS_NC */ |
| 1151 | { 0x0000, 0x0021 }, /* x8DS_NC */ |
| 1152 | { 0x0000, 0x0001 }, /* x16SS_NC */ |
| 1153 | { 0x0004, 0x0000 }, /* NC_x8SS */ |
| 1154 | { 0x0105, 0x0405 }, /* x8SS_x8SS */ |
| 1155 | { 0x0105, 0x4465 }, /* x8DS_x8SS */ |
| 1156 | { 0x0105, 0x0405 }, /* x16SS_x8SS */ |
| 1157 | { 0x0084, 0x0000 }, /* NC_x8DS */ |
| 1158 | { 0x1195, 0x0405 }, /* x8SS_x8DS */ |
| 1159 | { 0x1195, 0x4465 }, /* x8DS_x8DS */ |
| 1160 | { 0x1195, 0x0405 }, /* x16SS_x8DS */ |
| 1161 | { 0x0004, 0x0000 }, /* NC_x16SS */ |
| 1162 | { 0x0105, 0x0405 }, /* x8SS_x16SS */ |
| 1163 | { 0x0105, 0x4465 }, /* x8DS_x16SS */ |
| 1164 | { 0x0105, 0x0405 }, /* x16SS_x16SS */ |
Arthur Heymans | e6cc21e | 2017-05-15 10:43:20 +0200 | [diff] [blame] | 1165 | }; |
| 1166 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1167 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Arthur Heymans | e6cc21e | 2017-05-15 10:43:20 +0200 | [diff] [blame] | 1168 | if (s->spd_type == DDR2) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1169 | mchbar_write16(0x400 * i + 0x298, ddr2_odt[s->dimm_config[i]][1]); |
| 1170 | mchbar_write16(0x400 * i + 0x294, ddr2_odt[s->dimm_config[i]][0]); |
Arthur Heymans | e6cc21e | 2017-05-15 10:43:20 +0200 | [diff] [blame] | 1171 | } else { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1172 | mchbar_write16(0x400 * i + 0x298, ddr3_odt[s->dimm_config[i]][1]); |
| 1173 | mchbar_write16(0x400 * i + 0x294, ddr3_odt[s->dimm_config[i]][0]); |
Arthur Heymans | e6cc21e | 2017-05-15 10:43:20 +0200 | [diff] [blame] | 1174 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1175 | u16 reg16 = mchbar_read16(0x400 * i + 0x29c); |
Arthur Heymans | e6cc21e | 2017-05-15 10:43:20 +0200 | [diff] [blame] | 1176 | reg16 &= ~0xfff; |
| 1177 | reg16 |= (s->spd_type == DDR2 ? 0x66b : 0x778); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1178 | mchbar_write16(0x400 * i + 0x29c, reg16); |
| 1179 | mchbar_clrsetbits32(0x400 * i + 0x260, 0x70e3c00, 0x3063c00); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1180 | } |
| 1181 | } |
| 1182 | |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1183 | static void pre_jedec_memory_map(void) |
| 1184 | { |
| 1185 | /* |
| 1186 | * Configure the memory mapping in stacked mode (channel 1 being mapped |
| 1187 | * above channel 0) and with 128M per rank. |
| 1188 | * This simplifies dram trainings a lot since those need a test address. |
| 1189 | * |
| 1190 | * +-------------+ => 0 |
| 1191 | * | ch 0, rank 0| |
| 1192 | * +-------------+ => 0x8000000 (128M) |
| 1193 | * | ch 0, rank 1| |
| 1194 | * +-------------+ => 0x10000000 (256M) |
| 1195 | * | ch 0, rank 2| |
| 1196 | * +-------------+ => 0x18000000 (384M) |
| 1197 | * | ch 0, rank 3| |
| 1198 | * +-------------+ => 0x20000000 (512M) |
| 1199 | * | ch 1, rank 0| |
| 1200 | * +-------------+ => 0x28000000 (640M) |
| 1201 | * | ch 1, rank 1| |
| 1202 | * +-------------+ => 0x30000000 (768M) |
| 1203 | * | ch 1, rank 2| |
| 1204 | * +-------------+ => 0x38000000 (896M) |
| 1205 | * | ch 1, rank 3| |
| 1206 | * +-------------+ |
| 1207 | * |
| 1208 | * After all trainings are done this is set to the real values specified |
| 1209 | * by the SPD. |
| 1210 | */ |
| 1211 | /* Set rank 0-3 populated */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1212 | mchbar_clrsetbits32(C0CKECTRL, 1 << 0, 0xf << 20); |
| 1213 | mchbar_clrsetbits32(C1CKECTRL, 1 << 0, 0xf << 20); |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1214 | /* Set size of each rank to 128M */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1215 | mchbar_write16(C0DRA01, 0x0101); |
| 1216 | mchbar_write16(C0DRA23, 0x0101); |
| 1217 | mchbar_write16(C1DRA01, 0x0101); |
| 1218 | mchbar_write16(C1DRA23, 0x0101); |
| 1219 | mchbar_write16(C0DRB0, 0x0002); |
| 1220 | mchbar_write16(C0DRB1, 0x0004); |
| 1221 | mchbar_write16(C0DRB2, 0x0006); |
| 1222 | mchbar_write16(C0DRB3, 0x0008); |
| 1223 | mchbar_write16(C1DRB0, 0x0002); |
| 1224 | mchbar_write16(C1DRB1, 0x0004); |
| 1225 | mchbar_write16(C1DRB2, 0x0006); |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1226 | /* In stacked mode the last present rank on ch1 needs to have its |
| 1227 | size doubled in c1drbx */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1228 | mchbar_write16(C1DRB3, 0x0010); |
| 1229 | mchbar_setbits8(0x111, STACKED_MEM); |
| 1230 | mchbar_write32(0x104, 0); |
| 1231 | mchbar_write16(0x102, 0x400); |
| 1232 | mchbar_write8(0x110, 2 << 5 | 3 << 3); |
| 1233 | mchbar_write16(0x10e, 0); |
| 1234 | mchbar_write32(0x108, 0); |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1235 | pci_write_config16(HOST_BRIDGE, D0F0_TOLUD, 0x4000); |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1236 | /* TOM(64M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */ |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1237 | pci_write_config16(HOST_BRIDGE, D0F0_TOM, 0x10); |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1238 | /* TOUUD(1M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */ |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1239 | pci_write_config16(HOST_BRIDGE, D0F0_TOUUD, 0x0400); |
| 1240 | pci_write_config32(HOST_BRIDGE, D0F0_GBSM, 0x40000000); |
| 1241 | pci_write_config32(HOST_BRIDGE, D0F0_BGSM, 0x40000000); |
| 1242 | pci_write_config32(HOST_BRIDGE, D0F0_TSEG, 0x40000000); |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1243 | } |
| 1244 | |
| 1245 | u32 test_address(int channel, int rank) |
| 1246 | { |
| 1247 | ASSERT(channel <= 1 && rank < 4); |
| 1248 | return channel * 512 * MiB + rank * 128 * MiB; |
| 1249 | } |
| 1250 | |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1251 | /* DDR3 Rank1 Address mirror |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1252 | swap the following pins: |
| 1253 | A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1254 | static u32 mirror_shift_bit(const u32 data, u8 bit) |
| 1255 | { |
| 1256 | u32 temp0 = data, temp1 = data; |
| 1257 | temp0 &= 1 << bit; |
| 1258 | temp0 <<= 1; |
| 1259 | temp1 &= 1 << (bit + 1); |
| 1260 | temp1 >>= 1; |
| 1261 | return (data & ~(3 << bit)) | temp0 | temp1; |
| 1262 | } |
| 1263 | |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 1264 | void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1265 | { |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1266 | u32 addr = test_address(ch, r); |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1267 | u8 data8 = cmd; |
| 1268 | u32 data32; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1269 | |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1270 | if (s->spd_type == DDR3 && (r & 1) |
| 1271 | && s->dimms[ch * 2 + (r >> 1)].mirrored) { |
| 1272 | data8 = (u8)mirror_shift_bit(data8, 4); |
| 1273 | } |
| 1274 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1275 | mchbar_clrsetbits8(0x271, 0x3e, data8); |
| 1276 | mchbar_clrsetbits8(0x671, 0x3e, data8); |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1277 | data32 = val; |
| 1278 | if (s->spd_type == DDR3 && (r & 1) |
| 1279 | && s->dimms[ch * 2 + (r >> 1)].mirrored) { |
| 1280 | data32 = mirror_shift_bit(data32, 3); |
| 1281 | data32 = mirror_shift_bit(data32, 5); |
| 1282 | data32 = mirror_shift_bit(data32, 7); |
| 1283 | } |
| 1284 | data32 <<= 3; |
| 1285 | |
Arthur Heymans | 4d06ff0 | 2021-07-02 10:05:09 +0200 | [diff] [blame] | 1286 | read32p(data32 | addr); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1287 | udelay(10); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1288 | mchbar_clrsetbits8(0x271, 0x3e, NORMALOP_CMD); |
| 1289 | mchbar_clrsetbits8(0x671, 0x3e, NORMALOP_CMD); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1290 | } |
| 1291 | |
| 1292 | static void jedec_ddr2(struct sysinfo *s) |
| 1293 | { |
| 1294 | u8 i; |
| 1295 | u16 mrsval, ch, r, v; |
| 1296 | |
| 1297 | u8 odt[16][4] = { |
| 1298 | {0x00, 0x00, 0x00, 0x00}, |
| 1299 | {0x01, 0x00, 0x00, 0x00}, |
| 1300 | {0x01, 0x01, 0x00, 0x00}, |
| 1301 | {0x01, 0x00, 0x00, 0x00}, |
| 1302 | {0x00, 0x00, 0x01, 0x00}, |
| 1303 | {0x11, 0x00, 0x11, 0x00}, |
| 1304 | {0x11, 0x11, 0x11, 0x00}, |
| 1305 | {0x11, 0x00, 0x11, 0x00}, |
| 1306 | {0x00, 0x00, 0x01, 0x01}, |
| 1307 | {0x11, 0x00, 0x11, 0x11}, |
| 1308 | {0x11, 0x11, 0x11, 0x11}, |
| 1309 | {0x11, 0x00, 0x11, 0x11}, |
| 1310 | {0x00, 0x00, 0x01, 0x00}, |
| 1311 | {0x11, 0x00, 0x11, 0x00}, |
| 1312 | {0x11, 0x11, 0x11, 0x00}, |
| 1313 | {0x11, 0x00, 0x11, 0x00} |
| 1314 | }; |
| 1315 | |
| 1316 | u16 jedec[12][2] = { |
| 1317 | {NOP_CMD, 0x0}, |
| 1318 | {PRECHARGE_CMD, 0x0}, |
| 1319 | {EMRS2_CMD, 0x0}, |
| 1320 | {EMRS3_CMD, 0x0}, |
| 1321 | {EMRS1_CMD, 0x0}, |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1322 | {MRS_CMD, 0x100}, /* DLL Reset */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1323 | {PRECHARGE_CMD, 0x0}, |
| 1324 | {CBR_CMD, 0x0}, |
| 1325 | {CBR_CMD, 0x0}, |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1326 | {MRS_CMD, 0x0}, /* DLL out of reset */ |
| 1327 | {EMRS1_CMD, 0x380}, /* OCD calib default */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1328 | {EMRS1_CMD, 0x0} |
| 1329 | }; |
| 1330 | |
| 1331 | mrsval = (s->selected_timings.CAS << 4) | ((s->selected_timings.tWR - 1) << 9) | 0xb; |
| 1332 | |
| 1333 | printk(BIOS_DEBUG, "MRS...\n"); |
| 1334 | |
| 1335 | udelay(200); |
| 1336 | |
| 1337 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
| 1338 | printk(BIOS_DEBUG, "CH%d: Found Rank %d\n", ch, r); |
| 1339 | for (i = 0; i < 12; i++) { |
| 1340 | v = jedec[i][1]; |
| 1341 | switch (jedec[i][0]) { |
| 1342 | case EMRS1_CMD: |
| 1343 | v |= (odt[s->dimm_config[ch]][r] << 2); |
| 1344 | break; |
| 1345 | case MRS_CMD: |
| 1346 | v |= mrsval; |
| 1347 | break; |
| 1348 | default: |
| 1349 | break; |
| 1350 | } |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1351 | send_jedec_cmd(s, r, ch, jedec[i][0], v); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1352 | udelay(1); |
Arthur Heymans | cfa2eaa | 2017-03-20 16:32:07 +0100 | [diff] [blame] | 1353 | printk(RAM_SPEW, "Jedec step %d\n", i); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1354 | } |
| 1355 | } |
| 1356 | printk(BIOS_DEBUG, "MRS done\n"); |
| 1357 | } |
| 1358 | |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1359 | static void jedec_ddr3(struct sysinfo *s) |
| 1360 | { |
| 1361 | int ch, r, dimmconfig, cmd, ddr3_freq; |
| 1362 | |
| 1363 | u8 ddr3_emrs2_rtt_wr_config[16][4] = { /* [config][Rank] */ |
| 1364 | {0, 0, 0, 0}, /* NC_NC */ |
| 1365 | {0, 0, 0, 0}, /* x8ss_NC */ |
| 1366 | {0, 0, 0, 0}, /* x8ds_NC */ |
| 1367 | {0, 0, 0, 0}, /* x16ss_NC */ |
| 1368 | {0, 0, 0, 0}, /* NC_x8ss */ |
| 1369 | {2, 0, 2, 0}, /* x8ss_x8ss */ |
| 1370 | {2, 2, 2, 0}, /* x8ds_x8ss */ |
| 1371 | {2, 0, 2, 0}, /* x16ss_x8ss */ |
| 1372 | {0, 0, 0, 0}, /* NC_x8ss */ |
| 1373 | {2, 0, 2, 2}, /* x8ss_x8ds */ |
| 1374 | {2, 2, 2, 2}, /* x8ds_x8ds */ |
| 1375 | {2, 0, 2, 2}, /* x16ss_x8ds */ |
| 1376 | {0, 0, 0, 0}, /* NC_x16ss */ |
| 1377 | {2, 0, 2, 0}, /* x8ss_x16ss */ |
| 1378 | {2, 2, 2, 0}, /* x8ds_x16ss */ |
| 1379 | {2, 0, 2, 0}, /* x16ss_x16ss */ |
| 1380 | }; |
| 1381 | |
| 1382 | printk(BIOS_DEBUG, "MRS...\n"); |
| 1383 | |
| 1384 | ddr3_freq = s->selected_timings.mem_clk - MEM_CLOCK_800MHz; |
| 1385 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
| 1386 | printk(BIOS_DEBUG, "CH%d: Found Rank %d\n", ch, r); |
| 1387 | send_jedec_cmd(s, r, ch, NOP_CMD, 0); |
| 1388 | udelay(200); |
| 1389 | dimmconfig = s->dimm_config[ch]; |
| 1390 | cmd = ddr3_freq << 3; /* actually twl - 5 which is same */ |
| 1391 | cmd |= ddr3_emrs2_rtt_wr_config[dimmconfig][r] << 9; |
| 1392 | send_jedec_cmd(s, r, ch, EMRS2_CMD, cmd); |
| 1393 | send_jedec_cmd(s, r, ch, EMRS3_CMD, 0); |
| 1394 | cmd = ddr3_emrs1_rtt_nom_config[dimmconfig][r] << 2; |
| 1395 | /* Hardcode output drive strength to 34 Ohm / RZQ/7 (why??) */ |
| 1396 | cmd |= (1 << 1); |
| 1397 | send_jedec_cmd(s, r, ch, EMRS1_CMD, cmd); |
| 1398 | /* Burst type interleaved, burst length 8, Reset DLL, |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1399 | Precharge PD: DLL on */ |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1400 | send_jedec_cmd(s, r, ch, MRS_CMD, (1 << 3) | (1 << 8) |
| 1401 | | (1 << 12) | ((s->selected_timings.CAS - 4) << 4) |
| 1402 | | ((s->selected_timings.tWR - 4) << 9)); |
| 1403 | send_jedec_cmd(s, r, ch, ZQCAL_CMD, (1 << 10)); |
| 1404 | } |
| 1405 | printk(BIOS_DEBUG, "MRS done\n"); |
| 1406 | } |
| 1407 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1408 | static void sdram_recover_receive_enable(const struct sysinfo *s) |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1409 | { |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1410 | u32 reg32; |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1411 | u16 medium, coarse_offset; |
| 1412 | u8 pi_tap; |
| 1413 | int lane, channel; |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1414 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1415 | FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) { |
| 1416 | medium = 0; |
| 1417 | coarse_offset = 0; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1418 | reg32 = mchbar_read32(0x400 * channel + 0x248); |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1419 | reg32 &= ~0xf0000; |
| 1420 | reg32 |= s->rcven_t[channel].min_common_coarse << 16; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1421 | mchbar_write32(0x400 * channel + 0x248, reg32); |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1422 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 1423 | FOR_EACH_BYTELANE(lane) { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 1424 | medium |= s->rcven_t[channel].medium[lane] << (lane * 2); |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1425 | coarse_offset |= |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 1426 | (s->rcven_t[channel].coarse_offset[lane] & 0x3) << (lane * 2); |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1427 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1428 | pi_tap = mchbar_read8(0x400 * channel + 0x560 + lane * 4); |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1429 | pi_tap &= ~0x7f; |
| 1430 | pi_tap |= s->rcven_t[channel].tap[lane]; |
| 1431 | pi_tap |= s->rcven_t[channel].pi[lane] << 4; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1432 | mchbar_write8(0x400 * channel + 0x560 + lane * 4, pi_tap); |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1433 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1434 | mchbar_write16(0x400 * channel + 0x58c, medium); |
| 1435 | mchbar_write16(0x400 * channel + 0x5fa, coarse_offset); |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1436 | } |
| 1437 | } |
| 1438 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1439 | static void sdram_program_receive_enable(struct sysinfo *s, int fast_boot) |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1440 | { |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1441 | /* Program Receive Enable Timings */ |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1442 | if (fast_boot) |
| 1443 | sdram_recover_receive_enable(s); |
| 1444 | else |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 1445 | rcven(s); |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1446 | } |
| 1447 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1448 | static void set_dradrb(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1449 | { |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1450 | u8 map, i, ch, r, rankpop0, rankpop1, lastrank_ch1; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1451 | u32 c0dra = 0; |
| 1452 | u32 c1dra = 0; |
| 1453 | u32 c0drb = 0; |
| 1454 | u32 c1drb = 0; |
| 1455 | u32 dra; |
| 1456 | u32 dra0; |
| 1457 | u32 dra1; |
| 1458 | u16 totalmemorymb; |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1459 | u32 dual_channel_size, single_channel_size, single_channel_offset; |
| 1460 | u32 size_ch0, size_ch1, size_me; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1461 | u8 dratab[2][2][2][4] = { |
| 1462 | { |
| 1463 | { |
| 1464 | {0xff, 0xff, 0xff, 0xff}, |
| 1465 | {0xff, 0x00, 0x02, 0xff} |
| 1466 | }, |
| 1467 | { |
| 1468 | {0xff, 0x01, 0xff, 0xff}, |
| 1469 | {0xff, 0x03, 0xff, 0xff} |
| 1470 | } |
| 1471 | }, |
| 1472 | { |
| 1473 | { |
| 1474 | {0xff, 0xff, 0xff, 0xff}, |
| 1475 | {0xff, 0x04, 0x06, 0x08} |
| 1476 | }, |
| 1477 | { |
| 1478 | {0xff, 0xff, 0xff, 0xff}, |
| 1479 | {0x05, 0x07, 0x09, 0xff} |
| 1480 | } |
| 1481 | } |
| 1482 | }; |
| 1483 | |
| 1484 | u8 drbtab[10] = {0x04, 0x02, 0x08, 0x04, 0x08, 0x04, 0x10, 0x08, 0x20, 0x10}; |
| 1485 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1486 | /* DRA */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1487 | rankpop0 = 0; |
| 1488 | rankpop1 = 0; |
| 1489 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1490 | if (s->dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED |
| 1491 | && (r) < s->dimms[ch<<1].ranks) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1492 | i = ch << 1; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1493 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1494 | i = (ch << 1) + 1; |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 1495 | |
| 1496 | dra = dratab[s->dimms[i].n_banks] |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1497 | [s->dimms[i].width] |
| 1498 | [s->dimms[i].cols-9] |
| 1499 | [s->dimms[i].rows-12]; |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 1500 | if (s->dimms[i].n_banks == N_BANKS_8) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1501 | dra |= 0x80; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1502 | if (ch == 0) { |
| 1503 | c0dra |= dra << (r*8); |
| 1504 | rankpop0 |= 1 << r; |
| 1505 | } else { |
| 1506 | c1dra |= dra << (r*8); |
| 1507 | rankpop1 |= 1 << r; |
| 1508 | } |
| 1509 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1510 | mchbar_write32(0x208, c0dra); |
| 1511 | mchbar_write32(0x608, c1dra); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1512 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1513 | mchbar_clrsetbits8(0x262, 0xf0, (rankpop0 << 4) & 0xf0); |
| 1514 | mchbar_clrsetbits8(0x662, 0xf0, (rankpop1 << 4) & 0xf0); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1515 | |
Arthur Heymans | b4a7804 | 2017-12-25 20:17:41 +0100 | [diff] [blame] | 1516 | if (s->spd_type == DDR3) { |
| 1517 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
| 1518 | /* ZQCAL enable */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1519 | mchbar_setbits32(0x269 + 0x400 * ch, 1 << 26); |
Arthur Heymans | b4a7804 | 2017-12-25 20:17:41 +0100 | [diff] [blame] | 1520 | } |
| 1521 | } |
| 1522 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 1523 | if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1524 | mchbar_setbits8(0x260, 1); |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 1525 | if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) || ONLY_DIMMB_IS_POPULATED(s->dimms, 1)) |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1526 | mchbar_setbits8(0x660, 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1527 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1528 | /* DRB */ |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1529 | lastrank_ch1 = 0; |
Arthur Heymans | dfce932 | 2017-12-16 19:48:00 +0100 | [diff] [blame] | 1530 | FOR_EACH_RANK(ch, r) { |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1531 | if (ch == 0) { |
Arthur Heymans | dfce932 | 2017-12-16 19:48:00 +0100 | [diff] [blame] | 1532 | if (RANK_IS_POPULATED(s->dimms, ch, r)) { |
| 1533 | dra0 = (c0dra >> (8*r)) & 0x7f; |
| 1534 | c0drb = (u16)(c0drb + drbtab[dra0]); |
| 1535 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1536 | mchbar_write16(0x200 + 2 * r, c0drb); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1537 | } else { |
Arthur Heymans | dfce932 | 2017-12-16 19:48:00 +0100 | [diff] [blame] | 1538 | if (RANK_IS_POPULATED(s->dimms, ch, r)) { |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1539 | lastrank_ch1 = r; |
Arthur Heymans | dfce932 | 2017-12-16 19:48:00 +0100 | [diff] [blame] | 1540 | dra1 = (c1dra >> (8*r)) & 0x7f; |
| 1541 | c1drb = (u16)(c1drb + drbtab[dra1]); |
| 1542 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1543 | mchbar_write16(0x600 + 2 * r, c1drb); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1544 | } |
| 1545 | } |
| 1546 | |
| 1547 | s->channel_capacity[0] = c0drb << 6; |
| 1548 | s->channel_capacity[1] = c1drb << 6; |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1549 | |
| 1550 | /* |
| 1551 | * In stacked mode the last present rank on ch1 needs to have its |
| 1552 | * size doubled in c1drbx. All subsequent ranks need the same setting |
| 1553 | * according to: "Intel 4 Series Chipset Family Datasheet" |
| 1554 | */ |
| 1555 | if (s->stacked_mode) { |
| 1556 | for (r = lastrank_ch1; r < 4; r++) |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1557 | mchbar_write16(0x600 + 2 * r, 2 * c1drb); |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1558 | } |
| 1559 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1560 | totalmemorymb = s->channel_capacity[0] + s->channel_capacity[1]; |
| 1561 | printk(BIOS_DEBUG, "Total memory: %d + %d = %dMiB\n", |
| 1562 | s->channel_capacity[0], s->channel_capacity[1], totalmemorymb); |
| 1563 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1564 | /* Populated channel sizes in MiB */ |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1565 | size_ch0 = s->channel_capacity[0]; |
| 1566 | size_ch1 = s->channel_capacity[1]; |
| 1567 | size_me = ME_UMA_SIZEMB; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1568 | |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1569 | if (s->stacked_mode) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1570 | mchbar_setbits8(0x111, STACKED_MEM); |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1571 | } else { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1572 | mchbar_clrbits8(0x111, STACKED_MEM); |
| 1573 | mchbar_setbits8(0x111, 1 << 4); |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1574 | } |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1575 | |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1576 | if (s->stacked_mode) { |
| 1577 | dual_channel_size = 0; |
| 1578 | } else if (size_me == 0) { |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1579 | dual_channel_size = MIN(size_ch0, size_ch1) * 2; |
| 1580 | } else { |
| 1581 | if (size_ch0 == 0) { |
Elyes HAOUAS | ef90609 | 2020-02-20 19:41:17 +0100 | [diff] [blame] | 1582 | /* ME needs RAM on CH0 */ |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1583 | size_me = 0; |
| 1584 | /* TOTEST: bailout? */ |
| 1585 | } else { |
| 1586 | /* Set ME UMA size in MiB */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1587 | mchbar_write16(0x100, size_me); |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1588 | /* Set ME UMA Present bit */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1589 | mchbar_setbits8(0x111, 1 << 0); |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1590 | } |
| 1591 | dual_channel_size = MIN(size_ch0 - size_me, size_ch1) * 2; |
| 1592 | } |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1593 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1594 | mchbar_write16(0x104, dual_channel_size); |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1595 | single_channel_size = size_ch0 + size_ch1 - dual_channel_size; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1596 | mchbar_write16(0x102, single_channel_size); |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1597 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1598 | map = 0; |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1599 | if (size_ch0 == 0) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1600 | map = 0; |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1601 | else if (size_ch1 == 0) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1602 | map |= 0x20; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1603 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1604 | map |= 0x40; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1605 | |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1606 | if (dual_channel_size == 0) |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1607 | map |= 0x18; |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1608 | /* Enable flex mode, we hardcode this everywhere */ |
| 1609 | if (size_me == 0) { |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1610 | if (!(s->stacked_mode && size_ch0 != 0 && size_ch1 != 0)) { |
| 1611 | map |= 0x04; |
| 1612 | if (size_ch0 <= size_ch1) |
| 1613 | map |= 0x01; |
| 1614 | } |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1615 | } else { |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1616 | if (s->stacked_mode == 0 && size_ch0 - size_me < size_ch1) |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1617 | map |= 0x04; |
| 1618 | } |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1619 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1620 | mchbar_write8(0x110, map); |
| 1621 | mchbar_write16(0x10e, 0); |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1622 | |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1623 | /* |
| 1624 | * "108h[15:0] Single Channel Offset for Ch0" |
| 1625 | * This is the 'limit' of the part on CH0 that cannot be matched |
| 1626 | * with memory on CH1. MCHBAR16(0x10a) is where the dual channel |
| 1627 | * memory on ch0s end and MCHBAR16(0x108) is the limit of the single |
| 1628 | * channel size on ch0. |
| 1629 | */ |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1630 | if (s->stacked_mode && size_ch1 != 0) { |
| 1631 | single_channel_offset = 0; |
| 1632 | } else if (size_me == 0) { |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1633 | if (size_ch0 > size_ch1) |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 1634 | single_channel_offset = dual_channel_size / 2 + single_channel_size; |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1635 | else |
| 1636 | single_channel_offset = dual_channel_size / 2; |
| 1637 | } else { |
| 1638 | if ((size_ch0 > size_ch1) && ((map & 0x7) == 4)) |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 1639 | single_channel_offset = dual_channel_size / 2 + single_channel_size; |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1640 | else |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 1641 | single_channel_offset = dual_channel_size / 2 + size_me; |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1642 | } |
| 1643 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1644 | mchbar_write16(0x108, single_channel_offset); |
| 1645 | mchbar_write16(0x10a, dual_channel_size / 2); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1646 | } |
| 1647 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1648 | static void configure_mmap(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1649 | { |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1650 | bool reclaim; |
| 1651 | u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud; |
| 1652 | u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit; |
Arthur Heymans | 16a70a4 | 2017-09-22 12:22:24 +0200 | [diff] [blame] | 1653 | u32 mmiostart, umasizem; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1654 | u16 ggc; |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 1655 | u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, 160, 224, 352 }; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1656 | u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; |
| 1657 | |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1658 | ggc = pci_read_config16(HOST_BRIDGE, 0x52); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1659 | gfxsize = ggc2uma[(ggc & 0xf0) >> 4]; |
| 1660 | gttsize = ggc2gtt[(ggc & 0xf00) >> 8]; |
Arthur Heymans | d522db0 | 2018-08-06 15:50:54 +0200 | [diff] [blame] | 1661 | /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, |
| 1662 | which requires to have TSEG_BASE aligned to TSEG_SIZE. */ |
| 1663 | tsegsize = 2; |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1664 | mmiosize = 0x800; /* 2GB MMIO */ |
Arthur Heymans | 16a70a4 | 2017-09-22 12:22:24 +0200 | [diff] [blame] | 1665 | umasizem = gfxsize + gttsize + tsegsize; |
| 1666 | mmiostart = 0x1000 - mmiosize + umasizem; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1667 | tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB; |
Arthur Heymans | 16a70a4 | 2017-09-22 12:22:24 +0200 | [diff] [blame] | 1668 | tolud = MIN(mmiostart, tom); |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1669 | |
| 1670 | reclaim = false; |
| 1671 | if ((tom - tolud) > 0x40) |
| 1672 | reclaim = true; |
| 1673 | |
| 1674 | if (reclaim) { |
| 1675 | tolud = tolud & ~0x3f; |
| 1676 | tom = tom & ~0x3f; |
| 1677 | reclaimbase = MAX(0x1000, tom); |
| 1678 | reclaimlimit = reclaimbase + (MIN(0x1000, tom) - tolud) - 0x40; |
| 1679 | } |
| 1680 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1681 | touud = tom; |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1682 | if (reclaim) |
| 1683 | touud = reclaimlimit + 0x40; |
| 1684 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1685 | gfxbase = tolud - gfxsize; |
| 1686 | gttbase = gfxbase - gttsize; |
| 1687 | tsegbase = gttbase - tsegsize; |
| 1688 | |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1689 | pci_write_config16(HOST_BRIDGE, 0xb0, tolud << 4); |
| 1690 | pci_write_config16(HOST_BRIDGE, 0xa0, tom >> 6); |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1691 | if (reclaim) { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 1692 | pci_write_config16(HOST_BRIDGE, 0x98, (u16)(reclaimbase >> 6)); |
| 1693 | pci_write_config16(HOST_BRIDGE, 0x9a, (u16)(reclaimlimit >> 6)); |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1694 | } |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1695 | pci_write_config16(HOST_BRIDGE, 0xa2, touud); |
| 1696 | pci_write_config32(HOST_BRIDGE, 0xa4, gfxbase << 20); |
| 1697 | pci_write_config32(HOST_BRIDGE, 0xa8, gttbase << 20); |
Angel Pons | 4a9569a | 2020-06-08 01:39:25 +0200 | [diff] [blame] | 1698 | /* Enable and set TSEG size to 2M */ |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1699 | pci_update_config8(HOST_BRIDGE, D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); |
| 1700 | pci_write_config32(HOST_BRIDGE, 0xac, tsegbase << 20); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1701 | } |
| 1702 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1703 | static void set_enhanced_mode(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1704 | { |
| 1705 | u8 ch, reg8; |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1706 | u32 reg32; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1707 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1708 | mchbar_write32(0xfb0, 0x1000d024); |
| 1709 | mchbar_write32(0xfb4, 0xc842); |
| 1710 | mchbar_write32(0xfbc, 0xf); |
| 1711 | mchbar_write32(0xfc4, 0xfe22244); |
| 1712 | mchbar_write8(0x12f, 0x5c); |
| 1713 | mchbar_setbits8(0xfb0, 1 << 0); |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 1714 | if (s->selected_timings.mem_clk <= MEM_CLOCK_800MHz) |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1715 | mchbar_setbits8(0x12f, 1 << 1); |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 1716 | else |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1717 | mchbar_clrbits8(0x12f, 1 << 1); |
| 1718 | mchbar_clrsetbits8(0x6c0, 0xf0, 0xa0); |
| 1719 | mchbar_write32(0xfa8, 0x30d400); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1720 | |
| 1721 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1722 | mchbar_setbits8(0x400 * ch + 0x26c, 1); |
| 1723 | mchbar_write32(0x400 * ch + 0x278, 0x88141881); |
| 1724 | mchbar_write16(0x400 * ch + 0x27c, 0x0041); |
| 1725 | mchbar_write8(0x400 * ch + 0x292, 0xf2); |
| 1726 | mchbar_setbits16(0x400 * ch + 0x272, 1 << 8); |
| 1727 | mchbar_clrsetbits8(0x400 * ch + 0x243, 3, 1); |
| 1728 | mchbar_write32(0x400 * ch + 0x288, 0x8040200); |
| 1729 | mchbar_write32(0x400 * ch + 0x28c, 0xff402010); |
| 1730 | mchbar_write32(0x400 * ch + 0x290, 0x4f2091c); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1731 | } |
| 1732 | |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1733 | reg8 = pci_read_config8(HOST_BRIDGE, 0xf0); |
| 1734 | pci_write_config8(HOST_BRIDGE, 0xf0, reg8 | 1); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1735 | mchbar_clrsetbits32(0xfa0, 0x20002, 0x2 | (s->selected_timings.fsb_clk == |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 1736 | FSB_CLOCK_1333MHz ? 0x20000 : 0)); |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1737 | reg32 = 0x219100c2; |
| 1738 | if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) { |
| 1739 | reg32 |= 1; |
| 1740 | if (s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) |
| 1741 | reg32 &= ~0x10000; |
| 1742 | } else if (s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz) { |
| 1743 | reg32 &= ~0x10000; |
| 1744 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1745 | mchbar_clrsetbits32(0xfa4, 0x219100c3, reg32); |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1746 | reg32 = 0x44a00; |
| 1747 | switch (s->selected_timings.fsb_clk) { |
| 1748 | case FSB_CLOCK_1333MHz: |
| 1749 | reg32 |= 0x62; |
| 1750 | break; |
| 1751 | case FSB_CLOCK_1066MHz: |
| 1752 | reg32 |= 0x5a; |
| 1753 | break; |
| 1754 | default: |
| 1755 | case FSB_CLOCK_800MHz: |
| 1756 | reg32 |= 0x53; |
| 1757 | break; |
| 1758 | } |
| 1759 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1760 | mchbar_write32(0x2c, reg32); |
| 1761 | mchbar_write32(0x30, 0x1f5a86); |
| 1762 | mchbar_write32(0x34, 0x1902810); |
| 1763 | mchbar_write32(0x38, 0xf7000000); |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1764 | reg32 = 0x23014410; |
| 1765 | if (s->selected_timings.fsb_clk > FSB_CLOCK_800MHz) |
| 1766 | reg32 = (reg32 & ~0x2000000) | 0x44000000; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1767 | mchbar_write32(0x3c, reg32); |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1768 | reg32 = 0x8f038000; |
| 1769 | if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) |
| 1770 | reg32 &= ~0x4000000; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1771 | mchbar_clrsetbits32(0x40, 0x8f038000, reg32); |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1772 | reg32 = 0x00013001; |
| 1773 | if (s->selected_timings.fsb_clk < FSB_CLOCK_1333MHz) |
| 1774 | reg32 |= 0x20000; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1775 | mchbar_write32(0x20, reg32); |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1776 | pci_write_config8(HOST_BRIDGE, 0xf0, reg8 & ~1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1777 | } |
| 1778 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1779 | static void power_settings(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1780 | { |
| 1781 | u32 reg1, reg2, reg3, reg4, clkgate, x592; |
| 1782 | u8 lane, ch; |
| 1783 | u8 twl = 0; |
| 1784 | u16 x264, x23c; |
| 1785 | |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 1786 | if (s->spd_type == DDR2) { |
| 1787 | twl = s->selected_timings.CAS - 1; |
| 1788 | x264 = 0x78; |
| 1789 | |
| 1790 | switch (s->selected_timings.mem_clk) { |
| 1791 | default: |
| 1792 | case MEM_CLOCK_667MHz: |
| 1793 | reg1 = 0x99; |
| 1794 | reg2 = 0x1048a9; |
| 1795 | clkgate = 0x230000; |
| 1796 | x23c = 0x7a89; |
| 1797 | break; |
| 1798 | case MEM_CLOCK_800MHz: |
| 1799 | if (s->selected_timings.CAS == 5) { |
| 1800 | reg1 = 0x19a; |
| 1801 | reg2 = 0x1048aa; |
| 1802 | } else { |
| 1803 | reg1 = 0x9a; |
| 1804 | reg2 = 0x2158aa; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1805 | x264 = 0x89; |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 1806 | } |
| 1807 | clkgate = 0x280000; |
| 1808 | x23c = 0x7b89; |
| 1809 | break; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1810 | } |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 1811 | reg3 = 0x232; |
| 1812 | reg4 = 0x2864; |
| 1813 | } else { /* DDR3 */ |
| 1814 | int ddr3_idx = s->selected_timings.mem_clk - MEM_CLOCK_800MHz; |
| 1815 | int cas_idx = s->selected_timings.CAS - 5; |
| 1816 | |
| 1817 | twl = s->selected_timings.mem_clk - MEM_CLOCK_800MHz + 5; |
| 1818 | reg1 = ddr3_c2_tab[s->nmode - 1][ddr3_idx][cas_idx][0]; |
| 1819 | reg2 = ddr3_c2_tab[s->nmode - 1][ddr3_idx][cas_idx][1]; |
| 1820 | reg3 = 0x764; |
| 1821 | reg4 = 0x78c8; |
| 1822 | x264 = ddr3_c2_x264[ddr3_idx][cas_idx]; |
| 1823 | x23c = ddr3_c2_x23c[ddr3_idx][cas_idx]; |
| 1824 | switch (s->selected_timings.mem_clk) { |
| 1825 | case MEM_CLOCK_800MHz: |
| 1826 | default: |
| 1827 | clkgate = 0x280000; |
| 1828 | break; |
| 1829 | case MEM_CLOCK_1066MHz: |
| 1830 | clkgate = 0x350000; |
| 1831 | break; |
| 1832 | case MEM_CLOCK_1333MHz: |
| 1833 | clkgate = 0xff0000; |
| 1834 | break; |
| 1835 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1836 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1837 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1838 | if (CHANNEL_IS_POPULATED(s->dimms, 0) && CHANNEL_IS_POPULATED(s->dimms, 1)) |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1839 | mchbar_write32(0x14, 0x0010461f); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1840 | else |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1841 | mchbar_write32(0x14, 0x0010691f); |
| 1842 | mchbar_write32(0x18, 0xdf6437f7); |
| 1843 | mchbar_write32(0x1c, 0); |
| 1844 | mchbar_clrsetbits32(0x24, 0xe0000000, 0x60000000); |
| 1845 | mchbar_clrsetbits32(0x44, 0x1fef0000, 0x6b0000); |
| 1846 | mchbar_write16(0x115, reg1); |
| 1847 | mchbar_clrsetbits32(0x117, 0xffffff, reg2); |
| 1848 | mchbar_write8(0x124, 0x7); |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1849 | /* not sure if dummy reads are needed */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1850 | mchbar_clrsetbits16(0x12a, ~0, 0x80); |
| 1851 | mchbar_clrsetbits8(0x12c, ~0, 0xa0); |
| 1852 | mchbar_clrbits16(0x174, 1 << 15); |
| 1853 | mchbar_clrsetbits16(0x188, 0x1f00, 0x1f00); |
| 1854 | mchbar_clrbits8(0x18c, 1 << 3); |
| 1855 | mchbar_setbits8(0x192, 1); |
| 1856 | mchbar_setbits8(0x193, 0xf); |
| 1857 | mchbar_clrsetbits16(0x1b4, 0x480, 0x80); |
| 1858 | mchbar_clrsetbits16(0x210, 0x1fff, 0x3f); /* clockgating iii */ |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1859 | /* non-aligned access: possible bug? */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1860 | mchbar_clrsetbits32(0x6d1, 0xff03ff, 0x100 | clkgate); |
| 1861 | mchbar_clrsetbits8(0x212, 0x7f, 0x7f); |
| 1862 | mchbar_clrsetbits32(0x2c0, 0xffff0, 0xcc5f0); |
| 1863 | mchbar_clrsetbits8(0x2c4, 0x70, 0x70); |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1864 | /* non-aligned access: possible bug? */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1865 | mchbar_clrsetbits32(0x2d1, 0xffffff, 0xff2831); /* clockgating i */ |
| 1866 | mchbar_write32(0x2d4, 0x40453600); |
| 1867 | mchbar_write32(0x300, 0xc0b0a08); |
| 1868 | mchbar_write32(0x304, 0x6040201); |
| 1869 | mchbar_clrsetbits32(0x30c, 0x43c0f, 0x41405); |
| 1870 | mchbar_write16(0x610, reg3); |
| 1871 | mchbar_write16(0x612, reg4); |
| 1872 | mchbar_clrsetbits32(0x62c, 0xc000000, 0x4000000); |
| 1873 | mchbar_write32(0xae4, 0); |
| 1874 | mchbar_clrsetbits32(0xc00, 0xf0000, 0x10000); |
| 1875 | mchbar_write32(0xf00, 0x393a3b3c); |
| 1876 | mchbar_write32(0xf04, 0x3d3e3f40); |
| 1877 | mchbar_write32(0xf08, 0x393a3b3c); |
| 1878 | mchbar_write32(0xf0c, 0x3d3e3f40); |
| 1879 | mchbar_clrbits32(0xf18, 0xfff00001); |
| 1880 | mchbar_write32(0xf48, 0xfff0ffe0); |
| 1881 | mchbar_write32(0xf4c, 0xffc0ff00); |
| 1882 | mchbar_write32(0xf50, 0xfc00f000); |
| 1883 | mchbar_write32(0xf54, 0xc0008000); |
| 1884 | mchbar_clrsetbits32(0xf6c, 0xffff0000, 0xffff0000); |
| 1885 | mchbar_clrbits32(0xfac, 0x80000000); |
| 1886 | mchbar_clrbits32(0xfb8, 0xff000000); |
| 1887 | mchbar_clrsetbits32(0xfbc, 0x7f800, 0xf000); |
| 1888 | mchbar_write32(0x1104, 0x3003232); |
| 1889 | mchbar_write32(0x1108, 0x74); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1890 | if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1891 | mchbar_write32(0x110c, 0xaa); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1892 | else |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1893 | mchbar_write32(0x110c, 0x100); |
| 1894 | mchbar_write32(0x1110, 0x10810350 & ~0x78); |
| 1895 | mchbar_write32(0x1114, 0); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1896 | x592 = 0xff; |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1897 | if (pci_read_config8(HOST_BRIDGE, 0x8) < 3) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1898 | x592 = ~0x4; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1899 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1900 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1901 | mchbar_write8(0x400 * ch + 0x239, twl + 15); |
| 1902 | mchbar_write16(0x400 * ch + 0x23c, x23c); |
| 1903 | mchbar_clrsetbits32(0x400 * ch + 0x248, 0x706033, 0x406033); |
| 1904 | mchbar_clrsetbits32(0x400 * ch + 0x260, 1 << 16, 1 << 16); |
| 1905 | mchbar_write8(0x400 * ch + 0x264, x264); |
| 1906 | mchbar_clrsetbits8(0x400 * ch + 0x592, 0x3f, 0x3c & x592); |
| 1907 | mchbar_clrsetbits8(0x400 * ch + 0x593, 0x1f, 0x1e); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1908 | } |
| 1909 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1910 | for (lane = 0; lane < 8; lane++) |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1911 | mchbar_clrbits8(0x561 + (lane << 2), 1 << 3); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1912 | } |
| 1913 | |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 1914 | static void software_ddr3_reset(struct sysinfo *s) |
| 1915 | { |
| 1916 | printk(BIOS_DEBUG, "Software initiated DDR3 reset.\n"); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1917 | mchbar_setbits8(0x1a8, 1 << 1); |
| 1918 | mchbar_clrbits8(0x5da, 1 << 7); |
| 1919 | mchbar_clrbits8(0x1a8, 1 << 1); |
| 1920 | mchbar_clrsetbits8(0x5da, 3, 1); |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 1921 | udelay(200); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1922 | mchbar_clrbits8(0x1a8, 1 << 1); |
| 1923 | mchbar_setbits8(0x5da, 1 << 7); |
| 1924 | mchbar_clrbits8(0x5da, 1 << 7); |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 1925 | udelay(500); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1926 | mchbar_setbits8(0x5da, 3); |
| 1927 | mchbar_clrbits8(0x5da, 3); |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 1928 | /* After write leveling the dram needs to be reset and reinitialised */ |
| 1929 | jedec_ddr3(s); |
| 1930 | } |
| 1931 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1932 | void do_raminit(struct sysinfo *s, int fast_boot) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1933 | { |
| 1934 | u8 ch; |
| 1935 | u8 r, bank; |
| 1936 | u32 reg32; |
| 1937 | |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1938 | if (s->boot_path != BOOT_PATH_WARM_RESET) { |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1939 | /* Clear self refresh */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1940 | mchbar_setbits32(PMSTS_MCHBAR, PMSTS_BOTH_SELFREFRESH); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1941 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1942 | /* Clear host clk gate reg */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1943 | mchbar_setbits32(0x1c, 0xffffffff); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1944 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1945 | /* Select type */ |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 1946 | if (s->spd_type == DDR2) |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1947 | mchbar_clrbits8(0x1a8, 1 << 2); |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 1948 | else |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1949 | mchbar_setbits8(0x1a8, 1 << 2); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1950 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1951 | /* Set frequency */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1952 | mchbar_clrsetbits32(CLKCFG_MCHBAR, CLKCFG_MEMCLK_MASK, |
Angel Pons | 93aab51 | 2021-03-27 09:06:54 +0100 | [diff] [blame] | 1953 | (s->selected_timings.mem_clk << CLKCFG_MEMCLK_SHIFT) | CLKCFG_UPDATE); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1954 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1955 | /* Overwrite value if chipset rejects it */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1956 | s->selected_timings.mem_clk = (mchbar_read8(CLKCFG_MCHBAR) & |
| 1957 | CLKCFG_MEMCLK_MASK) >> CLKCFG_MEMCLK_SHIFT; |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1958 | if (s->selected_timings.mem_clk > (s->max_fsb + 3)) |
| 1959 | die("Error: DDR is faster than FSB, halt\n"); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1960 | } |
| 1961 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1962 | /* Program clock crossing */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1963 | program_crossclock(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1964 | printk(BIOS_DEBUG, "Done clk crossing\n"); |
| 1965 | |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1966 | if (s->boot_path != BOOT_PATH_WARM_RESET) { |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1967 | setioclk_dram(s); |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1968 | printk(BIOS_DEBUG, "Done I/O clk\n"); |
| 1969 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1970 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1971 | /* Grant to launch */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1972 | launch_dram(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1973 | printk(BIOS_DEBUG, "Done launch\n"); |
| 1974 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1975 | /* Program DRAM timings */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1976 | program_timings(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1977 | printk(BIOS_DEBUG, "Done timings\n"); |
| 1978 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1979 | /* Program DLL */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1980 | program_dll(s); |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 1981 | if (!fast_boot) |
| 1982 | select_default_dq_dqs_settings(s); |
| 1983 | set_all_dq_dqs_dll_settings(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1984 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1985 | /* RCOMP */ |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1986 | if (s->boot_path != BOOT_PATH_WARM_RESET) { |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1987 | prog_rcomp(s); |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1988 | printk(BIOS_DEBUG, "RCOMP\n"); |
| 1989 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1990 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1991 | /* ODT */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1992 | program_odt(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1993 | printk(BIOS_DEBUG, "Done ODT\n"); |
| 1994 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1995 | /* RCOMP update */ |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1996 | if (s->boot_path != BOOT_PATH_WARM_RESET) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 1997 | while (mchbar_read8(0x130) & 1) |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1998 | ; |
| 1999 | printk(BIOS_DEBUG, "Done RCOMP update\n"); |
| 2000 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2001 | |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 2002 | pre_jedec_memory_map(); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2003 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2004 | /* IOBUFACT */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2005 | if (CHANNEL_IS_POPULATED(s->dimms, 0)) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2006 | mchbar_clrsetbits8(0x5dd, 0x3f, 0x3f); |
| 2007 | mchbar_setbits8(0x5d8, 0x7); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2008 | } |
| 2009 | if (CHANNEL_IS_POPULATED(s->dimms, 1)) { |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 2010 | if (pci_read_config8(HOST_BRIDGE, 0x8) < 2) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2011 | mchbar_clrsetbits8(0x5dd, 0x3f, 0x3f); |
| 2012 | mchbar_setbits8(0x5d8, 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2013 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2014 | mchbar_setbits8(0x9dd, 0x3f); |
| 2015 | mchbar_setbits8(0x9d8, 0x7); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2016 | } |
| 2017 | |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 2018 | /* DDR3 reset */ |
| 2019 | if ((s->spd_type == DDR3) && (s->boot_path != BOOT_PATH_RESUME)) { |
| 2020 | printk(BIOS_DEBUG, "DDR3 Reset.\n"); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2021 | mchbar_clrbits8(0x1a8, 1 << 1); |
| 2022 | mchbar_setbits8(0x5da, 1 << 7); |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 2023 | udelay(500); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2024 | mchbar_clrbits8(0x1a8, 1 << 1); |
| 2025 | mchbar_clrbits8(0x5da, 1 << 7); |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 2026 | udelay(500); |
| 2027 | } |
| 2028 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2029 | /* Pre jedec */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2030 | mchbar_setbits8(0x40, 1 << 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2031 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2032 | mchbar_setbits32(0x400 * ch + 0x260, 1 << 27); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2033 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2034 | mchbar_setbits16(0x212, 0xf << 12); |
| 2035 | mchbar_setbits16(0x212, 0xf << 8); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2036 | printk(BIOS_DEBUG, "Done pre-jedec\n"); |
| 2037 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2038 | /* JEDEC reset */ |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 2039 | if (s->boot_path != BOOT_PATH_RESUME) { |
| 2040 | if (s->spd_type == DDR2) |
| 2041 | jedec_ddr2(s); |
| 2042 | else /* DDR3 */ |
| 2043 | jedec_ddr3(s); |
| 2044 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2045 | |
| 2046 | printk(BIOS_DEBUG, "Done jedec steps\n"); |
| 2047 | |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 2048 | if (s->spd_type == DDR3) { |
| 2049 | if (!fast_boot) |
| 2050 | search_write_leveling(s); |
| 2051 | if (s->boot_path == BOOT_PATH_NORMAL) |
| 2052 | software_ddr3_reset(s); |
| 2053 | } |
| 2054 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2055 | /* After JEDEC reset */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2056 | mchbar_clrbits8(0x40, 1 << 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2057 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Arthur Heymans | 0d28495 | 2017-05-25 19:55:52 +0200 | [diff] [blame] | 2058 | reg32 = (2 << 18); |
| 2059 | reg32 |= post_jedec_tab[s->selected_timings.fsb_clk] |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 2060 | [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][0] << 13; |
Arthur Heymans | 0d28495 | 2017-05-25 19:55:52 +0200 | [diff] [blame] | 2061 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz && |
| 2062 | s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz && |
| 2063 | ch == 1) { |
| 2064 | reg32 |= (post_jedec_tab[s->selected_timings.fsb_clk] |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 2065 | [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] - 1) << 8; |
Arthur Heymans | 0d28495 | 2017-05-25 19:55:52 +0200 | [diff] [blame] | 2066 | } else { |
| 2067 | reg32 |= post_jedec_tab[s->selected_timings.fsb_clk] |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 2068 | [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] << 8; |
Arthur Heymans | 0d28495 | 2017-05-25 19:55:52 +0200 | [diff] [blame] | 2069 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2070 | mchbar_clrsetbits32(0x400 * ch + 0x274, 0xfff00, reg32); |
| 2071 | mchbar_clrbits8(0x400 * ch + 0x274, 1 << 7); |
| 2072 | mchbar_setbits8(0x400 * ch + 0x26c, 1 << 0); |
| 2073 | mchbar_write32(0x400 * ch + 0x278, 0x88141881); |
| 2074 | mchbar_write16(0x400 * ch + 0x27c, 0x41); |
| 2075 | mchbar_write8(0x400 * ch + 0x292, 0xf2); |
| 2076 | mchbar_setbits8(0x400 * ch + 0x271, 0xe); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2077 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2078 | mchbar_setbits8(0x2c4, 1 << 3); |
| 2079 | mchbar_setbits8(0x2c3, 1 << 6); |
| 2080 | mchbar_setbits8(0x2c4, 1 << 2); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2081 | |
| 2082 | printk(BIOS_DEBUG, "Done post-jedec\n"); |
| 2083 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2084 | /* Set DDR init complete */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2085 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2086 | mchbar_setbits32(0x400 * ch + 0x268, 3 << 30); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2087 | } |
| 2088 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2089 | /* Dummy reads */ |
Arthur Heymans | 8bb2bac | 2019-08-10 20:34:17 +0200 | [diff] [blame] | 2090 | if (s->boot_path == BOOT_PATH_NORMAL) { |
| 2091 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
| 2092 | for (bank = 0; bank < 4; bank++) |
Arthur Heymans | 4d06ff0 | 2021-07-02 10:05:09 +0200 | [diff] [blame] | 2093 | read32p(test_address(ch, r) | 0x800000 | (bank << 12)); |
Arthur Heymans | 8bb2bac | 2019-08-10 20:34:17 +0200 | [diff] [blame] | 2094 | } |
| 2095 | } |
| 2096 | printk(BIOS_DEBUG, "Done dummy reads\n"); |
| 2097 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2098 | /* Receive enable */ |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 2099 | sdram_program_receive_enable(s, fast_boot); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2100 | printk(BIOS_DEBUG, "Done rcven\n"); |
| 2101 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2102 | /* Finish rcven */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2103 | FOR_EACH_CHANNEL(ch) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2104 | mchbar_clrbits8(0x400 * ch + 0x5d8, 7 << 1); |
| 2105 | mchbar_setbits8(0x400 * ch + 0x5d8, 1 << 1); |
| 2106 | mchbar_setbits8(0x400 * ch + 0x5d8, 1 << 2); |
| 2107 | mchbar_setbits8(0x400 * ch + 0x5d8, 1 << 3); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2108 | } |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2109 | mchbar_setbits8(0x5dc, 1 << 7); |
| 2110 | mchbar_clrbits8(0x5dc, 1 << 7); |
| 2111 | mchbar_setbits8(0x5dc, 1 << 7); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2112 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2113 | /* XXX tRD */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2114 | |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 2115 | if (!fast_boot) { |
| 2116 | if (s->selected_timings.mem_clk > MEM_CLOCK_667MHz) { |
Elyes HAOUAS | 5ba154a | 2020-08-04 13:27:52 +0200 | [diff] [blame] | 2117 | if (do_write_training(s)) |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 2118 | die("DQ write training failed!"); |
| 2119 | } |
| 2120 | if (do_read_training(s)) |
| 2121 | die("DQS read training failed!"); |
| 2122 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2123 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2124 | /* DRADRB */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2125 | set_dradrb(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2126 | printk(BIOS_DEBUG, "Done DRADRB\n"); |
| 2127 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2128 | /* Memory map */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2129 | configure_mmap(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2130 | printk(BIOS_DEBUG, "Done memory map\n"); |
| 2131 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2132 | /* Enhanced mode */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2133 | set_enhanced_mode(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2134 | printk(BIOS_DEBUG, "Done enhanced mode\n"); |
| 2135 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2136 | /* Periodic RCOMP */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2137 | mchbar_clrsetbits16(0x160, 0xfff, 0x999); |
| 2138 | mchbar_setbits16(0x1b4, 0x3000); |
| 2139 | mchbar_setbits8(0x130, 1 << 7 | 1 << 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2140 | printk(BIOS_DEBUG, "Done PRCOMP\n"); |
| 2141 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2142 | /* Power settings */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2143 | power_settings(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2144 | printk(BIOS_DEBUG, "Done power settings\n"); |
| 2145 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2146 | /* ME related */ |
Arthur Heymans | ddc8828 | 2017-02-27 16:27:21 +0100 | [diff] [blame] | 2147 | /* |
| 2148 | * FIXME: This locks some registers like bit1 of GGC |
| 2149 | * and is only needed in case of ME being used. |
| 2150 | */ |
| 2151 | if (ME_UMA_SIZEMB != 0) { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 2152 | if (RANK_IS_POPULATED(s->dimms, 0, 0) || RANK_IS_POPULATED(s->dimms, 1, 0)) |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2153 | mchbar_setbits8(0xa2f, 1 << 0); |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 2154 | if (RANK_IS_POPULATED(s->dimms, 0, 1) || RANK_IS_POPULATED(s->dimms, 1, 1)) |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 2155 | mchbar_setbits8(0xa2f, 1 << 1); |
| 2156 | mchbar_setbits32(0xa30, 1 << 26); |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 2157 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2158 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2159 | printk(BIOS_DEBUG, "Done raminit\n"); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2160 | } |