nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware
8M was set in the assumption that at least 4M was needed for IED
(Intel Enhanced Debug) , but this is not true.
The SMRR MTRR's need to have TSEG aligned to its size which is easier when TSEG
is only 2M. Also at most 6M of RAM more becomes available for use.
Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27873
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index c445cad..a94e9ca3 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -1722,7 +1722,9 @@
ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
gfxsize = ggc2uma[(ggc & 0xf0) >> 4];
gttsize = ggc2gtt[(ggc & 0xf00) >> 8];
- tsegsize = 8; // 8MB TSEG
+ /* TSEG 2M, This amount can easily be covered by SMRR MTRR's,
+ which requires to have TSEG_BASE aligned to TSEG_SIZE. */
+ tsegsize = 2;
mmiosize = 0x800; // 2GB MMIO
umasizem = gfxsize + gttsize + tsegsize;
mmiostart = 0x1000 - mmiosize + umasizem;
@@ -1759,10 +1761,10 @@
pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud);
pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20);
pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20);
- /* Enable and set tseg size to 8M */
+ /* Enable and set tseg size to 2M */
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
reg8 &= ~0x7;
- reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */
+ reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8);
pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20);
}