commit 276049f9eeb5a53d1f83ee0fb6876e965a6b7ca4
author Arthur Heymans <arthur@aheymans.xyz> Sun Nov 05 05:56:34 2017 +0100
committer Patrick Georgi <pgeorgi@google.com> Tue Apr 17 10:41:14 2018 +0000
tree 072a0feb2740ad6d7202bc3c8c386c1c2fde9be0
parent 1994e448be8e843716173dc7149c8644cfd9ebc5

nb/intel/x4x: Add a convenient macro to loop over bytelanes

During raminit a lot of procedures need to be done for each bytelane.

Change-Id: Ib9a30ffabaf5c845e962e3e79cf4a20faa1d9857
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/northbridge/intel/x4x/raminit_ddr2.c

diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index f70cc6e..b967583 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -805,49 +805,46 @@
 {
 	int ch, lane;
 
-	FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
-		for (lane = 0; lane < 8; lane++) {
-			switch (s->selected_timings.mem_clk) {
-			case MEM_CLOCK_667MHz:
+	FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(s->dimms, ch, lane) {
+		switch (s->selected_timings.mem_clk) {
+		case MEM_CLOCK_667MHz:
+			memcpy(s->dqs_settings[ch],
+				default_ddr2_667_dqs,
+				sizeof(s->dqs_settings[ch]));
+			memcpy(s->dq_settings[ch],
+				default_ddr2_667_dq,
+				sizeof(s->dq_settings[ch]));
+			s->rt_dqs[ch][lane].tap = 7;
+			s->rt_dqs[ch][lane].pi = 2;
+			break;
+		case MEM_CLOCK_800MHz:
+			if (s->spd_type == DDR2) {
 				memcpy(s->dqs_settings[ch],
-					default_ddr2_667_dqs,
+					default_ddr2_800_dqs,
 					sizeof(s->dqs_settings[ch]));
 				memcpy(s->dq_settings[ch],
-					default_ddr2_667_dq,
+					default_ddr2_800_dq,
 					sizeof(s->dq_settings[ch]));
 				s->rt_dqs[ch][lane].tap = 7;
-				s->rt_dqs[ch][lane].pi = 2;
-				break;
-			case MEM_CLOCK_800MHz:
-				if (s->spd_type == DDR2) {
-					memcpy(s->dqs_settings[ch],
-						default_ddr2_800_dqs,
-						sizeof(s->dqs_settings[ch]));
-					memcpy(s->dq_settings[ch],
-						default_ddr2_800_dq,
-						sizeof(s->dq_settings[ch]));
-
-					s->rt_dqs[ch][lane].tap = 7;
-					s->rt_dqs[ch][lane].pi = 0;
-				} else { /* DDR3 */
-					/* TODO: DDR3 write DQ-DQS */
-					s->rt_dqs[ch][lane].tap = 6;
-					s->rt_dqs[ch][lane].pi = 2;
-				}
-				break;
-			case MEM_CLOCK_1066MHz:
-				/* TODO: DDR3 write DQ-DQS */
-				s->rt_dqs[ch][lane].tap = 5;
-				s->rt_dqs[ch][lane].pi = 2;
-				break;
-			case MEM_CLOCK_1333MHz:
-				/* TODO: DDR3 write DQ-DQS */
-				s->rt_dqs[ch][lane].tap = 7;
 				s->rt_dqs[ch][lane].pi = 0;
-				break;
-			default: /* not supported */
-				break;
+			} else { /* DDR3 */
+				/* TODO: DDR3 write DQ-DQS */
+				s->rt_dqs[ch][lane].tap = 6;
+				s->rt_dqs[ch][lane].pi = 2;
 			}
+			break;
+		case MEM_CLOCK_1066MHz:
+			/* TODO: DDR3 write DQ-DQS */
+			s->rt_dqs[ch][lane].tap = 5;
+			s->rt_dqs[ch][lane].pi = 2;
+			break;
+		case MEM_CLOCK_1333MHz:
+			/* TODO: DDR3 write DQ-DQS */
+			s->rt_dqs[ch][lane].tap = 7;
+			s->rt_dqs[ch][lane].pi = 0;
+			break;
+		default: /* not supported */
+			break;
 		}
 	}
 }
@@ -863,7 +860,7 @@
 	int ch, lane, rank;
 
 	FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
-		for (lane = 0; lane < 8; lane++) {
+		FOR_EACH_BYTELANE(lane) {
 			FOR_EACH_RANK_IN_CHANNEL(rank) {
 				rt_set_dqs(ch, lane, rank,
 					&s->rt_dqs[ch][lane]);
@@ -1140,7 +1137,7 @@
 		reg32 |= s->rcven_t[channel].min_common_coarse << 16;
 		MCHBAR32(0x400 * channel + 0x248) = reg32;
 
-		for (lane = 0; lane < 8; lane++) {
+	        FOR_EACH_BYTELANE(lane) {
 			medium |= s->rcven_t[channel].medium[lane]
 				<< (lane * 2);
 			coarse_offset |=