nb/intel/x4x: Sort code in program_dll()
Move the last block of the sync DLL programming up. It's independent
of the switch/case statement that it's moved around.
Change-Id: I71bc1ca1c629e4f2f4a13474c7e2c22d1a3b65d9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index e5e17d1..b3321d5 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -880,6 +880,22 @@
printk(BIOS_NOTICE, "HMC failed, using async mode\n");
}
+ mchbar_clrbits8(0x180, 1 << 7);
+
+ if ((s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz)
+ || (s->spd_type == DDR2 && s->selected_timings.fsb_clk == FSB_CLOCK_800MHz
+ && s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) {
+ i = mchbar_read8(0x1c8) & 0xf;
+ if (s->spd_type == DDR2)
+ i = (i + 10) % 14;
+ else /* DDR3 */
+ i = (i + 3) % 12;
+ mchbar_clrsetbits8(0x1c8, 0x1f, i);
+ mchbar_setbits8(0x180, 1 << 4);
+ while (mchbar_read8(0x180) & (1 << 4))
+ ;
+ }
+
switch (s->selected_timings.mem_clk) {
case MEM_CLOCK_667MHz:
clk = 0x1a;
@@ -903,22 +919,6 @@
break;
}
- mchbar_clrbits8(0x180, 1 << 7);
-
- if ((s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz)
- || (s->spd_type == DDR2 && s->selected_timings.fsb_clk == FSB_CLOCK_800MHz
- && s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) {
- i = mchbar_read8(0x1c8) & 0xf;
- if (s->spd_type == DDR2)
- i = (i + 10) % 14;
- else /* DDR3 */
- i = (i + 3) % 12;
- mchbar_clrsetbits8(0x1c8, 0x1f, i);
- mchbar_setbits8(0x180, 1 << 4);
- while (mchbar_read8(0x180) & (1 << 4))
- ;
- }
-
reg8 = mchbar_read8(0x188) & ~1;
mchbar_write8(0x188, reg8);
reg8 &= ~0x3e;