nb/intel/x4x: Correct ctrlset{2,3} register mask
MRC uses an incorrect mask when programming this register, but the reset
default value is zero and it is only programmed once. As it makes no
difference, we can safely use the correct mask. Document this difference
in a comment to indicate the deviation from MRC behavior is intentional.
The default value for this register was dumped from Asus P5QL PRO.
Change-Id: I93b0c382f76e141b319414258e40a8bfe6c7848a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index 119eccd..9fb05b0 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -289,7 +289,12 @@
static void ctrlset2(u8 ch, const struct dll_setting *setting)
{
- MCHBAR32_AND_OR(0x400*ch + 0x598, ~0x18c00000,
+ /*
+ * MRC uses an incorrect mask when programming this register, but
+ * the reset default value is zero and it is only programmed once.
+ * As it makes no difference, we can safely use the correct mask.
+ */
+ MCHBAR32_AND_OR(0x400*ch + 0x598, ~0xf000,
(setting->clk_delay << 14) |
(setting->db_sel << 12) |
(setting->db_en << 13));
@@ -299,7 +304,12 @@
static void ctrlset3(u8 ch, const struct dll_setting *setting)
{
- MCHBAR32_AND_OR(0x400*ch + 0x598, ~0x18c00000,
+ /*
+ * MRC uses an incorrect mask when programming this register, but
+ * the reset default value is zero and it is only programmed once.
+ * As it makes no difference, we can safely use the correct mask.
+ */
+ MCHBAR32_AND_OR(0x400*ch + 0x598, ~0xf00,
(setting->clk_delay << 10) |
(setting->db_sel << 8) |
(setting->db_en << 9));