nb/intel/x4x: Unroll programming RCOMP data group
The RCOMP data group is special and is programmed differently. Prepare
to simplify the code by programming it outside of the loop. Subsequent
commits will simplify the logic even further, then clean up cosmetics.
The special DDR3 case in the loop overwrites the command group strength
multiplier value. It doesn't need to be programmed for each RCOMP group.
Add a comment to justify not programming this register while programming
the settings for the RCOMP data group.
Tested on Asus P5QL PRO (DDR2), still boots.
Change-Id: I5c2484f48e3c07e8e787b1894932e342e8e8a75c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index e466d64..06570c2 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -1093,20 +1093,25 @@
}
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
+ /* RCOMP data group is special, program it separately */
+ MCHBAR32_AND_OR(0x400*i + 0x31c, ~0xff000,
+ 0xaa000);
+ MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff,
+ 0x6666);
+ for (k = 0; k < 8; k++) {
+ MCHBAR32_AND_OR(0x400*i + 0x31c +
+ 0xe + (k << 2),
+ ~0x3f3f3f3f, x32a[k]);
+ MCHBAR32_AND_OR(0x400*i + 0x31c +
+ 0x2e + (k << 2),
+ ~0x3f3f3f3f, x32a[k]);
+ }
+ MCHBAR8_AND_OR(0x400*i + 0x31c, ~1, 0);
+
+ /* Now program the other RCOMP groups */
for (j = 0; j < 6; j++) {
if (j == 0) {
- MCHBAR32_AND_OR(0x400*i + addr[j], ~0xff000,
- 0xaa000);
- MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff,
- 0x6666);
- for (k = 0; k < 8; k++) {
- MCHBAR32_AND_OR(0x400*i + addr[j] +
- 0xe + (k << 2),
- ~0x3f3f3f3f, x32a[k]);
- MCHBAR32_AND_OR(0x400*i + addr[j] +
- 0x2e + (k << 2),
- ~0x3f3f3f3f, x32a[k]);
- }
+ continue;
} else {
MCHBAR16_AND_OR(0x400*i + addr[j],
~0xf000, 0xa000);
@@ -1129,6 +1134,8 @@
MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a,
~0x3f3f3f3f, x39e[j]);
}
+
+ /* Override command group strength multiplier */
if (s->spd_type == DDR3 &&
BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) {
MCHBAR16_AND_OR(0x378 + 0x400 * i,