Patrick Georgi | c49d7a3 | 2020-05-08 22:50:46 +0200 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 2 | |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 3 | mainmenu "coreboot configuration" |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 4 | |
Uwe Hermann | c04be93 | 2009-10-05 13:55:28 +0000 | [diff] [blame] | 5 | menu "General setup" |
| 6 | |
Lee Leahy | bb70c40 | 2017-04-03 07:38:20 -0700 | [diff] [blame] | 7 | config COREBOOT_BUILD |
| 8 | bool |
| 9 | default y |
| 10 | |
Uwe Hermann | c04be93 | 2009-10-05 13:55:28 +0000 | [diff] [blame] | 11 | config LOCALVERSION |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 12 | string "Local version string" |
Uwe Hermann | c04be93 | 2009-10-05 13:55:28 +0000 | [diff] [blame] | 13 | help |
| 14 | Append an extra string to the end of the coreboot version. |
| 15 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 16 | This can be useful if, for instance, you want to append the |
| 17 | respective board's hostname or some other identifying string to |
| 18 | the coreboot version number, so that you can easily distinguish |
| 19 | boot logs of different boards from each other. |
| 20 | |
Arthur Heymans | 6f75154 | 2019-06-08 11:28:52 +0200 | [diff] [blame] | 21 | config CONFIGURABLE_CBFS_PREFIX |
| 22 | bool |
| 23 | help |
| 24 | Select this to prompt to use to configure the prefix for cbfs files. |
| 25 | |
Arthur Heymans | 6010eb2 | 2019-10-06 13:34:20 +0200 | [diff] [blame] | 26 | choice |
| 27 | prompt "CBFS prefix to use" |
| 28 | depends on CONFIGURABLE_CBFS_PREFIX |
| 29 | default CBFS_PREFIX_FALLBACK |
| 30 | |
| 31 | config CBFS_PREFIX_FALLBACK |
| 32 | bool "fallback" |
| 33 | |
| 34 | config CBFS_PREFIX_NORMAL |
| 35 | bool "normal" |
| 36 | |
| 37 | config CBFS_PREFIX_DIY |
| 38 | bool "Define your own cbfs prefix" |
| 39 | |
| 40 | endchoice |
| 41 | |
Patrick Georgi | 4b8a241 | 2010-02-09 19:35:16 +0000 | [diff] [blame] | 42 | config CBFS_PREFIX |
Arthur Heymans | 6010eb2 | 2019-10-06 13:34:20 +0200 | [diff] [blame] | 43 | string "CBFS prefix to use" if CBFS_PREFIX_DIY |
| 44 | default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK |
| 45 | default "normal" if CBFS_PREFIX_NORMAL |
Patrick Georgi | 4b8a241 | 2010-02-09 19:35:16 +0000 | [diff] [blame] | 46 | help |
| 47 | Select the prefix to all files put into the image. It's "fallback" |
| 48 | by default, "normal" is a common alternative. |
| 49 | |
Patrick Georgi | 23d89cc | 2010-03-16 01:17:19 +0000 | [diff] [blame] | 50 | choice |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 51 | prompt "Compiler to use" |
Patrick Georgi | 23d89cc | 2010-03-16 01:17:19 +0000 | [diff] [blame] | 52 | default COMPILER_GCC |
| 53 | help |
| 54 | This option allows you to select the compiler used for building |
| 55 | coreboot. |
Martin Roth | a5a628e8 | 2016-01-19 12:01:09 -0700 | [diff] [blame] | 56 | You must build the coreboot crosscompiler for the board that you |
| 57 | have selected. |
| 58 | |
| 59 | To build all the GCC crosscompilers (takes a LONG time), run: |
| 60 | make crossgcc |
| 61 | |
| 62 | For help on individual architectures, run the command: |
| 63 | make help_toolchain |
Patrick Georgi | 23d89cc | 2010-03-16 01:17:19 +0000 | [diff] [blame] | 64 | |
| 65 | config COMPILER_GCC |
| 66 | bool "GCC" |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 67 | help |
| 68 | Use the GNU Compiler Collection (GCC) to build coreboot. |
| 69 | |
| 70 | For details see http://gcc.gnu.org. |
| 71 | |
Patrick Georgi | 23d89cc | 2010-03-16 01:17:19 +0000 | [diff] [blame] | 72 | config COMPILER_LLVM_CLANG |
Arthur Heymans | 5b528bc | 2022-03-24 10:38:54 +0100 | [diff] [blame] | 73 | bool "LLVM/clang" |
| 74 | depends on ALLOW_EXPERIMENTAL_CLANG || ARCH_SUPPORTS_CLANG |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 75 | help |
Martin Roth | a5a628e8 | 2016-01-19 12:01:09 -0700 | [diff] [blame] | 76 | Use LLVM/clang to build coreboot. To use this, you must build the |
| 77 | coreboot version of the clang compiler. Run the command |
| 78 | make clang |
Arthur Heymans | 5b528bc | 2022-03-24 10:38:54 +0100 | [diff] [blame] | 79 | Note that Clang is not currently working on all architectures. |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 80 | |
| 81 | For details see http://clang.llvm.org. |
| 82 | |
Patrick Georgi | 23d89cc | 2010-03-16 01:17:19 +0000 | [diff] [blame] | 83 | endchoice |
| 84 | |
Arthur Heymans | 5b528bc | 2022-03-24 10:38:54 +0100 | [diff] [blame] | 85 | config ARCH_SUPPORTS_CLANG |
| 86 | bool |
| 87 | help |
| 88 | Opt-in flag for architectures that generally work well with CLANG. |
| 89 | By default the option would be hidden. |
| 90 | |
| 91 | config ALLOW_EXPERIMENTAL_CLANG |
| 92 | bool "Allow experimental LLVM/Clang" |
| 93 | depends on !ARCH_SUPPORTS_CLANG |
| 94 | help |
| 95 | On some architectures CLANG does not work that well. |
| 96 | Use this only to try to get CLANG working. |
| 97 | |
Patrick Georgi | 9b0de71 | 2013-12-29 18:45:23 +0100 | [diff] [blame] | 98 | config ANY_TOOLCHAIN |
| 99 | bool "Allow building with any toolchain" |
| 100 | default n |
Patrick Georgi | 9b0de71 | 2013-12-29 18:45:23 +0100 | [diff] [blame] | 101 | help |
| 102 | Many toolchains break when building coreboot since it uses quite |
Martin Roth | 4ef61b1 | 2022-05-28 12:34:44 -0600 | [diff] [blame] | 103 | unusual linker features. Unless developers explicitly request it, |
Patrick Georgi | 9b0de71 | 2013-12-29 18:45:23 +0100 | [diff] [blame] | 104 | we'll have to assume that they use their distro compiler by mistake. |
| 105 | Make sure that using patched compilers is a conscious decision. |
| 106 | |
Patrick Georgi | 516a2a7 | 2010-03-25 21:45:25 +0000 | [diff] [blame] | 107 | config CCACHE |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 108 | bool "Use ccache to speed up (re)compilation" |
Patrick Georgi | 516a2a7 | 2010-03-25 21:45:25 +0000 | [diff] [blame] | 109 | default n |
| 110 | help |
| 111 | Enables the use of ccache for faster builds. |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 112 | |
| 113 | Requires the ccache utility in your system $PATH. |
| 114 | |
| 115 | For details see https://ccache.samba.org. |
Patrick Georgi | 516a2a7 | 2010-03-25 21:45:25 +0000 | [diff] [blame] | 116 | |
Martin Roth | 461c33b | 2022-09-27 18:13:48 -0600 | [diff] [blame] | 117 | config IWYU |
| 118 | bool "Test platform with include-what-you-use" |
| 119 | help |
| 120 | This runs each source file through the include-what-you-use tool |
| 121 | to check the header includes. |
| 122 | |
Sol Boucher | 69b88bf | 2015-02-26 11:47:19 -0800 | [diff] [blame] | 123 | config FMD_GENPARSER |
| 124 | bool "Generate flashmap descriptor parser using flex and bison" |
| 125 | default n |
Sol Boucher | 69b88bf | 2015-02-26 11:47:19 -0800 | [diff] [blame] | 126 | help |
| 127 | Enable this option if you are working on the flashmap descriptor |
| 128 | parser and made changes to fmd_scanner.l or fmd_parser.y. |
| 129 | |
| 130 | Otherwise, say N to use the provided pregenerated scanner/parser. |
| 131 | |
Martin Roth | f411b70 | 2017-04-09 19:12:42 -0600 | [diff] [blame] | 132 | config UTIL_GENPARSER |
Patrick Georgi | 615cdfc | 2021-09-06 16:59:56 +0200 | [diff] [blame] | 133 | bool "Generate parsers for bincfg, sconfig and kconfig locally" |
Stefan Reinauer | 9bf7810 | 2010-08-09 13:28:18 +0000 | [diff] [blame] | 134 | default n |
Stefan Reinauer | 9bf7810 | 2010-08-09 13:28:18 +0000 | [diff] [blame] | 135 | help |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 136 | Enable this option if you are working on the sconfig device tree |
Denis 'GNUtoo' Carikli | 780e931 | 2018-01-10 14:35:55 +0100 | [diff] [blame] | 137 | parser or bincfg and made changes to the .l or .y files. |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 138 | |
Sol Boucher | 69b88bf | 2015-02-26 11:47:19 -0800 | [diff] [blame] | 139 | Otherwise, say N to use the provided pregenerated scanner/parser. |
Stefan Reinauer | 9bf7810 | 2010-08-09 13:28:18 +0000 | [diff] [blame] | 140 | |
Angel Pons | 17852e6 | 2021-05-20 15:30:59 +0200 | [diff] [blame] | 141 | choice |
| 142 | prompt "Option backend to use" |
Angel Pons | 9bc780f | 2021-05-20 16:43:08 +0200 | [diff] [blame] | 143 | default USE_MAINBOARD_SPECIFIC_OPTION_BACKEND if HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND |
Angel Pons | 17852e6 | 2021-05-20 15:30:59 +0200 | [diff] [blame] | 144 | default USE_OPTION_TABLE if NVRAMCUI_SECONDARY_PAYLOAD |
Patrick Rudolph | 4d66ab5 | 2022-03-03 10:16:35 +0100 | [diff] [blame] | 145 | default USE_UEFI_VARIABLE_STORE if DRIVERS_EFI_VARIABLE_STORE && \ |
| 146 | PAYLOAD_EDK2 && SMMSTORE_V2 |
Angel Pons | 17852e6 | 2021-05-20 15:30:59 +0200 | [diff] [blame] | 147 | |
| 148 | config OPTION_BACKEND_NONE |
| 149 | bool "None" |
| 150 | |
Joe Korty | 6d77252 | 2010-05-19 18:41:15 +0000 | [diff] [blame] | 151 | config USE_OPTION_TABLE |
| 152 | bool "Use CMOS for configuration values" |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 153 | depends on HAVE_OPTION_TABLE |
Joe Korty | 6d77252 | 2010-05-19 18:41:15 +0000 | [diff] [blame] | 154 | help |
| 155 | Enable this option if coreboot shall read options from the "CMOS" |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 156 | NVRAM instead of using hard-coded values. |
Joe Korty | 6d77252 | 2010-05-19 18:41:15 +0000 | [diff] [blame] | 157 | |
Patrick Rudolph | 4d66ab5 | 2022-03-03 10:16:35 +0100 | [diff] [blame] | 158 | config USE_UEFI_VARIABLE_STORE |
| 159 | bool "Use UEFI variable-store in SPI flash as option backend" |
| 160 | depends on DRIVERS_EFI_VARIABLE_STORE |
| 161 | depends on SMMSTORE_V2 |
| 162 | help |
| 163 | Enable this option if coreboot shall read/write options from the |
| 164 | SMMSTORE region within the SPI flash. The region must be formatted |
| 165 | by the payload first before it can be used. |
| 166 | |
Angel Pons | 9bc780f | 2021-05-20 16:43:08 +0200 | [diff] [blame] | 167 | config USE_MAINBOARD_SPECIFIC_OPTION_BACKEND |
| 168 | bool "Use mainboard-specific option backend" |
| 169 | depends on HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND |
| 170 | help |
| 171 | Use a mainboard-specific mechanism to access runtime-configurable |
| 172 | options. |
| 173 | |
Angel Pons | 17852e6 | 2021-05-20 15:30:59 +0200 | [diff] [blame] | 174 | endchoice |
| 175 | |
Timothy Pearson | f20c6e8 | 2015-02-14 16:15:31 -0600 | [diff] [blame] | 176 | config STATIC_OPTION_TABLE |
| 177 | bool "Load default configuration values into CMOS on each boot" |
Timothy Pearson | f20c6e8 | 2015-02-14 16:15:31 -0600 | [diff] [blame] | 178 | depends on USE_OPTION_TABLE |
| 179 | help |
| 180 | Enable this option to reset "CMOS" NVRAM values to default on |
| 181 | every boot. Use this if you want the NVRAM configuration to |
| 182 | never be modified from its default values. |
| 183 | |
Martin Roth | 40729a5 | 2023-01-04 17:26:21 -0700 | [diff] [blame] | 184 | config MB_COMPRESS_RAMSTAGE_LZ4 |
| 185 | bool |
Sven Schnelle | 8eee19d | 2011-05-02 19:53:04 +0000 | [diff] [blame] | 186 | help |
Martin Roth | 40729a5 | 2023-01-04 17:26:21 -0700 | [diff] [blame] | 187 | Select this in a mainboard to use LZ4 compression by default |
| 188 | |
| 189 | choice |
| 190 | prompt "Ramstage compression" |
| 191 | depends on HAVE_RAMSTAGE && !UNCOMPRESSED_RAMSTAGE |
| 192 | default COMPRESS_RAMSTAGE_LZ4 if MB_COMPRESS_RAMSTAGE_LZ4 |
| 193 | default COMPRESS_RAMSTAGE_LZMA |
| 194 | |
| 195 | config COMPRESS_RAMSTAGE_LZMA |
| 196 | bool "Compress ramstage with LZMA" |
| 197 | help |
| 198 | Compress ramstage with LZMA to save memory in the flash image. |
| 199 | |
| 200 | config COMPRESS_RAMSTAGE_LZ4 |
| 201 | bool "Compress ramstage with LZ4" |
| 202 | help |
| 203 | LZ4 doesn't give as good compression as LZMA, but decompresses much |
| 204 | faster. For large binaries such as ramstage, it's typically best to |
| 205 | use LZMA, but there can be cases where the faster decompression of |
| 206 | LZ4 can lead to a faster boot time. Testing on each individual board |
| 207 | is typically going to be needed due to the large number of factors |
| 208 | that can influence the decision. Binary size, CPU speed, ROM read |
| 209 | speed, cache, and other factors all play a part. |
| 210 | |
| 211 | If you're not sure, stick with LZMA. |
| 212 | |
| 213 | endchoice |
Sven Schnelle | 8eee19d | 2011-05-02 19:53:04 +0000 | [diff] [blame] | 214 | |
Julius Werner | 09f2921 | 2015-09-29 13:51:35 -0700 | [diff] [blame] | 215 | config COMPRESS_PRERAM_STAGES |
| 216 | bool "Compress romstage and verstage with LZ4" |
Arthur Heymans | e146fbd | 2019-11-04 18:57:06 +0100 | [diff] [blame] | 217 | depends on (HAVE_ROMSTAGE || HAVE_VERSTAGE) && NO_XIP_EARLY_STAGES |
Martin Roth | 75e5cb7 | 2016-12-15 15:05:37 -0700 | [diff] [blame] | 218 | # Default value set at the end of the file |
Julius Werner | 09f2921 | 2015-09-29 13:51:35 -0700 | [diff] [blame] | 219 | help |
| 220 | Compress romstage and (if it exists) verstage with LZ4 to save flash |
| 221 | space and speed up boot, since the time for reading the image from SPI |
| 222 | (and in the vboot case verifying it) is usually much greater than the |
Arthur Heymans | e146fbd | 2019-11-04 18:57:06 +0100 | [diff] [blame] | 223 | time spent decompressing. Doesn't work for XIP stages for obvious |
| 224 | reasons. |
Julius Werner | 09f2921 | 2015-09-29 13:51:35 -0700 | [diff] [blame] | 225 | |
Julius Werner | 99f4683 | 2018-05-16 14:14:04 -0700 | [diff] [blame] | 226 | config COMPRESS_BOOTBLOCK |
| 227 | bool |
Subrata Banik | b5962a9 | 2019-06-08 12:29:02 +0530 | [diff] [blame] | 228 | depends on HAVE_BOOTBLOCK |
Julius Werner | 99f4683 | 2018-05-16 14:14:04 -0700 | [diff] [blame] | 229 | help |
| 230 | This option can be used to compress the bootblock with LZ4 and attach |
| 231 | a small self-decompression stub to its front. This can drastically |
| 232 | reduce boot time on platforms where the bootblock is loaded over a |
| 233 | very slow connection and bootblock size trumps all other factors for |
Jonathan Neuschäfer | 2930a72 | 2018-09-29 17:42:52 +0200 | [diff] [blame] | 234 | speed. Since using this option usually requires changes to the |
Julius Werner | 99f4683 | 2018-05-16 14:14:04 -0700 | [diff] [blame] | 235 | SoC memlayout and possibly extra support code, it should not be |
| 236 | user-selectable. (There's no real point in offering this to the user |
| 237 | anyway... if it works and saves boot time, you would always want it.) |
| 238 | |
Cristian Măgherușan-Stanciu | d367b00 | 2011-06-19 03:03:28 +0200 | [diff] [blame] | 239 | config INCLUDE_CONFIG_FILE |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 240 | bool "Include the coreboot .config file into the ROM image" |
Martin Roth | 75e5cb7 | 2016-12-15 15:05:37 -0700 | [diff] [blame] | 241 | # Default value set at the end of the file |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 242 | help |
| 243 | Include the .config file that was used to compile coreboot |
| 244 | in the (CBFS) ROM image. This is useful if you want to know which |
| 245 | options were used to build a specific coreboot.rom image. |
| 246 | |
Daniele Forsi | 53847a2 | 2014-07-22 18:00:56 +0200 | [diff] [blame] | 247 | Saying Y here will increase the image size by 2-3KB. |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 248 | |
Julius Werner | 4924cdb | 2022-11-16 17:48:46 -0800 | [diff] [blame] | 249 | You can then use cbfstool to extract the config from a final image: |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 250 | |
Julius Werner | 4924cdb | 2022-11-16 17:48:46 -0800 | [diff] [blame] | 251 | cbfstool coreboot.rom extract -n config -f <output file path> |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 252 | |
| 253 | Alternatively, you can also use cbfstool to print the image |
| 254 | contents (including the raw 'config' item we're looking for). |
| 255 | |
| 256 | Example: |
| 257 | |
| 258 | $ cbfstool coreboot.rom print |
| 259 | coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, |
| 260 | offset 0x0 |
| 261 | Alignment: 64 bytes |
Steve Goodrich | f026912 | 2012-05-18 11:18:47 -0600 | [diff] [blame] | 262 | |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 263 | Name Offset Type Size |
Elyes HAOUAS | 2119d0b | 2020-02-16 10:01:33 +0100 | [diff] [blame] | 264 | cmos_layout.bin 0x0 CMOS layout 1159 |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 265 | fallback/romstage 0x4c0 stage 339756 |
Daniele Forsi | 53847a2 | 2014-07-22 18:00:56 +0200 | [diff] [blame] | 266 | fallback/ramstage 0x53440 stage 186664 |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 267 | fallback/payload 0x80dc0 payload 51526 |
| 268 | config 0x8d740 raw 3324 |
| 269 | (empty) 0x8e480 null 3610440 |
Cristian Măgherușan-Stanciu | d367b00 | 2011-06-19 03:03:28 +0200 | [diff] [blame] | 270 | |
Vadim Bendebury | 9202473d | 2011-09-21 14:46:43 -0700 | [diff] [blame] | 271 | config COLLECT_TIMESTAMPS |
| 272 | bool "Create a table of timestamps collected during boot" |
Paul Menzel | 4e4a763 | 2015-10-11 11:57:44 +0200 | [diff] [blame] | 273 | default y if ARCH_X86 |
Vadim Bendebury | 9202473d | 2011-09-21 14:46:43 -0700 | [diff] [blame] | 274 | help |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 275 | Make coreboot create a table of timer-ID/timer-value pairs to |
| 276 | allow measuring time spent at different phases of the boot process. |
| 277 | |
Martin Roth | b22bbe2 | 2018-03-07 15:32:16 -0700 | [diff] [blame] | 278 | config TIMESTAMPS_ON_CONSOLE |
| 279 | bool "Print the timestamp values on the console" |
| 280 | default n |
| 281 | depends on COLLECT_TIMESTAMPS |
| 282 | help |
Kyösti Mälkki | 8b93cb7 | 2020-01-09 08:41:46 +0200 | [diff] [blame] | 283 | Print the timestamps to the debug console if enabled at level info. |
Martin Roth | b22bbe2 | 2018-03-07 15:32:16 -0700 | [diff] [blame] | 284 | |
Patrick Georgi | 7e9b9d8 | 2012-04-30 21:06:10 +0200 | [diff] [blame] | 285 | config USE_BLOBS |
| 286 | bool "Allow use of binary-only repository" |
Felix Held | a6b887e | 2019-12-28 19:10:12 +0100 | [diff] [blame] | 287 | default y |
Patrick Georgi | 7e9b9d8 | 2012-04-30 21:06:10 +0200 | [diff] [blame] | 288 | help |
| 289 | This draws in the blobs repository, which contains binary files that |
| 290 | might be required for some chipsets or boards. |
| 291 | This flag ensures that a "Free" option remains available for users. |
| 292 | |
Marshall Dawson | 20ce400 | 2019-10-28 15:55:03 -0600 | [diff] [blame] | 293 | config USE_AMD_BLOBS |
| 294 | bool "Allow AMD blobs repository (with license agreement)" |
| 295 | depends on USE_BLOBS |
| 296 | help |
| 297 | This draws in the amd_blobs repository, which contains binary files |
| 298 | distributed by AMD, including VBIOS, PSP bootloaders, SMU firmwares, |
| 299 | etc. Selecting this item to download or clone the repo implies your |
| 300 | agreement to the AMD license agreement. A copy of the license text |
| 301 | may be reviewed by reading Documentation/soc/amd/amdblobs_license.md, |
| 302 | and your copy of the license is present in the repo once downloaded. |
| 303 | |
| 304 | Note that for some products, omitting PSP, SMU images, or other items |
| 305 | may result in a nonbooting coreboot.rom. |
| 306 | |
Julius Werner | bc1cb38 | 2020-06-18 15:03:22 -0700 | [diff] [blame] | 307 | config USE_QC_BLOBS |
Benjamin Doron | 999d29e | 2020-07-01 01:47:22 +0000 | [diff] [blame] | 308 | bool "Allow QC blobs repository (selecting this agrees to the license!)" |
Julius Werner | bc1cb38 | 2020-06-18 15:03:22 -0700 | [diff] [blame] | 309 | depends on USE_BLOBS |
| 310 | help |
| 311 | This draws in the qc_blobs repository, which contains binary files |
| 312 | distributed by Qualcomm that are required to build firmware for |
| 313 | certain Qualcomm SoCs (including QcLib, QC-SEC, qtiseclib and QUP |
| 314 | firmware). If you say Y here you are implicitly agreeing to the |
| 315 | Qualcomm license agreement which can be found at: |
| 316 | https://review.coreboot.org/cgit/qc_blobs.git/tree/LICENSE |
| 317 | |
| 318 | ***************************************************** |
| 319 | PLEASE MAKE SURE YOU READ AND AGREE TO ALL TERMS IN |
| 320 | ABOVE LICENSE AGREEMENT BEFORE SELECTING THIS OPTION! |
| 321 | ***************************************************** |
| 322 | |
| 323 | Not selecting this option means certain Qualcomm SoCs and related |
| 324 | mainboards cannot be built and will be hidden from the "Mainboards" |
| 325 | section. |
| 326 | |
Stefan Reinauer | d37ab45 | 2012-12-18 16:23:28 -0800 | [diff] [blame] | 327 | config COVERAGE |
| 328 | bool "Code coverage support" |
| 329 | depends on COMPILER_GCC |
Stefan Reinauer | d37ab45 | 2012-12-18 16:23:28 -0800 | [diff] [blame] | 330 | help |
| 331 | Add code coverage support for coreboot. This will store code |
| 332 | coverage information in CBMEM for extraction from user space. |
| 333 | If unsure, say N. |
| 334 | |
Ryan Salsamendi | ab37e9a | 2017-06-11 21:07:31 -0700 | [diff] [blame] | 335 | config UBSAN |
| 336 | bool "Undefined behavior sanitizer support" |
| 337 | default n |
| 338 | help |
| 339 | Instrument the code with checks for undefined behavior. If unsure, |
| 340 | say N because it adds a small performance penalty and may abort |
| 341 | on code that happens to work in spite of the UB. |
| 342 | |
Harshit Sharma | 0b1ec5a | 2020-08-05 21:16:31 -0700 | [diff] [blame] | 343 | config HAVE_ASAN_IN_ROMSTAGE |
| 344 | bool |
Harshit Sharma | 2bcaba0 | 2020-06-09 20:25:16 -0700 | [diff] [blame] | 345 | default n |
Harshit Sharma | 0b1ec5a | 2020-08-05 21:16:31 -0700 | [diff] [blame] | 346 | |
| 347 | config ASAN_IN_ROMSTAGE |
| 348 | bool |
| 349 | default n |
| 350 | help |
| 351 | Enable address sanitizer in romstage for platform. |
| 352 | |
| 353 | config HAVE_ASAN_IN_RAMSTAGE |
| 354 | bool |
| 355 | default n |
| 356 | |
| 357 | config ASAN_IN_RAMSTAGE |
| 358 | bool |
| 359 | default n |
| 360 | help |
| 361 | Enable address sanitizer in ramstage for platform. |
| 362 | |
| 363 | config ASAN |
| 364 | bool "Address sanitizer support" |
| 365 | default n |
| 366 | select ASAN_IN_ROMSTAGE if HAVE_ASAN_IN_ROMSTAGE |
| 367 | select ASAN_IN_RAMSTAGE if HAVE_ASAN_IN_RAMSTAGE |
Arthur Heymans | 25a0c67 | 2022-03-24 00:15:46 +0100 | [diff] [blame] | 368 | depends on COMPILER_GCC |
Harshit Sharma | 2bcaba0 | 2020-06-09 20:25:16 -0700 | [diff] [blame] | 369 | help |
| 370 | Enable address sanitizer - runtime memory debugger, |
| 371 | designed to find out-of-bounds accesses and use-after-scope bugs. |
| 372 | |
| 373 | This feature consumes up to 1/8 of available memory and brings about |
| 374 | ~1.5x performance slowdown. |
| 375 | |
| 376 | If unsure, say N. |
| 377 | |
Harshit Sharma | 0b1ec5a | 2020-08-05 21:16:31 -0700 | [diff] [blame] | 378 | if ASAN |
Harshit Sharma | 3b9cc85 | 2020-07-06 23:38:31 -0700 | [diff] [blame] | 379 | comment "Before using this feature, make sure that " |
| 380 | comment "asan_shadow_offset_callback patch is applied to GCC." |
| 381 | endif |
| 382 | |
Kyösti Mälkki | 6766f4f | 2019-12-18 00:19:06 +0200 | [diff] [blame] | 383 | choice |
| 384 | prompt "Stage Cache for ACPI S3 resume" |
Reka Norman | 166c303 | 2022-12-19 11:11:48 +1100 | [diff] [blame] | 385 | default NO_STAGE_CACHE if !HAVE_ACPI_RESUME || MAINBOARD_DISABLE_STAGE_CACHE |
Kyösti Mälkki | 6766f4f | 2019-12-18 00:19:06 +0200 | [diff] [blame] | 386 | default TSEG_STAGE_CACHE if SMM_TSEG |
| 387 | |
| 388 | config NO_STAGE_CACHE |
| 389 | bool "Disabled" |
| 390 | help |
| 391 | Do not save any component in stage cache for resume path. On resume, |
| 392 | all components would be read back from CBFS again. |
| 393 | |
Kyösti Mälkki | 0a4457f | 2019-08-01 20:29:14 +0300 | [diff] [blame] | 394 | config TSEG_STAGE_CACHE |
Kyösti Mälkki | 6766f4f | 2019-12-18 00:19:06 +0200 | [diff] [blame] | 395 | bool "TSEG" |
| 396 | depends on SMM_TSEG |
Stefan Reinauer | 58470e3 | 2014-10-17 13:08:36 +0200 | [diff] [blame] | 397 | help |
Kyösti Mälkki | 0a4457f | 2019-08-01 20:29:14 +0300 | [diff] [blame] | 398 | The option enables stage cache support for platform. Platform |
| 399 | can stash copies of postcar, ramstage and raw runtime data |
| 400 | inside SMM TSEG, to be restored on S3 resume path. |
| 401 | |
| 402 | config CBMEM_STAGE_CACHE |
Kyösti Mälkki | 6766f4f | 2019-12-18 00:19:06 +0200 | [diff] [blame] | 403 | bool "CBMEM" |
| 404 | depends on !SMM_TSEG |
Kyösti Mälkki | 0a4457f | 2019-08-01 20:29:14 +0300 | [diff] [blame] | 405 | help |
| 406 | The option enables stage cache support for platform. Platform |
| 407 | can stash copies of postcar, ramstage and raw runtime data |
| 408 | inside CBMEM. |
| 409 | |
| 410 | While the approach is faster than reloading stages from boot media |
| 411 | it is also a possible attack scenario via which OS can possibly |
| 412 | circumvent SMM locks and SPI write protections. |
| 413 | |
| 414 | If unsure, select 'N' |
Stefan Reinauer | 58470e3 | 2014-10-17 13:08:36 +0200 | [diff] [blame] | 415 | |
Kyösti Mälkki | 6766f4f | 2019-12-18 00:19:06 +0200 | [diff] [blame] | 416 | endchoice |
| 417 | |
Reka Norman | 166c303 | 2022-12-19 11:11:48 +1100 | [diff] [blame] | 418 | config MAINBOARD_DISABLE_STAGE_CACHE |
| 419 | bool |
| 420 | help |
| 421 | Selected by mainboards which wish to disable the stage cache. |
| 422 | E.g. mainboards which don't use S3 resume in the field may wish to |
| 423 | disable it to save boot time at the cost of increasing S3 resume time. |
| 424 | |
Stefan Reinauer | 58470e3 | 2014-10-17 13:08:36 +0200 | [diff] [blame] | 425 | config UPDATE_IMAGE |
| 426 | bool "Update existing coreboot.rom image" |
Stefan Reinauer | 58470e3 | 2014-10-17 13:08:36 +0200 | [diff] [blame] | 427 | help |
| 428 | If this option is enabled, no new coreboot.rom file |
| 429 | is created. Instead it is expected that there already |
| 430 | is a suitable file for further processing. |
| 431 | The bootblock will not be modified. |
| 432 | |
Martin Roth | 5942e06 | 2016-01-20 14:59:21 -0700 | [diff] [blame] | 433 | If unsure, select 'N' |
| 434 | |
Konstantin Aladyshev | 6544cb3 | 2015-01-24 18:52:10 +0400 | [diff] [blame] | 435 | config BOOTSPLASH_IMAGE |
| 436 | bool "Add a bootsplash image" |
| 437 | help |
| 438 | Select this option if you have a bootsplash image that you would |
| 439 | like to add to your ROM. |
| 440 | |
| 441 | This will only add the image to the ROM. To actually run it check |
| 442 | options under 'Display' section. |
| 443 | |
| 444 | config BOOTSPLASH_FILE |
| 445 | string "Bootsplash path and filename" |
| 446 | depends on BOOTSPLASH_IMAGE |
Martin Roth | 75e5cb7 | 2016-12-15 15:05:37 -0700 | [diff] [blame] | 447 | # Default value set at the end of the file |
Konstantin Aladyshev | 6544cb3 | 2015-01-24 18:52:10 +0400 | [diff] [blame] | 448 | help |
| 449 | The path and filename of the file to use as graphical bootsplash |
Nico Huber | 799e79d | 2023-07-16 19:24:13 +0200 | [diff] [blame] | 450 | screen. The file format has to be JPEG with YCC 4:2:0 color sampling |
| 451 | unless converted with "Pre-process bootsplash file with ImageMagick". |
| 452 | |
| 453 | The image can only be displayed by coreboot if it's smaller or has |
| 454 | the same size as the framebuffer resolution. Width and height have |
| 455 | to be a multiple of 16 pixels. |
| 456 | |
| 457 | Setting these constraints allows a leaner implementation in coreboot. |
| 458 | The minimum necessary ImageMagick command line seems to be: |
| 459 | $ convert input.img -colorspace YCC -sampling-factor 4:2:0 bootsplash.jpg |
| 460 | |
| 461 | config BOOTSPLASH_CONVERT |
| 462 | bool "Pre-process bootsplash file with ImageMagick" |
| 463 | depends on BOOTSPLASH_IMAGE |
| 464 | help |
| 465 | Use ImageMagick (`convert` program) to convert a bootsplash image |
| 466 | to the supported JPEG format. |
| 467 | |
| 468 | config BOOTSPLASH_CONVERT_QUALITY |
| 469 | int "Bootsplash JPEG target quality (%)" |
| 470 | depends on BOOTSPLASH_CONVERT |
| 471 | range 1 100 |
| 472 | # Default value set at the end of the file |
| 473 | |
| 474 | config BOOTSPLASH_CONVERT_RESIZE |
| 475 | bool "Resize bootsplash image" |
| 476 | depends on BOOTSPLASH_CONVERT |
| 477 | help |
| 478 | Resize the image to the given resolution. Aspect ratio will be kept, |
| 479 | adding black bars as necessary. |
| 480 | |
| 481 | config BOOTSPLASH_CONVERT_RESOLUTION |
| 482 | string "Bootsplash image target size" |
| 483 | depends on BOOTSPLASH_CONVERT_RESIZE |
| 484 | # Default value set at the end of the file |
| 485 | help |
| 486 | Target image resolution given as <width>x<height>, e.g. 1024x768. |
| 487 | Values not divisible by 16 will be rounded down. |
| 488 | |
| 489 | When using coreboot to display the bootsplash image (CONFIG_BOOTSPLASH), |
| 490 | set this lower or equal to the minimum resolution you expect. |
| 491 | |
| 492 | config BOOTSPLASH_CONVERT_COLORSWAP |
| 493 | bool "Swap red and blue color channels" |
| 494 | depends on BOOTSPLASH_CONVERT |
| 495 | help |
| 496 | The JPEG decoder currently ignores the framebuffer color order. |
| 497 | If your colors seem all wrong, try this option. |
Konstantin Aladyshev | 6544cb3 | 2015-01-24 18:52:10 +0400 | [diff] [blame] | 498 | |
Duncan Laurie | 36e6c6f | 2020-05-09 19:20:10 -0700 | [diff] [blame] | 499 | config FW_CONFIG |
| 500 | bool "Firmware Configuration Probing" |
| 501 | default n |
| 502 | help |
| 503 | Enable support for probing devices with fw_config. This is a simple |
| 504 | bitmask broken into fields and options for probing. |
| 505 | |
Duncan Laurie | 36e6c6f | 2020-05-09 19:20:10 -0700 | [diff] [blame] | 506 | config FW_CONFIG_SOURCE_CHROMEEC_CBI |
| 507 | bool "Obtain Firmware Configuration value from Google Chrome EC CBI" |
| 508 | depends on FW_CONFIG && EC_GOOGLE_CHROMEEC |
| 509 | default n |
| 510 | help |
| 511 | This option tells coreboot to read the firmware configuration value |
| 512 | from the Google Chrome Embedded Controller CBI interface. This source |
| 513 | is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was |
| 514 | found in CBFS. |
| 515 | |
Wonkyu Kim | 3864973 | 2021-11-01 20:15:30 -0700 | [diff] [blame] | 516 | config FW_CONFIG_SOURCE_CBFS |
| 517 | bool "Obtain Firmware Configuration value from CBFS" |
| 518 | depends on FW_CONFIG |
| 519 | default n |
| 520 | help |
| 521 | With this option enabled coreboot will look for the 32bit firmware |
| 522 | configuration value in CBFS at the selected prefix with the file name |
| 523 | "fw_config". This option will override other sources and allow the |
| 524 | local image to preempt the mainboard selected source and can be used as |
| 525 | FW_CONFIG_SOURCE_CHROMEEC_CBI fallback option. |
| 526 | |
Wonkyu Kim | 43e2692 | 2021-11-01 20:55:25 -0700 | [diff] [blame] | 527 | config FW_CONFIG_SOURCE_VPD |
| 528 | bool "Obtain Firmware Configuration value from VPD" |
| 529 | depends on FW_CONFIG && VPD |
| 530 | default n |
| 531 | help |
| 532 | With this option enabled coreboot will look for the 32bit firmware |
| 533 | configuration value in VPD key name "fw_config". This option will |
| 534 | override other sources and allow the local image to preempt the mainboard |
| 535 | selected source and can be used for other FW_CONFIG_SOURCEs fallback option. |
| 536 | |
Nico Huber | 94cdec6 | 2019-06-06 19:36:02 +0200 | [diff] [blame] | 537 | config HAVE_RAMPAYLOAD |
| 538 | bool |
| 539 | |
Subrata Banik | 7e893a0 | 2019-05-06 14:17:41 +0530 | [diff] [blame] | 540 | config RAMPAYLOAD |
| 541 | bool "Enable coreboot flow without executing ramstage" |
Subrata Banik | 86dbe0f | 2019-06-28 18:18:37 +0530 | [diff] [blame] | 542 | default y if ARCH_X86 |
Nico Huber | 94cdec6 | 2019-06-06 19:36:02 +0200 | [diff] [blame] | 543 | depends on HAVE_RAMPAYLOAD |
Subrata Banik | 7e893a0 | 2019-05-06 14:17:41 +0530 | [diff] [blame] | 544 | help |
| 545 | If this option is enabled, coreboot flow will skip ramstage |
| 546 | loading and execution of ramstage to load payload. |
| 547 | |
| 548 | Instead it is expected to load payload from postcar stage itself. |
| 549 | |
| 550 | In this flow coreboot will perform basic x86 initialization |
| 551 | (DRAM resource allocation), MTRR programming, |
| 552 | Skip PCI enumeration logic and only allocate BAR for fixed devices |
| 553 | (bootable devices, TPM over GSPI). |
| 554 | |
Subrata Banik | 37bead6 | 2020-02-09 19:13:52 +0530 | [diff] [blame] | 555 | config HAVE_CONFIGURABLE_RAMSTAGE |
| 556 | bool |
| 557 | |
Ronald G. Minnich | 466ca2c | 2019-10-22 02:02:24 +0000 | [diff] [blame] | 558 | config CONFIGURABLE_RAMSTAGE |
| 559 | bool "Enable a configurable ramstage." |
| 560 | default y if ARCH_X86 |
Subrata Banik | 37bead6 | 2020-02-09 19:13:52 +0530 | [diff] [blame] | 561 | depends on HAVE_CONFIGURABLE_RAMSTAGE |
Ronald G. Minnich | 466ca2c | 2019-10-22 02:02:24 +0000 | [diff] [blame] | 562 | help |
| 563 | A configurable ramstage allows you to select which parts of the ramstage |
| 564 | to run. Currently, we can only select a minimal PCI scanning step. |
| 565 | The minimal PCI scanning will only check those parts that are enabled |
| 566 | in the devicetree.cb. By convention none of those devices should be bridges. |
| 567 | |
| 568 | config MINIMAL_PCI_SCANNING |
| 569 | bool "Enable minimal PCI scanning" |
Subrata Banik | 1cb26a6 | 2020-02-09 19:35:16 +0530 | [diff] [blame] | 570 | depends on CONFIGURABLE_RAMSTAGE && PCI |
Ronald G. Minnich | 466ca2c | 2019-10-22 02:02:24 +0000 | [diff] [blame] | 571 | help |
Subrata Banik | 1cb26a6 | 2020-02-09 19:35:16 +0530 | [diff] [blame] | 572 | If this option is enabled, coreboot will scan only PCI devices |
Ronald G. Minnich | 466ca2c | 2019-10-22 02:02:24 +0000 | [diff] [blame] | 573 | marked as mandatory in devicetree.cb |
Maximilian Brune | 1d7a9de | 2022-04-14 14:54:16 +0200 | [diff] [blame] | 574 | |
| 575 | menu "Software Bill Of Materials (SBOM)" |
| 576 | |
| 577 | source "src/sbom/Kconfig" |
| 578 | |
| 579 | endmenu |
Uwe Hermann | c04be93 | 2009-10-05 13:55:28 +0000 | [diff] [blame] | 580 | endmenu |
| 581 | |
Martin Roth | 026e4dc | 2015-06-19 23:17:15 -0600 | [diff] [blame] | 582 | menu "Mainboard" |
| 583 | |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 584 | source "src/mainboard/Kconfig" |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 585 | |
Marshall Dawson | e937513 | 2016-09-04 08:38:33 -0600 | [diff] [blame] | 586 | config DEVICETREE |
| 587 | string |
| 588 | default "devicetree.cb" |
| 589 | help |
| 590 | This symbol allows mainboards to select a different file under their |
| 591 | mainboard directory for the devicetree.cb file. This allows the board |
| 592 | variants that need different devicetrees to be in the same directory. |
| 593 | |
| 594 | Examples: "devicetree.variant.cb" |
| 595 | "variant/devicetree.cb" |
| 596 | |
Furquan Shaikh | f241998 | 2018-06-21 18:50:48 -0700 | [diff] [blame] | 597 | config OVERRIDE_DEVICETREE |
| 598 | string |
| 599 | default "" |
| 600 | help |
| 601 | This symbol allows variants to provide an override devicetree file to |
| 602 | override the registers and/or add new devices on top of the ones |
| 603 | provided by baseboard devicetree using CONFIG_DEVICETREE. |
| 604 | |
| 605 | Examples: "devicetree.variant-override.cb" |
| 606 | "variant/devicetree-override.cb" |
| 607 | |
Patrick Georgi | 8a3592e | 2015-09-16 18:10:52 +0200 | [diff] [blame] | 608 | config FMDFILE |
| 609 | string "fmap description file in fmd format" |
Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 610 | default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS |
Patrick Georgi | 8a3592e | 2015-09-16 18:10:52 +0200 | [diff] [blame] | 611 | default "" |
| 612 | help |
| 613 | The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE, |
| 614 | but in some cases more complex setups are required. |
| 615 | When an fmd is specified, it overrides the default format. |
| 616 | |
Arthur Heymans | 965881b | 2019-09-25 13:18:52 +0200 | [diff] [blame] | 617 | config CBFS_SIZE |
| 618 | hex "Size of CBFS filesystem in ROM" |
| 619 | depends on FMDFILE = "" |
| 620 | # Default value set at the end of the file |
| 621 | help |
| 622 | This is the part of the ROM actually managed by CBFS, located at the |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame] | 623 | end of the ROM (passed through cbfstool -o) on x86 and at the start |
Arthur Heymans | 965881b | 2019-09-25 13:18:52 +0200 | [diff] [blame] | 624 | of the ROM (passed through cbfstool -s) everywhere else. It defaults |
| 625 | to span the whole ROM on all but Intel systems that use an Intel Firmware |
| 626 | Descriptor. It can be overridden to make coreboot live alongside other |
| 627 | components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE |
| 628 | binaries. This symbol should only be used to generate a default FMAP and |
| 629 | is unused when a non-default fmd file is provided via CONFIG_FMDFILE. |
| 630 | |
Martin Roth | da1ca20 | 2015-12-26 16:51:16 -0700 | [diff] [blame] | 631 | endmenu |
| 632 | |
Martin Roth | b09a569 | 2016-01-24 19:38:33 -0700 | [diff] [blame] | 633 | # load site-local kconfig to allow user specific defaults and overrides |
| 634 | source "site-local/Kconfig" |
| 635 | |
Vladimir Serbinenko | a9db82f | 2014-10-16 13:21:47 +0200 | [diff] [blame] | 636 | config SYSTEM_TYPE_LAPTOP |
Martin Roth | 595e777 | 2015-04-26 18:53:26 -0600 | [diff] [blame] | 637 | default n |
| 638 | bool |
Vladimir Serbinenko | a9db82f | 2014-10-16 13:21:47 +0200 | [diff] [blame] | 639 | |
Duncan Laurie | 8312df4 | 2019-02-01 11:33:57 -0800 | [diff] [blame] | 640 | config SYSTEM_TYPE_TABLET |
| 641 | default n |
| 642 | bool |
| 643 | |
| 644 | config SYSTEM_TYPE_DETACHABLE |
| 645 | default n |
| 646 | bool |
| 647 | |
| 648 | config SYSTEM_TYPE_CONVERTIBLE |
| 649 | default n |
| 650 | bool |
| 651 | |
Werner Zeh | c0fb361 | 2016-01-14 15:08:36 +0100 | [diff] [blame] | 652 | config CBFS_AUTOGEN_ATTRIBUTES |
| 653 | default n |
| 654 | bool |
| 655 | help |
| 656 | If this option is selected, every file in cbfs which has a constraint |
| 657 | regarding position or alignment will get an additional file attribute |
| 658 | which describes this constraint. |
| 659 | |
Uwe Hermann | 63a8f2a | 2009-10-26 21:42:13 +0000 | [diff] [blame] | 660 | menu "Chipset" |
| 661 | |
Duncan Laurie | d211976 | 2015-06-08 18:11:56 -0700 | [diff] [blame] | 662 | comment "SoC" |
Martin Roth | 7e48686 | 2022-06-22 20:58:06 -0600 | [diff] [blame] | 663 | source "src/soc/*/*/Kconfig" |
| 664 | source "src/soc/*/*/Kconfig.common" |
Uwe Hermann | 63a8f2a | 2009-10-26 21:42:13 +0000 | [diff] [blame] | 665 | comment "CPU" |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 666 | source "src/cpu/Kconfig" |
Uwe Hermann | 63a8f2a | 2009-10-26 21:42:13 +0000 | [diff] [blame] | 667 | comment "Northbridge" |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 668 | source "src/northbridge/*/*/Kconfig" |
Angel Pons | f462b3d | 2021-01-20 00:36:31 +0100 | [diff] [blame] | 669 | source "src/northbridge/*/*/Kconfig.common" |
Uwe Hermann | 63a8f2a | 2009-10-26 21:42:13 +0000 | [diff] [blame] | 670 | comment "Southbridge" |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 671 | source "src/southbridge/*/*/Kconfig" |
Angel Pons | c027ece | 2021-02-16 16:13:35 +0100 | [diff] [blame] | 672 | source "src/southbridge/*/*/Kconfig.common" |
Uwe Hermann | 63a8f2a | 2009-10-26 21:42:13 +0000 | [diff] [blame] | 673 | comment "Super I/O" |
Omar Pakker | 57603e2 | 2016-07-29 23:31:45 +0200 | [diff] [blame] | 674 | source "src/superio/*/*/Kconfig" |
Sven Schnelle | 7592e8b | 2011-01-27 11:43:03 +0000 | [diff] [blame] | 675 | comment "Embedded Controllers" |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 676 | source "src/ec/acpi/Kconfig" |
| 677 | source "src/ec/*/*/Kconfig" |
Uwe Hermann | 63a8f2a | 2009-10-26 21:42:13 +0000 | [diff] [blame] | 678 | |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 679 | source "src/southbridge/intel/common/firmware/Kconfig" |
Martin Roth | e1523ec | 2015-06-19 22:30:43 -0600 | [diff] [blame] | 680 | source "src/vendorcode/*/Kconfig" |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 681 | |
Martin Roth | e1523ec | 2015-06-19 22:30:43 -0600 | [diff] [blame] | 682 | source "src/arch/*/Kconfig" |
| 683 | |
Duncan Laurie | e335c2e | 2020-07-29 16:28:43 -0700 | [diff] [blame] | 684 | config CHIPSET_DEVICETREE |
| 685 | string |
| 686 | default "" |
| 687 | help |
| 688 | This symbol allows a chipset to provide a set of default settings in |
| 689 | a devicetree which are common to all mainboards. This may include |
| 690 | devices (including alias names), chip drivers, register settings, |
| 691 | and others. This path is relative to the src/ directory. |
| 692 | |
| 693 | Example: "chipset.cb" |
| 694 | |
Uwe Hermann | 63a8f2a | 2009-10-26 21:42:13 +0000 | [diff] [blame] | 695 | endmenu |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 696 | |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 697 | source "src/device/Kconfig" |
Stefan Reinauer | 95a6396 | 2012-11-13 17:00:01 -0800 | [diff] [blame] | 698 | |
Rudolf Marek | d9c2549 | 2010-05-16 15:31:53 +0000 | [diff] [blame] | 699 | menu "Generic Drivers" |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 700 | source "src/drivers/*/Kconfig" |
Stefan Reinauer | 86ddd73 | 2016-03-11 20:22:28 -0800 | [diff] [blame] | 701 | source "src/drivers/*/*/Kconfig" |
Duncan Laurie | 2cc126b | 2020-08-28 19:46:35 +0000 | [diff] [blame] | 702 | source "src/drivers/*/*/*/Kconfig" |
Lee Leahy | 48dbc66 | 2017-05-08 16:56:03 -0700 | [diff] [blame] | 703 | source "src/commonlib/storage/Kconfig" |
Rudolf Marek | d9c2549 | 2010-05-16 15:31:53 +0000 | [diff] [blame] | 704 | endmenu |
| 705 | |
Philipp Deppenwiese | 1899fbe | 2017-10-16 17:09:33 +0200 | [diff] [blame] | 706 | menu "Security" |
| 707 | |
| 708 | source "src/security/Kconfig" |
Wim Vervoorn | e32d16f | 2019-11-14 14:10:28 +0100 | [diff] [blame] | 709 | source "src/vendorcode/eltan/security/Kconfig" |
Philipp Deppenwiese | 1899fbe | 2017-10-16 17:09:33 +0200 | [diff] [blame] | 710 | |
| 711 | endmenu |
| 712 | |
Martin Roth | 09210a1 | 2016-05-17 11:28:23 -0600 | [diff] [blame] | 713 | source "src/acpi/Kconfig" |
| 714 | |
Aaron Durbin | 4a36c4e | 2016-08-11 11:02:26 -0500 | [diff] [blame] | 715 | # This option is for the current boards/chipsets where SPI flash |
| 716 | # is not the boot device. Currently nearly all boards/chipsets assume |
| 717 | # SPI flash is the boot device. |
| 718 | config BOOT_DEVICE_NOT_SPI_FLASH |
| 719 | bool |
| 720 | default n |
| 721 | |
| 722 | config BOOT_DEVICE_SPI_FLASH |
| 723 | bool |
| 724 | default y if !BOOT_DEVICE_NOT_SPI_FLASH |
| 725 | default n |
| 726 | |
Aaron Durbin | 16c173f | 2016-08-11 14:04:10 -0500 | [diff] [blame] | 727 | config BOOT_DEVICE_MEMORY_MAPPED |
| 728 | bool |
| 729 | default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH |
| 730 | default n |
| 731 | help |
| 732 | Inform system if SPI is memory-mapped or not. |
| 733 | |
Aaron Durbin | e8e118d | 2016-08-12 15:00:10 -0500 | [diff] [blame] | 734 | config BOOT_DEVICE_SUPPORTS_WRITES |
| 735 | bool |
| 736 | default n |
| 737 | help |
| 738 | Indicate that the platform has writable boot device |
| 739 | support. |
| 740 | |
Patrick Georgi | 0770f25 | 2015-04-22 13:28:21 +0200 | [diff] [blame] | 741 | config RTC |
| 742 | bool |
| 743 | default n |
| 744 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 745 | config HEAP_SIZE |
| 746 | hex |
Marty E. Plummer | 0987e43 | 2019-04-22 20:46:27 -0500 | [diff] [blame] | 747 | default 0x100000 if FLATTENED_DEVICE_TREE |
Myles Watson | 04000f4 | 2009-10-16 19:12:49 +0000 | [diff] [blame] | 748 | default 0x4000 |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 749 | |
Julius Werner | c3e7c4e | 2014-09-19 13:18:16 -0700 | [diff] [blame] | 750 | config STACK_SIZE |
| 751 | hex |
Arthur Heymans | 3951bc7 | 2022-05-23 23:28:44 +0200 | [diff] [blame] | 752 | default 0x2000 if ARCH_X86 |
Julius Werner | 66a476a | 2015-10-12 16:45:21 -0700 | [diff] [blame] | 753 | default 0x0 |
Julius Werner | c3e7c4e | 2014-09-19 13:18:16 -0700 | [diff] [blame] | 754 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 755 | config MAX_CPUS |
| 756 | int |
| 757 | default 1 |
| 758 | |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 759 | source "src/console/Kconfig" |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 760 | |
Arthur Heymans | cbc5d3f | 2023-04-25 15:48:46 +0200 | [diff] [blame] | 761 | config ACPI_S1_NOT_SUPPORTED |
| 762 | bool |
| 763 | default n |
| 764 | help |
| 765 | Set this to 'y' on platforms that do not support ACPI S1 state. |
| 766 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 767 | config HAVE_ACPI_RESUME |
| 768 | bool |
| 769 | default n |
| 770 | |
Wim Vervoorn | bccc7e7 | 2020-01-15 11:31:25 +0100 | [diff] [blame] | 771 | config DISABLE_ACPI_HIBERNATE |
| 772 | bool |
| 773 | default n |
| 774 | help |
| 775 | Removes S4 from the available sleepstates |
| 776 | |
Aaron Durbin | 87c9fae | 2016-01-22 15:26:04 -0600 | [diff] [blame] | 777 | config RESUME_PATH_SAME_AS_BOOT |
| 778 | bool |
| 779 | default y if ARCH_X86 |
| 780 | depends on HAVE_ACPI_RESUME |
| 781 | help |
| 782 | This option indicates that when a system resumes it takes the |
| 783 | same path as a regular boot. e.g. an x86 system runs from the |
| 784 | reset vector at 0xfffffff0 on both resume and warm/cold boot. |
| 785 | |
Kyösti Mälkki | 76c4386 | 2019-07-01 17:25:41 +0300 | [diff] [blame] | 786 | config NO_MONOTONIC_TIMER |
Aaron Durbin | a421791 | 2013-04-29 22:31:51 -0500 | [diff] [blame] | 787 | def_bool n |
Kyösti Mälkki | 76c4386 | 2019-07-01 17:25:41 +0300 | [diff] [blame] | 788 | |
| 789 | config HAVE_MONOTONIC_TIMER |
| 790 | bool |
| 791 | depends on !NO_MONOTONIC_TIMER |
Kyösti Mälkki | b28b6b5 | 2019-07-01 15:38:25 +0300 | [diff] [blame] | 792 | default y |
Aaron Durbin | a421791 | 2013-04-29 22:31:51 -0500 | [diff] [blame] | 793 | help |
| 794 | The board/chipset provides a monotonic timer. |
| 795 | |
Aaron Durbin | e5e3630 | 2014-09-25 10:05:15 -0500 | [diff] [blame] | 796 | config GENERIC_UDELAY |
Kyösti Mälkki | 76c4386 | 2019-07-01 17:25:41 +0300 | [diff] [blame] | 797 | bool |
Aaron Durbin | e5e3630 | 2014-09-25 10:05:15 -0500 | [diff] [blame] | 798 | depends on HAVE_MONOTONIC_TIMER |
Kyösti Mälkki | 76c4386 | 2019-07-01 17:25:41 +0300 | [diff] [blame] | 799 | default y if !ARCH_X86 |
Aaron Durbin | e5e3630 | 2014-09-25 10:05:15 -0500 | [diff] [blame] | 800 | help |
| 801 | The board/chipset uses a generic udelay function utilizing the |
| 802 | monotonic timer. |
| 803 | |
Aaron Durbin | 340ca91 | 2013-04-30 09:58:12 -0500 | [diff] [blame] | 804 | config TIMER_QUEUE |
| 805 | def_bool n |
| 806 | depends on HAVE_MONOTONIC_TIMER |
| 807 | help |
Kyösti Mälkki | ecd8424 | 2013-09-13 07:57:49 +0300 | [diff] [blame] | 808 | Provide a timer queue for performing time-based callbacks. |
Aaron Durbin | 340ca91 | 2013-04-30 09:58:12 -0500 | [diff] [blame] | 809 | |
Aaron Durbin | 4409a5e | 2013-05-06 12:20:52 -0500 | [diff] [blame] | 810 | config COOP_MULTITASKING |
| 811 | def_bool n |
Raul E Rangel | 199c45c | 2021-11-02 11:29:33 -0600 | [diff] [blame] | 812 | select TIMER_QUEUE |
Arthur Heymans | f4c11dc | 2022-11-01 23:48:32 +0100 | [diff] [blame] | 813 | depends on ARCH_X86 |
Aaron Durbin | 4409a5e | 2013-05-06 12:20:52 -0500 | [diff] [blame] | 814 | help |
| 815 | Cooperative multitasking allows callbacks to be multiplexed on the |
Raul E Rangel | 199c45c | 2021-11-02 11:29:33 -0600 | [diff] [blame] | 816 | main thread. With this enabled it allows for multiple execution paths |
| 817 | to take place when they have udelay() calls within their code. |
Aaron Durbin | 4409a5e | 2013-05-06 12:20:52 -0500 | [diff] [blame] | 818 | |
| 819 | config NUM_THREADS |
| 820 | int |
| 821 | default 4 |
| 822 | depends on COOP_MULTITASKING |
| 823 | help |
| 824 | How many execution threads to cooperatively multitask with. |
| 825 | |
Angel Pons | 9bc780f | 2021-05-20 16:43:08 +0200 | [diff] [blame] | 826 | config HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND |
| 827 | bool |
| 828 | help |
| 829 | Selected by mainboards which implement a mainboard-specific mechanism |
| 830 | to access the values for runtime-configurable options. For example, a |
| 831 | custom BMC interface or an EEPROM with an externally-imposed layout. |
| 832 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 833 | config HAVE_OPTION_TABLE |
| 834 | bool |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 835 | default n |
Uwe Hermann | 6ba13bb | 2009-10-15 17:49:07 +0000 | [diff] [blame] | 836 | help |
| 837 | This variable specifies whether a given board has a cmos.layout |
| 838 | file containing NVRAM/CMOS bit definitions. |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 839 | It defaults to 'n' but can be selected in mainboard/*/Kconfig. |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 840 | |
Angel Pons | f206cda | 2021-05-17 12:12:39 +0200 | [diff] [blame] | 841 | config CMOS_LAYOUT_FILE |
| 842 | string |
| 843 | default "src/mainboard/\$(MAINBOARDDIR)/cmos.layout" |
| 844 | depends on HAVE_OPTION_TABLE |
| 845 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 846 | config PCI_IO_CFG_EXT |
| 847 | bool |
| 848 | default n |
| 849 | |
| 850 | config IOAPIC |
| 851 | bool |
Kyösti Mälkki | c25ecb5 | 2021-06-06 08:28:16 +0300 | [diff] [blame] | 852 | default y if SMP |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 853 | default n |
| 854 | |
Myles Watson | 45bb25f | 2009-09-22 18:49:08 +0000 | [diff] [blame] | 855 | config USE_WATCHDOG_ON_BOOT |
| 856 | bool |
| 857 | default n |
| 858 | |
Myles Watson | 45bb25f | 2009-09-22 18:49:08 +0000 | [diff] [blame] | 859 | config GFXUMA |
| 860 | bool |
Myles Watson | d73c1b5 | 2009-10-26 15:14:07 +0000 | [diff] [blame] | 861 | default n |
Myles Watson | 45bb25f | 2009-09-22 18:49:08 +0000 | [diff] [blame] | 862 | help |
| 863 | Enable Unified Memory Architecture for graphics. |
| 864 | |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame] | 865 | config HAVE_MP_TABLE |
| 866 | bool |
Uwe Hermann | 6ba13bb | 2009-10-15 17:49:07 +0000 | [diff] [blame] | 867 | help |
| 868 | This variable specifies whether a given board has MP table support. |
| 869 | It is usually set in mainboard/*/Kconfig. |
| 870 | Whether or not the MP table is actually generated by coreboot |
| 871 | is configurable by the user via GENERATE_MP_TABLE. |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame] | 872 | |
| 873 | config HAVE_PIRQ_TABLE |
| 874 | bool |
Uwe Hermann | 6ba13bb | 2009-10-15 17:49:07 +0000 | [diff] [blame] | 875 | help |
| 876 | This variable specifies whether a given board has PIRQ table support. |
| 877 | It is usually set in mainboard/*/Kconfig. |
| 878 | Whether or not the PIRQ table is actually generated by coreboot |
| 879 | is configurable by the user via GENERATE_PIRQ_TABLE. |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame] | 880 | |
Aaron Durbin | 9420a52 | 2015-11-17 16:31:00 -0600 | [diff] [blame] | 881 | config ACPI_NHLT |
| 882 | bool |
| 883 | default n |
| 884 | help |
| 885 | Build support for NHLT (non HD Audio) ACPI table generation. |
| 886 | |
Myles Watson | d73c1b5 | 2009-10-26 15:14:07 +0000 | [diff] [blame] | 887 | #These Options are here to avoid "undefined" warnings. |
| 888 | #The actual selection and help texts are in the following menu. |
| 889 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 890 | menu "System tables" |
Myles Watson | 45bb25f | 2009-09-22 18:49:08 +0000 | [diff] [blame] | 891 | |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame] | 892 | config GENERATE_MP_TABLE |
Kyösti Mälkki | ca5a793 | 2021-06-08 08:06:06 +0300 | [diff] [blame] | 893 | prompt "Generate an MP table" if HAVE_MP_TABLE |
Stefan Reinauer | 56cd70b | 2012-11-13 17:33:08 -0800 | [diff] [blame] | 894 | bool |
Kyösti Mälkki | ca5a793 | 2021-06-08 08:06:06 +0300 | [diff] [blame] | 895 | default HAVE_MP_TABLE |
Uwe Hermann | 6ba13bb | 2009-10-15 17:49:07 +0000 | [diff] [blame] | 896 | help |
| 897 | Generate an MP table (conforming to the Intel MultiProcessor |
| 898 | specification 1.4) for this board. |
| 899 | |
| 900 | If unsure, say Y. |
Myles Watson | 45bb25f | 2009-09-22 18:49:08 +0000 | [diff] [blame] | 901 | |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame] | 902 | config GENERATE_PIRQ_TABLE |
Stefan Reinauer | 56cd70b | 2012-11-13 17:33:08 -0800 | [diff] [blame] | 903 | prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE |
| 904 | bool |
| 905 | default HAVE_PIRQ_TABLE |
Uwe Hermann | 6ba13bb | 2009-10-15 17:49:07 +0000 | [diff] [blame] | 906 | help |
| 907 | Generate a PIRQ table for this board. |
| 908 | |
| 909 | If unsure, say Y. |
Myles Watson | 45bb25f | 2009-09-22 18:49:08 +0000 | [diff] [blame] | 910 | |
Sven Schnelle | 164bcfd | 2011-08-14 20:56:34 +0200 | [diff] [blame] | 911 | config GENERATE_SMBIOS_TABLES |
| 912 | depends on ARCH_X86 |
| 913 | bool "Generate SMBIOS tables" |
| 914 | default y |
| 915 | help |
| 916 | Generate SMBIOS tables for this board. |
| 917 | |
| 918 | If unsure, say Y. |
| 919 | |
Angel Pons | 437da71 | 2021-09-03 16:51:40 +0200 | [diff] [blame] | 920 | config SMBIOS_TYPE41_PROVIDED_BY_DEVTREE |
| 921 | bool |
| 922 | depends on ARCH_X86 |
| 923 | help |
| 924 | If enabled, only generate SMBIOS Type 41 entries for PCI devices in |
| 925 | the devicetree for which Type 41 information is provided, e.g. with |
| 926 | the `smbios_dev_info` devicetree syntax. This is useful to manually |
| 927 | assign specific instance IDs to onboard devices irrespective of the |
| 928 | device traversal order. It is assumed that instance IDs for devices |
| 929 | of the same class are unique. |
| 930 | When disabled, coreboot autogenerates SMBIOS Type 41 entries for all |
| 931 | appropriate PCI devices in the devicetree. Instance IDs are assigned |
| 932 | successive numbers from a monotonically increasing counter, with one |
| 933 | counter for each device class. |
| 934 | |
Vladimir Serbinenko | 0afdec4 | 2015-05-30 23:08:26 +0200 | [diff] [blame] | 935 | config SMBIOS_PROVIDED_BY_MOBO |
| 936 | bool |
| 937 | default n |
| 938 | |
Kyösti Mälkki | 96581b3 | 2022-12-16 01:42:44 +0200 | [diff] [blame] | 939 | if GENERATE_SMBIOS_TABLES |
| 940 | |
Hao Wang | 634c7a4 | 2022-06-14 10:56:40 +0800 | [diff] [blame] | 941 | config BIOS_VENDOR |
| 942 | prompt "SMBIOS BIOS Vendor name" |
| 943 | string |
| 944 | default "coreboot" |
| 945 | help |
| 946 | The BIOS Vendor name to store in the SMBIOS Type0 table. |
| 947 | |
Stefan Reinauer | 6023ca4 | 2014-10-17 13:28:15 +0200 | [diff] [blame] | 948 | config MAINBOARD_SERIAL_NUMBER |
Nico Huber | ebd8a4f | 2017-11-01 09:49:16 +0100 | [diff] [blame] | 949 | prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO |
| 950 | string |
Stefan Reinauer | 6023ca4 | 2014-10-17 13:28:15 +0200 | [diff] [blame] | 951 | default "123456789" |
Martin Roth | 595e777 | 2015-04-26 18:53:26 -0600 | [diff] [blame] | 952 | help |
Stefan Reinauer | 6023ca4 | 2014-10-17 13:28:15 +0200 | [diff] [blame] | 953 | The Serial Number to store in SMBIOS structures. |
| 954 | |
| 955 | config MAINBOARD_VERSION |
Nico Huber | ebd8a4f | 2017-11-01 09:49:16 +0100 | [diff] [blame] | 956 | prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO |
| 957 | string |
Stefan Reinauer | 6023ca4 | 2014-10-17 13:28:15 +0200 | [diff] [blame] | 958 | default "1.0" |
| 959 | help |
| 960 | The Version Number to store in SMBIOS structures. |
| 961 | |
| 962 | config MAINBOARD_SMBIOS_MANUFACTURER |
Nico Huber | ebd8a4f | 2017-11-01 09:49:16 +0100 | [diff] [blame] | 963 | prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO |
| 964 | string |
Stefan Reinauer | 6023ca4 | 2014-10-17 13:28:15 +0200 | [diff] [blame] | 965 | default MAINBOARD_VENDOR |
| 966 | help |
| 967 | Override the default Manufacturer stored in SMBIOS structures. |
| 968 | |
| 969 | config MAINBOARD_SMBIOS_PRODUCT_NAME |
Nico Huber | ebd8a4f | 2017-11-01 09:49:16 +0100 | [diff] [blame] | 970 | prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO |
| 971 | string |
Stefan Reinauer | 6023ca4 | 2014-10-17 13:28:15 +0200 | [diff] [blame] | 972 | default MAINBOARD_PART_NUMBER |
| 973 | help |
| 974 | Override the default Product name stored in SMBIOS structures. |
| 975 | |
Johnny Lin | c746a74 | 2020-06-03 11:44:22 +0800 | [diff] [blame] | 976 | config VPD_SMBIOS_VERSION |
| 977 | bool "Populates SMBIOS type 0 version from the VPD_RO variable 'firmware_version'" |
| 978 | default n |
Kyösti Mälkki | 96581b3 | 2022-12-16 01:42:44 +0200 | [diff] [blame] | 979 | depends on VPD |
Johnny Lin | c746a74 | 2020-06-03 11:44:22 +0800 | [diff] [blame] | 980 | help |
| 981 | Selecting this option will read firmware_version from |
| 982 | VPD_RO and override SMBIOS type 0 version. One special |
| 983 | scenario of using this feature is to assign a BIOS version |
| 984 | to a coreboot image without the need to rebuild from source. |
| 985 | |
Kyösti Mälkki | 96581b3 | 2022-12-16 01:42:44 +0200 | [diff] [blame] | 986 | endif |
| 987 | |
Myles Watson | 45bb25f | 2009-09-22 18:49:08 +0000 | [diff] [blame] | 988 | endmenu |
| 989 | |
Martin Roth | 21c0650 | 2016-02-04 19:52:27 -0700 | [diff] [blame] | 990 | source "payloads/Kconfig" |
Peter Stuge | a758ca2 | 2009-09-17 16:21:31 +0000 | [diff] [blame] | 991 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 992 | menu "Debugging" |
| 993 | |
Nico Huber | d67edca | 2018-11-13 19:28:07 +0100 | [diff] [blame] | 994 | comment "CPU Debug Settings" |
Arthur Heymans | aae8190 | 2019-11-04 21:50:21 +0100 | [diff] [blame] | 995 | source "src/cpu/*/Kconfig.debug_cpu" |
Nico Huber | d67edca | 2018-11-13 19:28:07 +0100 | [diff] [blame] | 996 | |
Arthur Heymans | 71bd7e4 | 2019-10-20 14:20:53 +0200 | [diff] [blame] | 997 | comment "BLOB Debug Settings" |
| 998 | source "src/drivers/intel/fsp*/Kconfig.debug_blob" |
| 999 | |
Nico Huber | d67edca | 2018-11-13 19:28:07 +0100 | [diff] [blame] | 1000 | comment "General Debug Settings" |
| 1001 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 1002 | # TODO: Better help text and detailed instructions. |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 1003 | config GDB_STUB |
Uwe Hermann | 5ec2c2b | 2009-08-25 00:53:22 +0000 | [diff] [blame] | 1004 | bool "GDB debugging support" |
Rudolf Marek | 6588802 | 2012-03-25 20:51:16 +0200 | [diff] [blame] | 1005 | default n |
Arthur Heymans | 8e98013 | 2019-11-04 09:33:04 +0100 | [diff] [blame] | 1006 | depends on DRIVERS_UART |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 1007 | help |
Uwe Hermann | 5ec2c2b | 2009-08-25 00:53:22 +0000 | [diff] [blame] | 1008 | If enabled, you will be able to set breakpoints for gdb debugging. |
Elyes Haouas | 95231b2 | 2022-02-16 22:37:44 +0100 | [diff] [blame] | 1009 | See src/arch/x86/c_start.S for details. |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 1010 | |
Denis 'GNUtoo' Carikli | e4cece0 | 2012-06-22 15:56:37 +0200 | [diff] [blame] | 1011 | config GDB_WAIT |
Denis 'GNUtoo' Carikli | 7d234f2 | 2015-12-10 21:58:52 +0100 | [diff] [blame] | 1012 | bool "Wait for a GDB connection in the ramstage" |
Denis 'GNUtoo' Carikli | e4cece0 | 2012-06-22 15:56:37 +0200 | [diff] [blame] | 1013 | default n |
| 1014 | depends on GDB_STUB |
| 1015 | help |
Denis 'GNUtoo' Carikli | 7d234f2 | 2015-12-10 21:58:52 +0100 | [diff] [blame] | 1016 | If enabled, coreboot will wait for a GDB connection in the ramstage. |
| 1017 | |
Denis 'GNUtoo' Carikli | e4cece0 | 2012-06-22 15:56:37 +0200 | [diff] [blame] | 1018 | |
Julius Werner | d82e0cf | 2015-02-17 17:27:23 -0800 | [diff] [blame] | 1019 | config FATAL_ASSERTS |
| 1020 | bool "Halt when hitting a BUG() or assertion error" |
| 1021 | default n |
| 1022 | help |
| 1023 | If enabled, coreboot will call hlt() on a BUG() or failed ASSERT(). |
| 1024 | |
Nico Huber | 371a667 | 2018-11-13 22:06:40 +0100 | [diff] [blame] | 1025 | config HAVE_DEBUG_GPIO |
| 1026 | bool |
| 1027 | |
| 1028 | config DEBUG_GPIO |
| 1029 | bool "Output verbose GPIO debug messages" |
| 1030 | depends on HAVE_DEBUG_GPIO |
| 1031 | |
Stefan Reinauer | fe42218 | 2012-05-02 16:33:18 -0700 | [diff] [blame] | 1032 | config DEBUG_CBFS |
| 1033 | bool "Output verbose CBFS debug messages" |
| 1034 | default n |
Stefan Reinauer | fe42218 | 2012-05-02 16:33:18 -0700 | [diff] [blame] | 1035 | help |
| 1036 | This option enables additional CBFS related debug messages. |
| 1037 | |
Jens Rottmann | 0d11f2d | 2010-08-26 12:46:02 +0000 | [diff] [blame] | 1038 | config HAVE_DEBUG_RAM_SETUP |
| 1039 | def_bool n |
| 1040 | |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1041 | config DEBUG_RAM_SETUP |
| 1042 | bool "Output verbose RAM init debug messages" |
| 1043 | default n |
Jens Rottmann | 0d11f2d | 2010-08-26 12:46:02 +0000 | [diff] [blame] | 1044 | depends on HAVE_DEBUG_RAM_SETUP |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1045 | help |
| 1046 | This option enables additional RAM init related debug messages. |
| 1047 | It is recommended to enable this when debugging issues on your |
| 1048 | board which might be RAM init related. |
| 1049 | |
| 1050 | Note: This option will increase the size of the coreboot image. |
| 1051 | |
| 1052 | If unsure, say N. |
| 1053 | |
Myles Watson | 80e914ff | 2010-06-01 19:25:31 +0000 | [diff] [blame] | 1054 | config DEBUG_PIRQ |
| 1055 | bool "Check PIRQ table consistency" |
| 1056 | default n |
| 1057 | depends on GENERATE_PIRQ_TABLE |
| 1058 | help |
| 1059 | If unsure, say N. |
| 1060 | |
Jens Rottmann | 0d11f2d | 2010-08-26 12:46:02 +0000 | [diff] [blame] | 1061 | config HAVE_DEBUG_SMBUS |
| 1062 | def_bool n |
| 1063 | |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1064 | config DEBUG_SMBUS |
| 1065 | bool "Output verbose SMBus debug messages" |
| 1066 | default n |
Jens Rottmann | 0d11f2d | 2010-08-26 12:46:02 +0000 | [diff] [blame] | 1067 | depends on HAVE_DEBUG_SMBUS |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1068 | help |
| 1069 | This option enables additional SMBus (and SPD) debug messages. |
| 1070 | |
| 1071 | Note: This option will increase the size of the coreboot image. |
| 1072 | |
| 1073 | If unsure, say N. |
| 1074 | |
| 1075 | config DEBUG_SMI |
| 1076 | bool "Output verbose SMI debug messages" |
| 1077 | default n |
| 1078 | depends on HAVE_SMI_HANDLER |
Angel Pons | 12d48cd | 2020-10-03 12:22:04 +0200 | [diff] [blame] | 1079 | select SPI_FLASH_SMM if EM100PRO_SPI_CONSOLE || CONSOLE_SPI_FLASH |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1080 | help |
| 1081 | This option enables additional SMI related debug messages. |
| 1082 | |
| 1083 | Note: This option will increase the size of the coreboot image. |
| 1084 | |
| 1085 | If unsure, say N. |
| 1086 | |
Kyösti Mälkki | 9446447 | 2020-06-13 13:45:42 +0300 | [diff] [blame] | 1087 | config DEBUG_PERIODIC_SMI |
| 1088 | bool "Trigger SMI periodically" |
| 1089 | depends on DEBUG_SMI |
| 1090 | |
Uwe Hermann | a953f37 | 2010-11-10 00:14:32 +0000 | [diff] [blame] | 1091 | # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional |
| 1092 | # printk(BIOS_DEBUG, ...) calls. |
| 1093 | config DEBUG_MALLOC |
Marc Jones | cf3dcd6 | 2020-12-02 11:34:17 -0700 | [diff] [blame] | 1094 | prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL |
Stefan Reinauer | 95a6396 | 2012-11-13 17:00:01 -0800 | [diff] [blame] | 1095 | bool |
Uwe Hermann | a953f37 | 2010-11-10 00:14:32 +0000 | [diff] [blame] | 1096 | default n |
Uwe Hermann | a953f37 | 2010-11-10 00:14:32 +0000 | [diff] [blame] | 1097 | help |
| 1098 | This option enables additional malloc related debug messages. |
| 1099 | |
| 1100 | Note: This option will increase the size of the coreboot image. |
| 1101 | |
| 1102 | If unsure, say N. |
Cristian Măgherușan-Stanciu | 9f52ea4 | 2011-07-02 00:44:39 +0300 | [diff] [blame] | 1103 | |
Marc Jones | 5b5c52e | 2020-10-12 11:44:46 -0600 | [diff] [blame] | 1104 | # Only visible if DEBUG_SPEW (8) is set. |
| 1105 | config DEBUG_RESOURCES |
Marc Jones | cf3dcd6 | 2020-12-02 11:34:17 -0700 | [diff] [blame] | 1106 | bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL |
Marc Jones | 5b5c52e | 2020-10-12 11:44:46 -0600 | [diff] [blame] | 1107 | default n |
| 1108 | help |
| 1109 | This option enables additional PCI memory and IO debug messages. |
| 1110 | Note: This option will increase the size of the coreboot image. |
| 1111 | If unsure, say N. |
| 1112 | |
Kyösti Mälkki | 6627795 | 2018-12-31 15:22:34 +0200 | [diff] [blame] | 1113 | config DEBUG_CONSOLE_INIT |
| 1114 | bool "Debug console initialisation code" |
| 1115 | default n |
| 1116 | help |
| 1117 | With this option printk()'s are attempted before console hardware |
| 1118 | initialisation has been completed. Your mileage may vary. |
| 1119 | |
| 1120 | Typically you will need to modify source in console_hw_init() such |
| 1121 | that a working console appears before the one you want to debug. |
| 1122 | |
| 1123 | If unsure, say N. |
| 1124 | |
Uwe Hermann | a953f37 | 2010-11-10 00:14:32 +0000 | [diff] [blame] | 1125 | # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional |
| 1126 | # printk(BIOS_DEBUG, ...) calls. |
Myles Watson | 6c9bc01 | 2010-09-07 22:30:15 +0000 | [diff] [blame] | 1127 | config REALMODE_DEBUG |
Marc Jones | cf3dcd6 | 2020-12-02 11:34:17 -0700 | [diff] [blame] | 1128 | prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL |
Stefan Reinauer | 95a6396 | 2012-11-13 17:00:01 -0800 | [diff] [blame] | 1129 | bool |
Myles Watson | 6c9bc01 | 2010-09-07 22:30:15 +0000 | [diff] [blame] | 1130 | default n |
Peter Stuge | 5015f79 | 2010-11-10 02:00:32 +0000 | [diff] [blame] | 1131 | depends on PCI_OPTION_ROM_RUN_REALMODE |
Myles Watson | 6c9bc01 | 2010-09-07 22:30:15 +0000 | [diff] [blame] | 1132 | help |
| 1133 | This option enables additional x86emu related debug messages. |
| 1134 | |
| 1135 | Note: This option will increase the time to emulate a ROM. |
| 1136 | |
| 1137 | If unsure, say N. |
| 1138 | |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1139 | config X86EMU_DEBUG |
| 1140 | bool "Output verbose x86emu debug messages" |
| 1141 | default n |
| 1142 | depends on PCI_OPTION_ROM_RUN_YABEL |
| 1143 | help |
| 1144 | This option enables additional x86emu related debug messages. |
| 1145 | |
| 1146 | Note: This option will increase the size of the coreboot image. |
| 1147 | |
| 1148 | If unsure, say N. |
| 1149 | |
Elyes Haouas | 9718e26 | 2023-05-01 17:22:03 +0200 | [diff] [blame] | 1150 | if X86EMU_DEBUG |
| 1151 | |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1152 | config X86EMU_DEBUG_JMP |
| 1153 | bool "Trace JMP/RETF" |
| 1154 | default n |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1155 | help |
| 1156 | Print information about JMP and RETF opcodes from x86emu. |
| 1157 | |
| 1158 | Note: This option will increase the size of the coreboot image. |
| 1159 | |
| 1160 | If unsure, say N. |
| 1161 | |
| 1162 | config X86EMU_DEBUG_TRACE |
| 1163 | bool "Trace all opcodes" |
| 1164 | default n |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1165 | help |
| 1166 | Print _all_ opcodes that are executed by x86emu. |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 1167 | |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1168 | WARNING: This will produce a LOT of output and take a long time. |
| 1169 | |
| 1170 | Note: This option will increase the size of the coreboot image. |
| 1171 | |
| 1172 | If unsure, say N. |
| 1173 | |
| 1174 | config X86EMU_DEBUG_PNP |
| 1175 | bool "Log Plug&Play accesses" |
| 1176 | default n |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1177 | help |
| 1178 | Print Plug And Play accesses made by option ROMs. |
| 1179 | |
| 1180 | Note: This option will increase the size of the coreboot image. |
| 1181 | |
| 1182 | If unsure, say N. |
| 1183 | |
| 1184 | config X86EMU_DEBUG_DISK |
| 1185 | bool "Log Disk I/O" |
| 1186 | default n |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1187 | help |
| 1188 | Print Disk I/O related messages. |
| 1189 | |
| 1190 | Note: This option will increase the size of the coreboot image. |
| 1191 | |
| 1192 | If unsure, say N. |
| 1193 | |
| 1194 | config X86EMU_DEBUG_PMM |
| 1195 | bool "Log PMM" |
| 1196 | default n |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1197 | help |
| 1198 | Print messages related to POST Memory Manager (PMM). |
| 1199 | |
| 1200 | Note: This option will increase the size of the coreboot image. |
| 1201 | |
| 1202 | If unsure, say N. |
| 1203 | |
| 1204 | |
| 1205 | config X86EMU_DEBUG_VBE |
| 1206 | bool "Debug VESA BIOS Extensions" |
| 1207 | default n |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1208 | help |
| 1209 | Print messages related to VESA BIOS Extension (VBE) functions. |
| 1210 | |
| 1211 | Note: This option will increase the size of the coreboot image. |
| 1212 | |
| 1213 | If unsure, say N. |
| 1214 | |
| 1215 | config X86EMU_DEBUG_INT10 |
| 1216 | bool "Redirect INT10 output to console" |
| 1217 | default n |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1218 | help |
| 1219 | Let INT10 (i.e. character output) calls print messages to debug output. |
| 1220 | |
| 1221 | Note: This option will increase the size of the coreboot image. |
| 1222 | |
| 1223 | If unsure, say N. |
| 1224 | |
| 1225 | config X86EMU_DEBUG_INTERRUPTS |
| 1226 | bool "Log intXX calls" |
| 1227 | default n |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1228 | help |
| 1229 | Print messages related to interrupt handling. |
| 1230 | |
| 1231 | Note: This option will increase the size of the coreboot image. |
| 1232 | |
| 1233 | If unsure, say N. |
| 1234 | |
| 1235 | config X86EMU_DEBUG_CHECK_VMEM_ACCESS |
| 1236 | bool "Log special memory accesses" |
| 1237 | default n |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1238 | help |
| 1239 | Print messages related to accesses to certain areas of the virtual |
| 1240 | memory (e.g. BDA (BIOS Data Area) or interrupt vectors) |
| 1241 | |
| 1242 | Note: This option will increase the size of the coreboot image. |
| 1243 | |
| 1244 | If unsure, say N. |
| 1245 | |
| 1246 | config X86EMU_DEBUG_MEM |
| 1247 | bool "Log all memory accesses" |
| 1248 | default n |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1249 | help |
| 1250 | Print memory accesses made by option ROM. |
| 1251 | Note: This also includes accesses to fetch instructions. |
| 1252 | |
| 1253 | Note: This option will increase the size of the coreboot image. |
| 1254 | |
| 1255 | If unsure, say N. |
| 1256 | |
| 1257 | config X86EMU_DEBUG_IO |
| 1258 | bool "Log IO accesses" |
| 1259 | default n |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 1260 | help |
| 1261 | Print I/O accesses made by option ROM. |
| 1262 | |
| 1263 | Note: This option will increase the size of the coreboot image. |
| 1264 | |
| 1265 | If unsure, say N. |
| 1266 | |
Denis 'GNUtoo' Carikli | 4cdc5d6 | 2013-05-15 00:19:49 +0200 | [diff] [blame] | 1267 | config X86EMU_DEBUG_TIMINGS |
| 1268 | bool "Output timing information" |
| 1269 | default n |
Elyes Haouas | 9718e26 | 2023-05-01 17:22:03 +0200 | [diff] [blame] | 1270 | depends on HAVE_MONOTONIC_TIMER |
Denis 'GNUtoo' Carikli | 4cdc5d6 | 2013-05-15 00:19:49 +0200 | [diff] [blame] | 1271 | help |
| 1272 | Print timing information needed by i915tool. |
| 1273 | |
| 1274 | If unsure, say N. |
| 1275 | |
Elyes Haouas | 9718e26 | 2023-05-01 17:22:03 +0200 | [diff] [blame] | 1276 | endif |
| 1277 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 1278 | config DEBUG_SPI_FLASH |
| 1279 | bool "Output verbose SPI flash debug messages" |
| 1280 | default n |
| 1281 | depends on SPI_FLASH |
| 1282 | help |
| 1283 | This option enables additional SPI flash related debug messages. |
| 1284 | |
Marc Jones | dc12daf | 2021-04-16 14:26:08 -0600 | [diff] [blame] | 1285 | config DEBUG_IPMI |
| 1286 | bool "Output verbose IPMI debug messages" |
| 1287 | default n |
| 1288 | depends on IPMI_KCS |
| 1289 | help |
| 1290 | This option enables additional IPMI related debug messages. |
| 1291 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1292 | if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8 |
| 1293 | # Only visible with the right southbridge and loglevel. |
| 1294 | config DEBUG_INTEL_ME |
| 1295 | bool "Verbose logging for Intel Management Engine" |
| 1296 | default n |
| 1297 | help |
| 1298 | Enable verbose logging for Intel Management Engine driver that |
| 1299 | is present on Intel 6-series chipsets. |
| 1300 | endif |
| 1301 | |
Marc Jones | 8b522db | 2020-10-12 11:58:46 -0600 | [diff] [blame] | 1302 | config DEBUG_FUNC |
Marc Jones | c6076ef | 2021-11-11 12:07:46 -0700 | [diff] [blame] | 1303 | bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL |
Marc Jones | 8b522db | 2020-10-12 11:58:46 -0600 | [diff] [blame] | 1304 | default n |
| 1305 | help |
| 1306 | This option enables additional function entry and exit debug messages |
Kyösti Mälkki | 8c99c27 | 2020-07-24 15:54:31 +0300 | [diff] [blame] | 1307 | for select functions. |
Marc Jones | 8b522db | 2020-10-12 11:58:46 -0600 | [diff] [blame] | 1308 | Note: This option will increase the size of the coreboot image. |
| 1309 | If unsure, say N. |
| 1310 | |
Stefan Reinauer | d37ab45 | 2012-12-18 16:23:28 -0800 | [diff] [blame] | 1311 | config DEBUG_COVERAGE |
| 1312 | bool "Debug code coverage" |
| 1313 | default n |
| 1314 | depends on COVERAGE |
| 1315 | help |
| 1316 | If enabled, the code coverage hooks in coreboot will output some |
| 1317 | information about the coverage data that is dumped. |
| 1318 | |
Jonathan Neuschäfer | fc04f9b | 2016-06-29 21:59:32 +0200 | [diff] [blame] | 1319 | config DEBUG_BOOT_STATE |
| 1320 | bool "Debug boot state machine" |
| 1321 | default n |
| 1322 | help |
| 1323 | Control debugging of the boot state machine. When selected displays |
| 1324 | the state boundaries in ramstage. |
| 1325 | |
Nico Huber | e84e625 | 2016-10-05 17:43:56 +0200 | [diff] [blame] | 1326 | config DEBUG_ADA_CODE |
| 1327 | bool "Compile debug code in Ada sources" |
| 1328 | default n |
| 1329 | help |
| 1330 | Add the compiler switch `-gnata` to compile code guarded by |
| 1331 | `pragma Debug`. |
| 1332 | |
Simon Glass | 46255f7 | 2018-07-12 15:26:07 -0600 | [diff] [blame] | 1333 | config HAVE_EM100_SUPPORT |
Arthur Heymans | 1842aa2 | 2022-04-17 20:10:41 +0200 | [diff] [blame] | 1334 | bool |
Simon Glass | 46255f7 | 2018-07-12 15:26:07 -0600 | [diff] [blame] | 1335 | help |
| 1336 | This is enabled by platforms which can support using the EM100. |
| 1337 | |
| 1338 | config EM100 |
| 1339 | bool "Configure image for EM100 usage" |
| 1340 | depends on HAVE_EM100_SUPPORT |
| 1341 | help |
| 1342 | The Dediprog EM100 SPI emulator allows fast loading of new SPI images |
| 1343 | over USB. However it only supports a maximum SPI clock of 20MHz and |
| 1344 | single data output. Enable this option to use a 20MHz SPI clock and |
| 1345 | disable "Dual Output Fast Read" Support. |
| 1346 | |
| 1347 | On AMD platforms this changes the SPI speed at run-time if the |
| 1348 | mainboard code supports this. On supported Intel platforms this works |
| 1349 | by changing the settings in the descriptor.bin file. |
| 1350 | |
Arthur Heymans | 0ad766c | 2023-06-07 10:45:59 +0200 | [diff] [blame] | 1351 | config DEBUG_ACPICA_COMPATIBLE |
| 1352 | bool "Print out ACPI tables in ACPICA compatible format" |
| 1353 | depends on HAVE_ACPI_TABLES |
| 1354 | help |
| 1355 | Select this to print out ACPI tables in an ACPICA compatible |
| 1356 | format. Set the console loglevel to verbosity 'SPEW'. |
| 1357 | To analyze ACPI tables capture the coreboot log between |
| 1358 | "Printing ACPI in ACPICA compatible table" and "Done printing |
| 1359 | ACPI in ACPICA compatible table". |
| 1360 | Remove the prefix "[SPEW ] " and then issue 'acpixtract -a dump' |
| 1361 | to extract all the tables. Then use 'iasl -d' on the .dat files |
| 1362 | to decompile the tables. |
| 1363 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 1364 | endmenu |
| 1365 | |
Martin Roth | 8e4aafb | 2016-12-15 15:25:15 -0700 | [diff] [blame] | 1366 | ############################################################################### |
| 1367 | # Set variables with no prompt - these can be set anywhere, and putting at |
| 1368 | # the end of this file gives the most flexibility. |
Nico Huber | 3db7653 | 2017-05-18 18:07:34 +0200 | [diff] [blame] | 1369 | |
| 1370 | source "src/lib/Kconfig" |
| 1371 | |
Myles Watson | 2e67273 | 2009-11-12 16:38:03 +0000 | [diff] [blame] | 1372 | config WARNINGS_ARE_ERRORS |
| 1373 | bool |
Edward O'Callaghan | 63f6dc7 | 2014-11-18 03:17:54 +1100 | [diff] [blame] | 1374 | default y |
Patrick Georgi | 436f99b | 2009-11-27 16:55:13 +0000 | [diff] [blame] | 1375 | |
Peter Stuge | 51eafde | 2010-10-13 06:23:02 +0000 | [diff] [blame] | 1376 | # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, |
| 1377 | # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are |
| 1378 | # mutually exclusive. One of these options must be selected in the |
| 1379 | # mainboard Kconfig if the chipset supports enabling and disabling of |
| 1380 | # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set |
| 1381 | # in mainboard/Kconfig to know if the button should be enabled or not. |
| 1382 | |
| 1383 | config POWER_BUTTON_DEFAULT_ENABLE |
| 1384 | def_bool n |
| 1385 | help |
| 1386 | Select when the board has a power button which can optionally be |
| 1387 | disabled by the user. |
| 1388 | |
| 1389 | config POWER_BUTTON_DEFAULT_DISABLE |
| 1390 | def_bool n |
| 1391 | help |
| 1392 | Select when the board has a power button which can optionally be |
| 1393 | enabled by the user, e.g. when the board ships with a jumper over |
| 1394 | the power switch contacts. |
| 1395 | |
| 1396 | config POWER_BUTTON_FORCE_ENABLE |
| 1397 | def_bool n |
| 1398 | help |
| 1399 | Select when the board requires that the power button is always |
| 1400 | enabled. |
| 1401 | |
| 1402 | config POWER_BUTTON_FORCE_DISABLE |
| 1403 | def_bool n |
| 1404 | help |
| 1405 | Select when the board requires that the power button is always |
| 1406 | disabled, e.g. when it has been hardwired to ground. |
| 1407 | |
| 1408 | config POWER_BUTTON_IS_OPTIONAL |
| 1409 | bool |
| 1410 | default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE |
| 1411 | default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE) |
| 1412 | help |
| 1413 | Internal option that controls ENABLE_POWER_BUTTON visibility. |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 1414 | |
| 1415 | config REG_SCRIPT |
| 1416 | bool |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 1417 | default n |
| 1418 | help |
| 1419 | Internal option that controls whether we compile in register scripts. |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 1420 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 1421 | config MAX_REBOOT_CNT |
| 1422 | int |
| 1423 | default 3 |
Timothy Pearson | 17ada2e | 2015-03-18 01:31:34 -0500 | [diff] [blame] | 1424 | help |
| 1425 | Internal option that sets the maximum number of bootblock executions allowed |
| 1426 | with the normal image enabled before assuming the normal image is defective |
Vadim Bendebury | 9c9c336 | 2014-07-23 09:40:02 -0700 | [diff] [blame] | 1427 | and switching to the fallback image. |
Martin Roth | 59ff340 | 2016-02-09 09:06:46 -0700 | [diff] [blame] | 1428 | |
Martin Roth | 8e4aafb | 2016-12-15 15:25:15 -0700 | [diff] [blame] | 1429 | config UNCOMPRESSED_RAMSTAGE |
| 1430 | bool |
| 1431 | |
| 1432 | config NO_XIP_EARLY_STAGES |
| 1433 | bool |
| 1434 | default n if ARCH_X86 |
| 1435 | default y |
| 1436 | help |
| 1437 | Identify if early stages are eXecute-In-Place(XIP). |
| 1438 | |
Martin Roth | 8e4aafb | 2016-12-15 15:25:15 -0700 | [diff] [blame] | 1439 | config EARLY_CBMEM_LIST |
| 1440 | bool |
| 1441 | default n |
| 1442 | help |
| 1443 | Enable display of CBMEM during romstage and postcar. |
| 1444 | |
| 1445 | config RELOCATABLE_MODULES |
| 1446 | bool |
| 1447 | help |
| 1448 | If RELOCATABLE_MODULES is selected then support is enabled for |
| 1449 | building relocatable modules in the RAM stage. Those modules can be |
| 1450 | loaded anywhere and all the relocations are handled automatically. |
| 1451 | |
Martin Roth | 8e4aafb | 2016-12-15 15:25:15 -0700 | [diff] [blame] | 1452 | config GENERIC_GPIO_LIB |
| 1453 | bool |
| 1454 | help |
| 1455 | If enabled, compile the generic GPIO library. A "generic" GPIO |
| 1456 | implies configurability usually found on SoCs, particularly the |
| 1457 | ability to control internal pull resistors. |
| 1458 | |
Martin Roth | 8e4aafb | 2016-12-15 15:25:15 -0700 | [diff] [blame] | 1459 | config BOOTBLOCK_CUSTOM |
| 1460 | # To be selected by arch, SoC or mainboard if it does not want use the normal |
| 1461 | # src/lib/bootblock.c#main() C entry point. |
| 1462 | bool |
| 1463 | |
Arthur Heymans | e8217b1 | 2022-04-05 20:42:07 +0200 | [diff] [blame] | 1464 | config BOOTBLOCK_IN_CBFS |
| 1465 | bool |
| 1466 | default y if ARCH_X86 |
| 1467 | help |
| 1468 | Select this on platforms that have a top aligned bootblock inside cbfs. |
| 1469 | |
Furquan Shaikh | 46514c2 | 2020-06-11 11:59:07 -0700 | [diff] [blame] | 1470 | config MEMLAYOUT_LD_FILE |
| 1471 | string |
Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 1472 | default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/memlayout.ld" |
Furquan Shaikh | 46514c2 | 2020-06-11 11:59:07 -0700 | [diff] [blame] | 1473 | help |
| 1474 | This variable allows SoC/mainboard to supply in a custom linker file |
| 1475 | if required. This determines the linker file used for all the stages |
| 1476 | (bootblock, romstage, verstage, ramstage, postcar) in |
| 1477 | src/arch/${ARCH}/Makefile.inc. |
| 1478 | |
Martin Roth | 75e5cb7 | 2016-12-15 15:05:37 -0700 | [diff] [blame] | 1479 | ############################################################################### |
| 1480 | # Set default values for symbols created before mainboards. This allows the |
| 1481 | # option to be displayed in the general menu, but the default to be loaded in |
| 1482 | # the mainboard if desired. |
Martin Roth | 75e5cb7 | 2016-12-15 15:05:37 -0700 | [diff] [blame] | 1483 | config COMPRESS_PRERAM_STAGES |
Arthur Heymans | e146fbd | 2019-11-04 18:57:06 +0100 | [diff] [blame] | 1484 | depends on (HAVE_ROMSTAGE || HAVE_VERSTAGE) && NO_XIP_EARLY_STAGES |
Martin Roth | 75e5cb7 | 2016-12-15 15:05:37 -0700 | [diff] [blame] | 1485 | default y |
| 1486 | |
| 1487 | config INCLUDE_CONFIG_FILE |
| 1488 | default y |
| 1489 | |
Martin Roth | 75e5cb7 | 2016-12-15 15:05:37 -0700 | [diff] [blame] | 1490 | config BOOTSPLASH_FILE |
| 1491 | depends on BOOTSPLASH_IMAGE |
| 1492 | default "bootsplash.jpg" |
| 1493 | |
Nico Huber | 799e79d | 2023-07-16 19:24:13 +0200 | [diff] [blame] | 1494 | config BOOTSPLASH_CONVERT_QUALITY |
| 1495 | depends on BOOTSPLASH_CONVERT |
| 1496 | default 80 |
| 1497 | |
| 1498 | config BOOTSPLASH_CONVERT_RESOLUTION |
| 1499 | depends on BOOTSPLASH_CONVERT_RESIZE |
| 1500 | default "1024x768" |
| 1501 | |
Martin Roth | 75e5cb7 | 2016-12-15 15:05:37 -0700 | [diff] [blame] | 1502 | config CBFS_SIZE |
| 1503 | default ROM_SIZE |
Subrata Banik | b5962a9 | 2019-06-08 12:29:02 +0530 | [diff] [blame] | 1504 | |
| 1505 | config HAVE_BOOTBLOCK |
| 1506 | bool |
| 1507 | default y |
| 1508 | |
| 1509 | config HAVE_VERSTAGE |
| 1510 | bool |
| 1511 | depends on VBOOT_SEPARATE_VERSTAGE |
| 1512 | default y |
| 1513 | |
| 1514 | config HAVE_ROMSTAGE |
| 1515 | bool |
| 1516 | default y |
| 1517 | |
Subrata Banik | b5962a9 | 2019-06-08 12:29:02 +0530 | [diff] [blame] | 1518 | config HAVE_RAMSTAGE |
| 1519 | bool |
| 1520 | default n if RAMPAYLOAD |
| 1521 | default y |