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Patrick Georgi0588d192009-08-12 15:00:51 +00001##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00002## This file is part of the coreboot project.
Patrick Georgi0588d192009-08-12 15:00:51 +00003##
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -05004## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
Stefan Reinauer16f515a2010-01-20 18:44:30 +00005## Copyright (C) 2009-2010 coresystems GmbH
Patrick Georgi0588d192009-08-12 15:00:51 +00006##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00007## This program is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; version 2 of the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +010018## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Patrick Georgi0588d192009-08-12 15:00:51 +000019##
20
Uwe Hermannad8c95f2012-04-12 22:00:03 +020021mainmenu "coreboot configuration"
Patrick Georgi0588d192009-08-12 15:00:51 +000022
Uwe Hermannc04be932009-10-05 13:55:28 +000023menu "General setup"
24
Uwe Hermanna29ad5c2009-10-18 18:35:50 +000025config EXPERT
26 bool "Expert mode"
27 help
28 This allows you to select certain advanced configuration options.
29
30 Warning: Only enable this option if you really know what you are
31 doing! You have been warned!
32
Uwe Hermannc04be932009-10-05 13:55:28 +000033config LOCALVERSION
Uwe Hermann168b11b2009-10-07 16:15:40 +000034 string "Local version string"
Uwe Hermannc04be932009-10-05 13:55:28 +000035 help
36 Append an extra string to the end of the coreboot version.
37
Uwe Hermann168b11b2009-10-07 16:15:40 +000038 This can be useful if, for instance, you want to append the
39 respective board's hostname or some other identifying string to
40 the coreboot version number, so that you can easily distinguish
41 boot logs of different boards from each other.
42
Patrick Georgi4b8a2412010-02-09 19:35:16 +000043config CBFS_PREFIX
44 string "CBFS prefix to use"
45 default "fallback"
46 help
47 Select the prefix to all files put into the image. It's "fallback"
48 by default, "normal" is a common alternative.
49
Aaron Durbin81108b92013-01-22 13:22:02 -060050config ALT_CBFS_LOAD_PAYLOAD
51 bool "Use alternative cbfs_load_payload() implementation."
52 default n
53 help
54 Either board or southbridge provide an alternative cbfs_load_payload()
55 implementation. This may be used, for example, if accessing the ROM
56 through memory-mapped I/O is slow and a faster alternative can be
57 provided.
58
Patrick Georgi23d89cc2010-03-16 01:17:19 +000059choice
Uwe Hermannad8c95f2012-04-12 22:00:03 +020060 prompt "Compiler to use"
Patrick Georgi23d89cc2010-03-16 01:17:19 +000061 default COMPILER_GCC
62 help
63 This option allows you to select the compiler used for building
64 coreboot.
65
66config COMPILER_GCC
67 bool "GCC"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020068 help
69 Use the GNU Compiler Collection (GCC) to build coreboot.
70
71 For details see http://gcc.gnu.org.
72
Patrick Georgi23d89cc2010-03-16 01:17:19 +000073config COMPILER_LLVM_CLANG
74 bool "LLVM/clang"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020075 help
76 Use LLVM/clang to build coreboot.
77
78 For details see http://clang.llvm.org.
79
Patrick Georgi23d89cc2010-03-16 01:17:19 +000080endchoice
81
Patrick Georgi020f51f2010-03-14 21:25:03 +000082config SCANBUILD_ENABLE
Uwe Hermannad8c95f2012-04-12 22:00:03 +020083 bool "Build with scan-build for static code analysis"
Patrick Georgi020f51f2010-03-14 21:25:03 +000084 default n
85 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +020086 Changes the build process to use scan-build (a utility for
87 running the clang static code analyzer from the command line).
88
89 Requires the scan-build utility in your system $PATH.
90
91 For details see http://clang-analyzer.llvm.org/scan-build.html.
Patrick Georgi020f51f2010-03-14 21:25:03 +000092
93config SCANBUILD_REPORT_LOCATION
Uwe Hermannad8c95f2012-04-12 22:00:03 +020094 string "Directory for the scan-build report(s)"
Patrick Georgi020f51f2010-03-14 21:25:03 +000095 default ""
96 depends on SCANBUILD_ENABLE
97 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +020098 Directory where the scan-build reports should be stored in. The
99 reports are stored in subdirectories of the form 'yyyy-mm-dd-*'
100 in the specified directory.
101
102 If this setting is left empty, the coreboot top-level directory
103 will be used to store the report subdirectories.
Patrick Georgi020f51f2010-03-14 21:25:03 +0000104
Patrick Georgi516a2a72010-03-25 21:45:25 +0000105config CCACHE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200106 bool "Use ccache to speed up (re)compilation"
Patrick Georgi516a2a72010-03-25 21:45:25 +0000107 default n
108 help
109 Enables the use of ccache for faster builds.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200110
111 Requires the ccache utility in your system $PATH.
112
113 For details see https://ccache.samba.org.
Patrick Georgi516a2a72010-03-25 21:45:25 +0000114
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000115config SCONFIG_GENPARSER
116 bool "Generate SCONFIG parser using flex and bison"
117 default n
118 depends on EXPERT
119 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200120 Enable this option if you are working on the sconfig device tree
121 parser and made changes to sconfig.l and sconfig.y.
122
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000123 Otherwise, say N.
124
Joe Korty6d772522010-05-19 18:41:15 +0000125config USE_OPTION_TABLE
126 bool "Use CMOS for configuration values"
127 default n
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000128 depends on HAVE_OPTION_TABLE
Joe Korty6d772522010-05-19 18:41:15 +0000129 help
130 Enable this option if coreboot shall read options from the "CMOS"
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200131 NVRAM instead of using hard-coded values.
Joe Korty6d772522010-05-19 18:41:15 +0000132
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000133config COMPRESS_RAMSTAGE
134 bool "Compress ramstage with LZMA"
135 default y
136 help
137 Compress ramstage to save memory in the flash image. Note
138 that decompression might slow down booting if the boot flash
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200139 is connected through a slow link (i.e. SPI).
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000140
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200141config INCLUDE_CONFIG_FILE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200142 bool "Include the coreboot .config file into the ROM image"
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200143 default y
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200144 help
145 Include the .config file that was used to compile coreboot
146 in the (CBFS) ROM image. This is useful if you want to know which
147 options were used to build a specific coreboot.rom image.
148
149 Saying Y here will increase the image size by 2-3kB.
150
151 You can use the following command to easily list the options:
152
153 grep -a CONFIG_ coreboot.rom
154
155 Alternatively, you can also use cbfstool to print the image
156 contents (including the raw 'config' item we're looking for).
157
158 Example:
159
160 $ cbfstool coreboot.rom print
161 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
162 offset 0x0
163 Alignment: 64 bytes
Steve Goodrichf0269122012-05-18 11:18:47 -0600164
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200165 Name Offset Type Size
166 cmos_layout.bin 0x0 cmos layout 1159
167 fallback/romstage 0x4c0 stage 339756
168 fallback/coreboot_ram 0x53440 stage 186664
169 fallback/payload 0x80dc0 payload 51526
170 config 0x8d740 raw 3324
171 (empty) 0x8e480 null 3610440
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200172
Vadim Bendeburye6b6aff2011-09-20 16:46:46 -0700173config EARLY_CBMEM_INIT
Stefan Reinauer1bc9efa2013-02-28 01:18:29 +0100174 bool
Vadim Bendeburye6b6aff2011-09-20 16:46:46 -0700175 default n
176 help
Paul Menzele62b8e92013-04-26 17:15:07 +0200177 Make coreboot initialize the CBMEM structures while running in ROM
Stefan Reinauer1bc9efa2013-02-28 01:18:29 +0100178 stage. This is useful when the ROM stage wants to communicate
179 some, for instance, execution timestamps. It needs support in
180 romstage.c and should be enabled by the board's Kconfig.
Vadim Bendeburye6b6aff2011-09-20 16:46:46 -0700181
Aaron Durbindf3a1092013-03-13 12:41:44 -0500182config DYNAMIC_CBMEM
183 bool "The CBMEM space is dynamically grown."
184 default n
185 help
186 Instead of reserving a static amount of CBMEM space the CBMEM
187 area grows dynamically. CBMEM can be used both in romstage (after
188 memory initialization) and ramstage.
189
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700190config COLLECT_TIMESTAMPS
191 bool "Create a table of timestamps collected during boot"
Aaron Durbinc15551a2013-03-23 00:00:54 -0500192 depends on (EARLY_CBMEM_INIT || DYNAMIC_CBMEM)
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700193 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200194 Make coreboot create a table of timer-ID/timer-value pairs to
195 allow measuring time spent at different phases of the boot process.
196
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200197config USE_BLOBS
198 bool "Allow use of binary-only repository"
199 default n
200 help
201 This draws in the blobs repository, which contains binary files that
202 might be required for some chipsets or boards.
203 This flag ensures that a "Free" option remains available for users.
204
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800205config COVERAGE
206 bool "Code coverage support"
207 depends on COMPILER_GCC
208 default n
209 help
210 Add code coverage support for coreboot. This will store code
211 coverage information in CBMEM for extraction from user space.
212 If unsure, say N.
213
Uwe Hermannc04be932009-10-05 13:55:28 +0000214endmenu
215
Patrick Georgi0588d192009-08-12 15:00:51 +0000216source src/mainboard/Kconfig
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000217
218# This option is used to set the architecture of a mainboard to X86.
219# It is usually set in mainboard/*/Kconfig.
220config ARCH_X86
221 bool
222 default n
Ronald G. Minnich78a16672012-11-29 16:28:21 -0800223 select PCI
224
David Hendricks5367e472012-11-28 20:16:28 -0800225config ARCH_ARMV7
226 bool
227 default n
228
Ronald G. Minnich6e3728b2012-11-27 10:36:06 -0800229# Warning: The file is included whether or not the if is here.
230# but the if controls how the evaluation occurs.
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000231if ARCH_X86
Stefan Reinauer8677a232010-12-11 20:33:41 +0000232source src/arch/x86/Kconfig
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000233endif
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000234
David Hendricks5367e472012-11-28 20:16:28 -0800235if ARCH_ARMV7
236source src/arch/armv7/Kconfig
237endif
238
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000239menu "Chipset"
240
241comment "CPU"
Patrick Georgi0588d192009-08-12 15:00:51 +0000242source src/cpu/Kconfig
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000243comment "Northbridge"
244source src/northbridge/Kconfig
245comment "Southbridge"
246source src/southbridge/Kconfig
247comment "Super I/O"
248source src/superio/Kconfig
Sven Schnelle7592e8b2011-01-27 11:43:03 +0000249comment "Embedded Controllers"
250source src/ec/Kconfig
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000251
252endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000253
Stefan Reinauer8d711552012-11-30 12:34:04 -0800254source src/device/Kconfig
Stefan Reinauer95a63962012-11-13 17:00:01 -0800255
Rudolf Marekd9c25492010-05-16 15:31:53 +0000256menu "Generic Drivers"
257source src/drivers/Kconfig
258endmenu
259
Patrick Georgi0588d192009-08-12 15:00:51 +0000260config HEAP_SIZE
261 hex
Myles Watson04000f42009-10-16 19:12:49 +0000262 default 0x4000
Patrick Georgi0588d192009-08-12 15:00:51 +0000263
Patrick Georgi0588d192009-08-12 15:00:51 +0000264config MAX_CPUS
265 int
266 default 1
267
268config MMCONF_SUPPORT_DEFAULT
269 bool
270 default n
271
272config MMCONF_SUPPORT
273 bool
274 default n
275
Patrick Georgi0588d192009-08-12 15:00:51 +0000276source src/console/Kconfig
277
Stefan Reinauer4885daa2011-04-26 23:47:04 +0000278# This should default to N and be set by SuperI/O drivers that have an UART
279config HAVE_UART_IO_MAPPED
280 bool
Stefan Reinauer3600e962012-12-11 12:49:32 -0800281 default y if ARCH_X86
282 default n if ARCH_ARMV7
Stefan Reinauer4885daa2011-04-26 23:47:04 +0000283
284config HAVE_UART_MEMORY_MAPPED
285 bool
286 default n
287
Hung-Te Linad173ea2013-02-06 21:24:12 +0800288config HAVE_UART_SPECIAL
289 bool
290 default n
291
Patrick Georgi0588d192009-08-12 15:00:51 +0000292config HAVE_ACPI_RESUME
293 bool
294 default n
295
Stefan Reinauerc4f1a772010-06-05 10:03:08 +0000296config HAVE_ACPI_SLIC
297 bool
298 default n
299
Patrick Georgi0588d192009-08-12 15:00:51 +0000300config ACPI_SSDTX_NUM
301 int
302 default 0
303
Patrick Georgi0588d192009-08-12 15:00:51 +0000304config HAVE_HARD_RESET
305 bool
Uwe Hermann748475b2009-10-09 11:47:21 +0000306 default n
Patrick Georgi37bdb872010-02-27 08:39:04 +0000307 help
308 This variable specifies whether a given board has a hard_reset
309 function, no matter if it's provided by board code or chipset code.
310
Patrick Georgi0588d192009-08-12 15:00:51 +0000311config HAVE_INIT_TIMER
312 bool
Patrick Georgi1f807fd2010-01-04 20:09:27 +0000313 default n if UDELAY_IO
Myles Watsond73c1b52009-10-26 15:14:07 +0000314 default y
Patrick Georgi0588d192009-08-12 15:00:51 +0000315
Aaron Durbina4217912013-04-29 22:31:51 -0500316config HAVE_MONOTONIC_TIMER
317 def_bool n
318 help
319 The board/chipset provides a monotonic timer.
320
Aaron Durbin340ca912013-04-30 09:58:12 -0500321config TIMER_QUEUE
322 def_bool n
323 depends on HAVE_MONOTONIC_TIMER
324 help
325 Provide a timer queue for performing time-based callbacks.
326
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500327config COOP_MULTITASKING
328 def_bool n
329 depends on TIMER_QUEUE
330 help
331 Cooperative multitasking allows callbacks to be multiplexed on the
332 main thread of ramstage. With this enabled it allows for multiple
333 execution paths to take place when they have udelay() calls within
334 their code.
335
336config NUM_THREADS
337 int
338 default 4
339 depends on COOP_MULTITASKING
340 help
341 How many execution threads to cooperatively multitask with.
342
zbaof7223732012-04-13 13:42:15 +0800343config HIGH_SCRATCH_MEMORY_SIZE
344 hex
345 default 0x0
346
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000347config USE_OPTION_TABLE
348 bool
349 default n
350
Patrick Georgi0588d192009-08-12 15:00:51 +0000351config HAVE_OPTION_TABLE
352 bool
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000353 default n
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000354 help
355 This variable specifies whether a given board has a cmos.layout
356 file containing NVRAM/CMOS bit definitions.
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000357 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
Patrick Georgi0588d192009-08-12 15:00:51 +0000358
Patrick Georgi0588d192009-08-12 15:00:51 +0000359config PIRQ_ROUTE
360 bool
361 default n
362
363config HAVE_SMI_HANDLER
364 bool
365 default n
366
367config PCI_IO_CFG_EXT
368 bool
369 default n
370
371config IOAPIC
372 bool
373 default n
374
Stefan Reinauer5b635792012-08-16 14:05:42 -0700375config CBFS_SIZE
376 hex
377 default ROM_SIZE
378
379config CACHE_ROM_SIZE
380 hex
381 default CBFS_SIZE
382
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000383# TODO: Can probably be removed once all chipsets have kconfig options for it.
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000384config VIDEO_MB
385 int
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000386 default 0
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000387
Myles Watson45bb25f2009-09-22 18:49:08 +0000388config USE_WATCHDOG_ON_BOOT
389 bool
390 default n
391
392config VGA
393 bool
394 default n
395 help
396 Build board-specific VGA code.
397
398config GFXUMA
399 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000400 default n
Myles Watson45bb25f2009-09-22 18:49:08 +0000401 help
402 Enable Unified Memory Architecture for graphics.
403
Aaron Durbinad935522012-12-24 14:28:37 -0600404config RELOCATABLE_MODULES
405 bool "Relocatable Modules"
406 default n
407 help
408 If RELOCATABLE_MODULES is selected then support is enabled for
409 building relocatable modules in the ram stage. Those modules can be
410 loaded anywhere and all the relocations are handled automatically.
411
Aaron Durbin8e4a3552013-02-08 17:28:04 -0600412config RELOCATABLE_RAMSTAGE
Aaron Durbindd4a6d22013-02-27 22:50:12 -0600413 depends on (RELOCATABLE_MODULES && DYNAMIC_CBMEM)
Aaron Durbin8e4a3552013-02-08 17:28:04 -0600414 bool "Build the ramstage to be relocatable in 32-bit address space."
415 default n
416 help
417 The reloctable ramstage support allows for the ramstage to be built
418 as a relocatable module. The stage loader can identify a place
419 out of the OS way so that copying memory is unnecessary during an S3
420 wake. When selecting this option the romstage is responsible for
421 determing a stack location to use for loading the ramstage.
422
Myles Watsonb8e20272009-10-15 13:35:47 +0000423config HAVE_ACPI_TABLES
424 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000425 help
426 This variable specifies whether a given board has ACPI table support.
427 It is usually set in mainboard/*/Kconfig.
428 Whether or not the ACPI tables are actually generated by coreboot
429 is configurable by the user via GENERATE_ACPI_TABLES.
Myles Watsonb8e20272009-10-15 13:35:47 +0000430
431config HAVE_MP_TABLE
432 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000433 help
434 This variable specifies whether a given board has MP table support.
435 It is usually set in mainboard/*/Kconfig.
436 Whether or not the MP table is actually generated by coreboot
437 is configurable by the user via GENERATE_MP_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000438
439config HAVE_PIRQ_TABLE
440 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000441 help
442 This variable specifies whether a given board has PIRQ table support.
443 It is usually set in mainboard/*/Kconfig.
444 Whether or not the PIRQ table is actually generated by coreboot
445 is configurable by the user via GENERATE_PIRQ_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000446
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -0500447config MAX_PIRQ_LINKS
448 int
449 default 4
450 help
451 This variable specifies the number of PIRQ interrupt links which are
452 routable. On most chipsets, this is 4, INTA through INTD. Some
453 chipsets offer more than four links, commonly up to INTH. They may
454 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
455 table specifies links greater than 4, pirq_route_irqs will not
456 function properly, unless this variable is correctly set.
457
Myles Watsond73c1b52009-10-26 15:14:07 +0000458#These Options are here to avoid "undefined" warnings.
459#The actual selection and help texts are in the following menu.
460
Uwe Hermann168b11b2009-10-07 16:15:40 +0000461menu "System tables"
Myles Watson45bb25f2009-09-22 18:49:08 +0000462
Myles Watson45bb25f2009-09-22 18:49:08 +0000463config MULTIBOOT
Uwe Hermann168b11b2009-10-07 16:15:40 +0000464 bool "Generate Multiboot tables (for GRUB2)"
Ronald G. Minnich7f91d922009-11-09 17:56:47 +0000465 default y
Stefan Reinauera957b7a2013-02-14 13:39:25 -0800466 depends on ARCH_X86
Myles Watson45bb25f2009-09-22 18:49:08 +0000467
Myles Watsonb8e20272009-10-15 13:35:47 +0000468config GENERATE_ACPI_TABLES
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800469 prompt "Generate ACPI tables" if HAVE_ACPI_TABLES
470 bool
471 default HAVE_ACPI_TABLES
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000472 help
473 Generate ACPI tables for this board.
474
475 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000476
Myles Watsonb8e20272009-10-15 13:35:47 +0000477config GENERATE_MP_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800478 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
479 bool
480 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000481 help
482 Generate an MP table (conforming to the Intel MultiProcessor
483 specification 1.4) for this board.
484
485 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000486
Myles Watsonb8e20272009-10-15 13:35:47 +0000487config GENERATE_PIRQ_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800488 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
489 bool
490 default HAVE_PIRQ_TABLE
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000491 help
492 Generate a PIRQ table for this board.
493
494 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000495
Sven Schnelle164bcfd2011-08-14 20:56:34 +0200496config GENERATE_SMBIOS_TABLES
497 depends on ARCH_X86
498 bool "Generate SMBIOS tables"
499 default y
500 help
501 Generate SMBIOS tables for this board.
502
503 If unsure, say Y.
504
Myles Watson45bb25f2009-09-22 18:49:08 +0000505endmenu
506
Patrick Georgi0588d192009-08-12 15:00:51 +0000507menu "Payload"
508
Patrick Georgi0588d192009-08-12 15:00:51 +0000509choice
Uwe Hermann168b11b2009-10-07 16:15:40 +0000510 prompt "Add a payload"
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000511 default PAYLOAD_NONE if !ARCH_X86
512 default PAYLOAD_SEABIOS if ARCH_X86
Patrick Georgi0588d192009-08-12 15:00:51 +0000513
Uwe Hermann168b11b2009-10-07 16:15:40 +0000514config PAYLOAD_NONE
515 bool "None"
516 help
517 Select this option if you want to create an "empty" coreboot
518 ROM image for a certain mainboard, i.e. a coreboot ROM image
519 which does not yet contain a payload.
520
521 For such an image to be useful, you have to use 'cbfstool'
522 to add a payload to the ROM image later.
523
Patrick Georgi0588d192009-08-12 15:00:51 +0000524config PAYLOAD_ELF
Uwe Hermann168b11b2009-10-07 16:15:40 +0000525 bool "An ELF executable payload"
Patrick Georgi0588d192009-08-12 15:00:51 +0000526 help
527 Select this option if you have a payload image (an ELF file)
528 which coreboot should run as soon as the basic hardware
529 initialization is completed.
530
531 You will be able to specify the location and file name of the
532 payload image later.
Patrick Georgi0588d192009-08-12 15:00:51 +0000533
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000534config PAYLOAD_SEABIOS
535 bool "SeaBIOS"
536 depends on ARCH_X86
537 help
538 Select this option if you want to build a coreboot image
539 with a SeaBIOS payload. If you don't know what this is
540 about, just leave it enabled.
541
542 See http://coreboot.org/Payloads for more information.
543
Stefan Reinauere50952f2011-04-15 03:34:05 +0000544config PAYLOAD_FILO
545 bool "FILO"
546 help
547 Select this option if you want to build a coreboot image
548 with a FILO payload. If you don't know what this is
549 about, just leave it enabled.
550
551 See http://coreboot.org/Payloads for more information.
552
Stefan Reinauercc5b3442013-01-15 17:02:58 -0800553config PAYLOAD_TIANOCORE
554 bool "Tiano Core"
555 help
556 Select this option if you want to build a coreboot image
557 with a Tiano Core payload. If you don't know what this is
558 about, just leave it enabled.
559
560 See http://coreboot.org/Payloads for more information.
561
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000562endchoice
563
564choice
565 prompt "SeaBIOS version"
566 default SEABIOS_STABLE
567 depends on PAYLOAD_SEABIOS
568
569config SEABIOS_STABLE
Idwer Vollering1a433092013-03-02 18:27:05 +0100570 bool "1.7.2.1"
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000571 help
572 Stable SeaBIOS version
573config SEABIOS_MASTER
574 bool "master"
575 help
576 Newest SeaBIOS version
Patrick Georgi0588d192009-08-12 15:00:51 +0000577endchoice
578
Stefan Reinauere50952f2011-04-15 03:34:05 +0000579choice
580 prompt "FILO version"
581 default FILO_STABLE
582 depends on PAYLOAD_FILO
583
584config FILO_STABLE
585 bool "0.6.0"
586 help
587 Stable FILO version
588config FILO_MASTER
589 bool "HEAD"
590 help
591 Newest FILO version
592endchoice
593
Stefan Reinauerbccbbe62010-12-19 21:20:14 +0000594config PAYLOAD_FILE
Cristi Magherusanb5034d42009-08-17 14:47:32 +0000595 string "Payload path and filename"
Patrick Georgi0588d192009-08-12 15:00:51 +0000596 depends on PAYLOAD_ELF
597 default "payload.elf"
598 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000599 The path and filename of the ELF executable file to use as payload.
Patrick Georgi0588d192009-08-12 15:00:51 +0000600
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000601config PAYLOAD_FILE
602 depends on PAYLOAD_SEABIOS
Stefan Reinaueraff6dc22012-01-21 10:34:22 -0800603 default "$(obj)/seabios/out/bios.bin.elf"
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000604
Stefan Reinauere50952f2011-04-15 03:34:05 +0000605config PAYLOAD_FILE
606 depends on PAYLOAD_FILO
607 default "payloads/external/FILO/filo/build/filo.elf"
608
Stefan Reinauer275fb632013-02-05 13:58:29 -0800609config PAYLOAD_FILE
610 string "Tianocore firmware volume"
611 depends on PAYLOAD_TIANOCORE
612 default "COREBOOT.fd"
613 help
614 The result of a corebootPkg build
615
Uwe Hermann168b11b2009-10-07 16:15:40 +0000616# TODO: Defined if no payload? Breaks build?
617config COMPRESSED_PAYLOAD_LZMA
618 bool "Use LZMA compression for payloads"
619 default y
Patrick Georgied08bcc2013-02-04 19:15:06 +0100620 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO || PAYLOAD_TIANOCORE
Uwe Hermann168b11b2009-10-07 16:15:40 +0000621 help
622 In order to reduce the size payloads take up in the ROM chip
623 coreboot can compress them using the LZMA algorithm.
624
Myles Watson04000f42009-10-16 19:12:49 +0000625config COMPRESSED_PAYLOAD_NRV2B
Peter Stuged7b37b02009-10-17 03:00:04 +0000626 bool
Myles Watson04000f42009-10-16 19:12:49 +0000627 default n
628
Peter Stugea758ca22009-09-17 16:21:31 +0000629endmenu
630
Uwe Hermann168b11b2009-10-07 16:15:40 +0000631menu "Debugging"
632
633# TODO: Better help text and detailed instructions.
Patrick Georgi0588d192009-08-12 15:00:51 +0000634config GDB_STUB
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000635 bool "GDB debugging support"
Rudolf Marek65888022012-03-25 20:51:16 +0200636 default n
Patrick Georgi0588d192009-08-12 15:00:51 +0000637 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000638 If enabled, you will be able to set breakpoints for gdb debugging.
Stefan Reinauer8677a232010-12-11 20:33:41 +0000639 See src/arch/x86/lib/c_start.S for details.
Patrick Georgi0588d192009-08-12 15:00:51 +0000640
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200641config GDB_WAIT
642 bool "Wait for a GDB connection"
643 default n
644 depends on GDB_STUB
645 help
646 If enabled, coreboot will wait for a GDB connection.
647
Stefan Reinauerfe422182012-05-02 16:33:18 -0700648config DEBUG_CBFS
649 bool "Output verbose CBFS debug messages"
650 default n
Stefan Reinauerfe422182012-05-02 16:33:18 -0700651 help
652 This option enables additional CBFS related debug messages.
653
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000654config HAVE_DEBUG_RAM_SETUP
655 def_bool n
656
Uwe Hermann01ce6012010-03-05 10:03:50 +0000657config DEBUG_RAM_SETUP
658 bool "Output verbose RAM init debug messages"
659 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000660 depends on HAVE_DEBUG_RAM_SETUP
Uwe Hermann01ce6012010-03-05 10:03:50 +0000661 help
662 This option enables additional RAM init related debug messages.
663 It is recommended to enable this when debugging issues on your
664 board which might be RAM init related.
665
666 Note: This option will increase the size of the coreboot image.
667
668 If unsure, say N.
669
Patrick Georgie82618d2010-10-01 14:50:12 +0000670config HAVE_DEBUG_CAR
671 def_bool n
672
Peter Stuge5015f792010-11-10 02:00:32 +0000673config DEBUG_CAR
674 def_bool n
675 depends on HAVE_DEBUG_CAR
676
677if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
Uwe Hermanna953f372010-11-10 00:14:32 +0000678# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
679# printk(BIOS_DEBUG, ...) calls.
Patrick Georgie82618d2010-10-01 14:50:12 +0000680config DEBUG_CAR
681 bool "Output verbose Cache-as-RAM debug messages"
682 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000683 depends on HAVE_DEBUG_CAR
Patrick Georgie82618d2010-10-01 14:50:12 +0000684 help
685 This option enables additional CAR related debug messages.
Peter Stuge5015f792010-11-10 02:00:32 +0000686endif
Patrick Georgie82618d2010-10-01 14:50:12 +0000687
Myles Watson80e914ff2010-06-01 19:25:31 +0000688config DEBUG_PIRQ
689 bool "Check PIRQ table consistency"
690 default n
691 depends on GENERATE_PIRQ_TABLE
692 help
693 If unsure, say N.
694
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000695config HAVE_DEBUG_SMBUS
696 def_bool n
697
Uwe Hermann01ce6012010-03-05 10:03:50 +0000698config DEBUG_SMBUS
699 bool "Output verbose SMBus debug messages"
700 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000701 depends on HAVE_DEBUG_SMBUS
Uwe Hermann01ce6012010-03-05 10:03:50 +0000702 help
703 This option enables additional SMBus (and SPD) debug messages.
704
705 Note: This option will increase the size of the coreboot image.
706
707 If unsure, say N.
708
709config DEBUG_SMI
710 bool "Output verbose SMI debug messages"
711 default n
712 depends on HAVE_SMI_HANDLER
713 help
714 This option enables additional SMI related debug messages.
715
716 Note: This option will increase the size of the coreboot image.
717
718 If unsure, say N.
719
Stefan Reinauerbc0f7a62010-08-01 15:41:14 +0000720config DEBUG_SMM_RELOCATION
721 bool "Debug SMM relocation code"
722 default n
723 depends on HAVE_SMI_HANDLER
724 help
725 This option enables additional SMM handler relocation related
726 debug messages.
727
728 Note: This option will increase the size of the coreboot image.
729
730 If unsure, say N.
731
Uwe Hermanna953f372010-11-10 00:14:32 +0000732# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
733# printk(BIOS_DEBUG, ...) calls.
734config DEBUG_MALLOC
Stefan Reinauer95a63962012-11-13 17:00:01 -0800735 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
736 bool
Uwe Hermanna953f372010-11-10 00:14:32 +0000737 default n
Uwe Hermanna953f372010-11-10 00:14:32 +0000738 help
739 This option enables additional malloc related debug messages.
740
741 Note: This option will increase the size of the coreboot image.
742
743 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300744
745# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
746# printk(BIOS_DEBUG, ...) calls.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300747config DEBUG_ACPI
Stefan Reinauer95a63962012-11-13 17:00:01 -0800748 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
749 bool
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300750 default n
751 help
752 This option enables additional ACPI related debug messages.
753
754 Note: This option will slightly increase the size of the coreboot image.
755
756 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300757
Uwe Hermanna953f372010-11-10 00:14:32 +0000758# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
759# printk(BIOS_DEBUG, ...) calls.
Myles Watson6c9bc012010-09-07 22:30:15 +0000760config REALMODE_DEBUG
Stefan Reinauer95a63962012-11-13 17:00:01 -0800761 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
762 bool
Myles Watson6c9bc012010-09-07 22:30:15 +0000763 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000764 depends on PCI_OPTION_ROM_RUN_REALMODE
Myles Watson6c9bc012010-09-07 22:30:15 +0000765 help
766 This option enables additional x86emu related debug messages.
767
768 Note: This option will increase the time to emulate a ROM.
769
770 If unsure, say N.
771
Uwe Hermann01ce6012010-03-05 10:03:50 +0000772config X86EMU_DEBUG
773 bool "Output verbose x86emu debug messages"
774 default n
775 depends on PCI_OPTION_ROM_RUN_YABEL
776 help
777 This option enables additional x86emu related debug messages.
778
779 Note: This option will increase the size of the coreboot image.
780
781 If unsure, say N.
782
783config X86EMU_DEBUG_JMP
784 bool "Trace JMP/RETF"
785 default n
786 depends on X86EMU_DEBUG
787 help
788 Print information about JMP and RETF opcodes from x86emu.
789
790 Note: This option will increase the size of the coreboot image.
791
792 If unsure, say N.
793
794config X86EMU_DEBUG_TRACE
795 bool "Trace all opcodes"
796 default n
797 depends on X86EMU_DEBUG
798 help
799 Print _all_ opcodes that are executed by x86emu.
Stefan Reinauer14e22772010-04-27 06:56:47 +0000800
Uwe Hermann01ce6012010-03-05 10:03:50 +0000801 WARNING: This will produce a LOT of output and take a long time.
802
803 Note: This option will increase the size of the coreboot image.
804
805 If unsure, say N.
806
807config X86EMU_DEBUG_PNP
808 bool "Log Plug&Play accesses"
809 default n
810 depends on X86EMU_DEBUG
811 help
812 Print Plug And Play accesses made by option ROMs.
813
814 Note: This option will increase the size of the coreboot image.
815
816 If unsure, say N.
817
818config X86EMU_DEBUG_DISK
819 bool "Log Disk I/O"
820 default n
821 depends on X86EMU_DEBUG
822 help
823 Print Disk I/O related messages.
824
825 Note: This option will increase the size of the coreboot image.
826
827 If unsure, say N.
828
829config X86EMU_DEBUG_PMM
830 bool "Log PMM"
831 default n
832 depends on X86EMU_DEBUG
833 help
834 Print messages related to POST Memory Manager (PMM).
835
836 Note: This option will increase the size of the coreboot image.
837
838 If unsure, say N.
839
840
841config X86EMU_DEBUG_VBE
842 bool "Debug VESA BIOS Extensions"
843 default n
844 depends on X86EMU_DEBUG
845 help
846 Print messages related to VESA BIOS Extension (VBE) functions.
847
848 Note: This option will increase the size of the coreboot image.
849
850 If unsure, say N.
851
852config X86EMU_DEBUG_INT10
853 bool "Redirect INT10 output to console"
854 default n
855 depends on X86EMU_DEBUG
856 help
857 Let INT10 (i.e. character output) calls print messages to debug output.
858
859 Note: This option will increase the size of the coreboot image.
860
861 If unsure, say N.
862
863config X86EMU_DEBUG_INTERRUPTS
864 bool "Log intXX calls"
865 default n
866 depends on X86EMU_DEBUG
867 help
868 Print messages related to interrupt handling.
869
870 Note: This option will increase the size of the coreboot image.
871
872 If unsure, say N.
873
874config X86EMU_DEBUG_CHECK_VMEM_ACCESS
875 bool "Log special memory accesses"
876 default n
877 depends on X86EMU_DEBUG
878 help
879 Print messages related to accesses to certain areas of the virtual
880 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
881
882 Note: This option will increase the size of the coreboot image.
883
884 If unsure, say N.
885
886config X86EMU_DEBUG_MEM
887 bool "Log all memory accesses"
888 default n
889 depends on X86EMU_DEBUG
890 help
891 Print memory accesses made by option ROM.
892 Note: This also includes accesses to fetch instructions.
893
894 Note: This option will increase the size of the coreboot image.
895
896 If unsure, say N.
897
898config X86EMU_DEBUG_IO
899 bool "Log IO accesses"
900 default n
901 depends on X86EMU_DEBUG
902 help
903 Print I/O accesses made by option ROM.
904
905 Note: This option will increase the size of the coreboot image.
906
907 If unsure, say N.
908
Stefan Reinauerdfb098d2011-11-17 12:50:54 -0800909config DEBUG_TPM
910 bool "Output verbose TPM debug messages"
911 default n
912 depends on TPM
913 help
914 This option enables additional TPM related debug messages.
915
Stefan Reinauer1c56d9b2012-05-10 11:27:32 -0700916config DEBUG_SPI_FLASH
917 bool "Output verbose SPI flash debug messages"
918 default n
919 depends on SPI_FLASH
920 help
921 This option enables additional SPI flash related debug messages.
922
Stefan Reinauer8e073822012-04-04 00:07:22 +0200923if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
924# Only visible with the right southbridge and loglevel.
925config DEBUG_INTEL_ME
926 bool "Verbose logging for Intel Management Engine"
927 default n
928 help
929 Enable verbose logging for Intel Management Engine driver that
930 is present on Intel 6-series chipsets.
931endif
932
Stefan Reinauer5c503922010-03-13 22:07:15 +0000933config LLSHELL
934 bool "Built-in low-level shell"
935 default n
936 help
937 If enabled, you will have a low level shell to examine your machine.
938 Put llshell() in your (romstage) code to start the shell.
Stefan Reinauer8677a232010-12-11 20:33:41 +0000939 See src/arch/x86/llshell/llshell.inc for details.
Stefan Reinauer5c503922010-03-13 22:07:15 +0000940
Rudolf Marek7f0e9302011-09-02 23:23:41 +0200941config TRACE
942 bool "Trace function calls"
943 default n
944 help
945 If enabled, every function will print information to console once
946 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
947 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
948 of calling function. Please note some printk releated functions
949 are omitted from trace to have good looking console dumps.
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800950
951config DEBUG_COVERAGE
952 bool "Debug code coverage"
953 default n
954 depends on COVERAGE
955 help
956 If enabled, the code coverage hooks in coreboot will output some
957 information about the coverage data that is dumped.
958
Uwe Hermann168b11b2009-10-07 16:15:40 +0000959endmenu
960
Myles Watsond73c1b52009-10-26 15:14:07 +0000961# These probably belong somewhere else, but they are needed somewhere.
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000962config RAMINIT_SYSINFO
963 bool
964 default n
965
Myles Watsond73c1b52009-10-26 15:14:07 +0000966config ENABLE_APIC_EXT_ID
967 bool
968 default n
Myles Watson2e672732009-11-12 16:38:03 +0000969
970config WARNINGS_ARE_ERRORS
971 bool
Stefan Reinauer6f57b512010-07-08 16:41:05 +0000972 default y
Patrick Georgi436f99b2009-11-27 16:55:13 +0000973
Peter Stuge51eafde2010-10-13 06:23:02 +0000974# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
975# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
976# mutually exclusive. One of these options must be selected in the
977# mainboard Kconfig if the chipset supports enabling and disabling of
978# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
979# in mainboard/Kconfig to know if the button should be enabled or not.
980
981config POWER_BUTTON_DEFAULT_ENABLE
982 def_bool n
983 help
984 Select when the board has a power button which can optionally be
985 disabled by the user.
986
987config POWER_BUTTON_DEFAULT_DISABLE
988 def_bool n
989 help
990 Select when the board has a power button which can optionally be
991 enabled by the user, e.g. when the board ships with a jumper over
992 the power switch contacts.
993
994config POWER_BUTTON_FORCE_ENABLE
995 def_bool n
996 help
997 Select when the board requires that the power button is always
998 enabled.
999
1000config POWER_BUTTON_FORCE_DISABLE
1001 def_bool n
1002 help
1003 Select when the board requires that the power button is always
1004 disabled, e.g. when it has been hardwired to ground.
1005
1006config POWER_BUTTON_IS_OPTIONAL
1007 bool
1008 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1009 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1010 help
1011 Internal option that controls ENABLE_POWER_BUTTON visibility.
1012
Stefan Reinauerb89a7612012-03-30 01:01:51 +02001013source src/vendorcode/Kconfig