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Patrick Georgi0588d192009-08-12 15:00:51 +00001##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00002## This file is part of the coreboot project.
Patrick Georgi0588d192009-08-12 15:00:51 +00003##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00004## Copyright (C) 2009-2010 coresystems GmbH
Patrick Georgi0588d192009-08-12 15:00:51 +00005##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00006## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
17## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Patrick Georgi0588d192009-08-12 15:00:51 +000018##
19
20mainmenu "Coreboot Configuration"
21
Uwe Hermannc04be932009-10-05 13:55:28 +000022menu "General setup"
23
Uwe Hermanna29ad5c2009-10-18 18:35:50 +000024config EXPERT
25 bool "Expert mode"
26 help
27 This allows you to select certain advanced configuration options.
28
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
31
Uwe Hermannc04be932009-10-05 13:55:28 +000032config LOCALVERSION
Uwe Hermann168b11b2009-10-07 16:15:40 +000033 string "Local version string"
Uwe Hermannc04be932009-10-05 13:55:28 +000034 help
35 Append an extra string to the end of the coreboot version.
36
Uwe Hermann168b11b2009-10-07 16:15:40 +000037 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
41
Patrick Georgi4b8a2412010-02-09 19:35:16 +000042config CBFS_PREFIX
43 string "CBFS prefix to use"
44 default "fallback"
45 help
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
48
Patrick Georgi23d89cc2010-03-16 01:17:19 +000049choice
50 prompt "Compiler"
51 default COMPILER_GCC
52 help
53 This option allows you to select the compiler used for building
54 coreboot.
55
56config COMPILER_GCC
57 bool "GCC"
58config COMPILER_LLVM_CLANG
59 bool "LLVM/clang"
60endchoice
61
Patrick Georgi020f51f2010-03-14 21:25:03 +000062config SCANBUILD_ENABLE
Patrick Georgi23d89cc2010-03-16 01:17:19 +000063 bool "Build with scan-build for static analysis"
Patrick Georgi020f51f2010-03-14 21:25:03 +000064 default n
65 help
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
68
69config SCANBUILD_REPORT_LOCATION
Patrick Georgi23d89cc2010-03-16 01:17:19 +000070 string "Directory to put scan-build report in"
Patrick Georgi020f51f2010-03-14 21:25:03 +000071 default ""
72 depends on SCANBUILD_ENABLE
73 help
74 Where the scan-build report should be stored
75
Patrick Georgi516a2a72010-03-25 21:45:25 +000076config CCACHE
77 bool "ccache"
78 default n
79 help
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
82
Stefan Reinauer9bf78102010-08-09 13:28:18 +000083config SCONFIG_GENPARSER
84 bool "Generate SCONFIG parser using flex and bison"
85 default n
86 depends on EXPERT
87 help
88 Enable this option if you are working on the sconfig
89 device tree parser and made changes to sconfig.l and
Sven Schnelle164bcfd2011-08-14 20:56:34 +020090 sconfig.y.
Stefan Reinauer9bf78102010-08-09 13:28:18 +000091 Otherwise, say N.
92
Joe Korty6d772522010-05-19 18:41:15 +000093config USE_OPTION_TABLE
94 bool "Use CMOS for configuration values"
95 default n
Edwin Beasanteb50c7d2010-07-06 21:05:04 +000096 depends on HAVE_OPTION_TABLE
Joe Korty6d772522010-05-19 18:41:15 +000097 help
98 Enable this option if coreboot shall read options from the "CMOS"
99 NVRAM instead of using hard coded values.
100
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000101config COMPRESS_RAMSTAGE
102 bool "Compress ramstage with LZMA"
103 default y
104 help
105 Compress ramstage to save memory in the flash image. Note
106 that decompression might slow down booting if the boot flash
107 is connected through a slow Link (i.e. SPI)
108
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200109config INCLUDE_CONFIG_FILE
110 bool "Include the coreboot config file into the ROM image"
111 default y
112 help
113 Include in CBFS the coreboot config file that was used to compile the ROM image
114
Vadim Bendeburye6b6aff2011-09-20 16:46:46 -0700115config EARLY_CBMEM_INIT
116 bool "Initialize CBMEM while in ROM stage"
117 default n
118 help
119 Make coreboot initialize the cbmem structures while running in rom
120 stage. This could be useful when the rom stage wants to communicate
121 some, for instance, execution timestamps.
122
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700123config COLLECT_TIMESTAMPS
124 bool "Create a table of timestamps collected during boot"
125 depends on EARLY_CBMEM_INIT
126 help
127 Make coreboot create a table of timer id/timer value pairs to
128 allow measuring time spent at different phases of the boot
129 process.
Uwe Hermannc04be932009-10-05 13:55:28 +0000130endmenu
131
Patrick Georgi0588d192009-08-12 15:00:51 +0000132source src/mainboard/Kconfig
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000133
134# This option is used to set the architecture of a mainboard to X86.
135# It is usually set in mainboard/*/Kconfig.
136config ARCH_X86
137 bool
138 default n
139
140if ARCH_X86
Stefan Reinauer8677a232010-12-11 20:33:41 +0000141source src/arch/x86/Kconfig
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000142endif
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000143
144menu "Chipset"
145
146comment "CPU"
Patrick Georgi0588d192009-08-12 15:00:51 +0000147source src/cpu/Kconfig
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000148comment "Northbridge"
149source src/northbridge/Kconfig
150comment "Southbridge"
151source src/southbridge/Kconfig
152comment "Super I/O"
153source src/superio/Kconfig
154comment "Devices"
155source src/devices/Kconfig
Sven Schnelle7592e8b2011-01-27 11:43:03 +0000156comment "Embedded Controllers"
157source src/ec/Kconfig
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000158
159endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000160
Rudolf Marekd9c25492010-05-16 15:31:53 +0000161menu "Generic Drivers"
162source src/drivers/Kconfig
163endmenu
164
Patrick Georgi0588d192009-08-12 15:00:51 +0000165config PCI_BUS_SEGN_BITS
Myles Watson74fb8f22009-09-24 15:09:11 +0000166 int
167 default 0
Patrick Georgi892b0912009-09-24 09:03:06 +0000168
Patrick Georgi0588d192009-08-12 15:00:51 +0000169config PCI_ROM_RUN
Patrick Georgi698c0e0e2009-08-25 17:38:24 +0000170 bool
171 default n
Patrick Georgi0588d192009-08-12 15:00:51 +0000172
Patrick Georgi0588d192009-08-12 15:00:51 +0000173config HEAP_SIZE
174 hex
Myles Watson04000f42009-10-16 19:12:49 +0000175 default 0x4000
Patrick Georgi0588d192009-08-12 15:00:51 +0000176
Patrick Georgi0588d192009-08-12 15:00:51 +0000177config MAX_CPUS
178 int
179 default 1
180
181config MMCONF_SUPPORT_DEFAULT
182 bool
183 default n
184
185config MMCONF_SUPPORT
186 bool
187 default n
188
Patrick Georgi0588d192009-08-12 15:00:51 +0000189source src/console/Kconfig
190
Stefan Reinauer4885daa2011-04-26 23:47:04 +0000191# This should default to N and be set by SuperI/O drivers that have an UART
192config HAVE_UART_IO_MAPPED
193 bool
194 default y
195
196config HAVE_UART_MEMORY_MAPPED
197 bool
198 default n
199
Patrick Georgi0588d192009-08-12 15:00:51 +0000200config HAVE_ACPI_RESUME
201 bool
202 default n
203
Stefan Reinauerc4f1a772010-06-05 10:03:08 +0000204config HAVE_ACPI_SLIC
205 bool
206 default n
207
Patrick Georgi0588d192009-08-12 15:00:51 +0000208config ACPI_SSDTX_NUM
209 int
210 default 0
211
Patrick Georgi0588d192009-08-12 15:00:51 +0000212config HAVE_HARD_RESET
213 bool
Patrick Georgi37bdb872010-02-27 08:39:04 +0000214 default y if BOARD_HAS_HARD_RESET
Uwe Hermann748475b2009-10-09 11:47:21 +0000215 default n
Patrick Georgi37bdb872010-02-27 08:39:04 +0000216 help
217 This variable specifies whether a given board has a hard_reset
218 function, no matter if it's provided by board code or chipset code.
219
Patrick Georgi0588d192009-08-12 15:00:51 +0000220config HAVE_INIT_TIMER
221 bool
Patrick Georgi1f807fd2010-01-04 20:09:27 +0000222 default n if UDELAY_IO
Myles Watsond73c1b52009-10-26 15:14:07 +0000223 default y
Patrick Georgi0588d192009-08-12 15:00:51 +0000224
225config HAVE_MAINBOARD_RESOURCES
226 bool
227 default n
228
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000229config USE_OPTION_TABLE
230 bool
231 default n
232
Patrick Georgi0588d192009-08-12 15:00:51 +0000233config HAVE_OPTION_TABLE
234 bool
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000235 default n
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000236 help
237 This variable specifies whether a given board has a cmos.layout
238 file containing NVRAM/CMOS bit definitions.
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000239 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
Patrick Georgi0588d192009-08-12 15:00:51 +0000240
Patrick Georgi0588d192009-08-12 15:00:51 +0000241config PIRQ_ROUTE
242 bool
243 default n
244
245config HAVE_SMI_HANDLER
246 bool
247 default n
248
249config PCI_IO_CFG_EXT
250 bool
251 default n
252
253config IOAPIC
254 bool
255 default n
256
Stefan Reinauer3008bbad2011-10-11 14:46:25 -0700257config TPM
258 bool
259 default n
260
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000261# TODO: Can probably be removed once all chipsets have kconfig options for it.
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000262config VIDEO_MB
263 int
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000264 default 0
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000265
Myles Watson45bb25f2009-09-22 18:49:08 +0000266config USE_WATCHDOG_ON_BOOT
267 bool
268 default n
269
270config VGA
271 bool
272 default n
273 help
274 Build board-specific VGA code.
275
276config GFXUMA
277 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000278 default n
Myles Watson45bb25f2009-09-22 18:49:08 +0000279 help
280 Enable Unified Memory Architecture for graphics.
281
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000282# TODO
283# menu "Drivers"
Uwe Hermann168b11b2009-10-07 16:15:40 +0000284#
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000285# endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000286
Myles Watsonb8e20272009-10-15 13:35:47 +0000287config HAVE_ACPI_TABLES
288 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000289 help
290 This variable specifies whether a given board has ACPI table support.
291 It is usually set in mainboard/*/Kconfig.
292 Whether or not the ACPI tables are actually generated by coreboot
293 is configurable by the user via GENERATE_ACPI_TABLES.
Myles Watsonb8e20272009-10-15 13:35:47 +0000294
295config HAVE_MP_TABLE
296 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000297 help
298 This variable specifies whether a given board has MP table support.
299 It is usually set in mainboard/*/Kconfig.
300 Whether or not the MP table is actually generated by coreboot
301 is configurable by the user via GENERATE_MP_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000302
303config HAVE_PIRQ_TABLE
304 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000305 help
306 This variable specifies whether a given board has PIRQ table support.
307 It is usually set in mainboard/*/Kconfig.
308 Whether or not the PIRQ table is actually generated by coreboot
309 is configurable by the user via GENERATE_PIRQ_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000310
Myles Watsond73c1b52009-10-26 15:14:07 +0000311#These Options are here to avoid "undefined" warnings.
312#The actual selection and help texts are in the following menu.
313
314config GENERATE_ACPI_TABLES
Myles Watsonb8e20272009-10-15 13:35:47 +0000315 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000316 default HAVE_ACPI_TABLES
317
318config GENERATE_MP_TABLE
319 bool
320 default HAVE_MP_TABLE
321
322config GENERATE_PIRQ_TABLE
323 bool
324 default HAVE_PIRQ_TABLE
325
Sven Schnelle164bcfd2011-08-14 20:56:34 +0200326config GENERATE_SMBIOS_TABLES
327 bool
328 default y
329
Uwe Hermann168b11b2009-10-07 16:15:40 +0000330menu "System tables"
Myles Watson45bb25f2009-09-22 18:49:08 +0000331
Myles Watsonb8e20272009-10-15 13:35:47 +0000332config WRITE_HIGH_TABLES
Myles Watson45bb25f2009-09-22 18:49:08 +0000333 bool "Write 'high' tables to avoid being overwritten in F segment"
334 default y
335
336config MULTIBOOT
Uwe Hermann168b11b2009-10-07 16:15:40 +0000337 bool "Generate Multiboot tables (for GRUB2)"
Ronald G. Minnich7f91d922009-11-09 17:56:47 +0000338 default y
Myles Watson45bb25f2009-09-22 18:49:08 +0000339
Myles Watsonb8e20272009-10-15 13:35:47 +0000340config GENERATE_ACPI_TABLES
341 depends on HAVE_ACPI_TABLES
Myles Watson45bb25f2009-09-22 18:49:08 +0000342 bool "Generate ACPI tables"
Myles Watsonb8e20272009-10-15 13:35:47 +0000343 default y
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000344 help
345 Generate ACPI tables for this board.
346
347 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000348
Myles Watsonb8e20272009-10-15 13:35:47 +0000349config GENERATE_MP_TABLE
350 depends on HAVE_MP_TABLE
Myles Watson45bb25f2009-09-22 18:49:08 +0000351 bool "Generate an MP table"
Myles Watsonb8e20272009-10-15 13:35:47 +0000352 default y
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000353 help
354 Generate an MP table (conforming to the Intel MultiProcessor
355 specification 1.4) for this board.
356
357 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000358
Myles Watsonb8e20272009-10-15 13:35:47 +0000359config GENERATE_PIRQ_TABLE
360 depends on HAVE_PIRQ_TABLE
Myles Watson45bb25f2009-09-22 18:49:08 +0000361 bool "Generate a PIRQ table"
Myles Watsonb8e20272009-10-15 13:35:47 +0000362 default y
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000363 help
364 Generate a PIRQ table for this board.
365
366 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000367
Sven Schnelle164bcfd2011-08-14 20:56:34 +0200368config GENERATE_SMBIOS_TABLES
369 depends on ARCH_X86
370 bool "Generate SMBIOS tables"
371 default y
372 help
373 Generate SMBIOS tables for this board.
374
375 If unsure, say Y.
376
Myles Watson45bb25f2009-09-22 18:49:08 +0000377endmenu
378
Patrick Georgi0588d192009-08-12 15:00:51 +0000379menu "Payload"
380
Patrick Georgi0588d192009-08-12 15:00:51 +0000381choice
Uwe Hermann168b11b2009-10-07 16:15:40 +0000382 prompt "Add a payload"
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000383 default PAYLOAD_NONE if !ARCH_X86
384 default PAYLOAD_SEABIOS if ARCH_X86
Patrick Georgi0588d192009-08-12 15:00:51 +0000385
Uwe Hermann168b11b2009-10-07 16:15:40 +0000386config PAYLOAD_NONE
387 bool "None"
388 help
389 Select this option if you want to create an "empty" coreboot
390 ROM image for a certain mainboard, i.e. a coreboot ROM image
391 which does not yet contain a payload.
392
393 For such an image to be useful, you have to use 'cbfstool'
394 to add a payload to the ROM image later.
395
Patrick Georgi0588d192009-08-12 15:00:51 +0000396config PAYLOAD_ELF
Uwe Hermann168b11b2009-10-07 16:15:40 +0000397 bool "An ELF executable payload"
Patrick Georgi0588d192009-08-12 15:00:51 +0000398 help
399 Select this option if you have a payload image (an ELF file)
400 which coreboot should run as soon as the basic hardware
401 initialization is completed.
402
403 You will be able to specify the location and file name of the
404 payload image later.
Patrick Georgi0588d192009-08-12 15:00:51 +0000405
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000406config PAYLOAD_SEABIOS
407 bool "SeaBIOS"
408 depends on ARCH_X86
409 help
410 Select this option if you want to build a coreboot image
411 with a SeaBIOS payload. If you don't know what this is
412 about, just leave it enabled.
413
414 See http://coreboot.org/Payloads for more information.
415
Stefan Reinauere50952f2011-04-15 03:34:05 +0000416config PAYLOAD_FILO
417 bool "FILO"
418 help
419 Select this option if you want to build a coreboot image
420 with a FILO payload. If you don't know what this is
421 about, just leave it enabled.
422
423 See http://coreboot.org/Payloads for more information.
424
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000425endchoice
426
427choice
428 prompt "SeaBIOS version"
429 default SEABIOS_STABLE
430 depends on PAYLOAD_SEABIOS
431
432config SEABIOS_STABLE
433 bool "stable"
434 help
435 Stable SeaBIOS version
436config SEABIOS_MASTER
437 bool "master"
438 help
439 Newest SeaBIOS version
Patrick Georgi0588d192009-08-12 15:00:51 +0000440endchoice
441
Stefan Reinauere50952f2011-04-15 03:34:05 +0000442choice
443 prompt "FILO version"
444 default FILO_STABLE
445 depends on PAYLOAD_FILO
446
447config FILO_STABLE
448 bool "0.6.0"
449 help
450 Stable FILO version
451config FILO_MASTER
452 bool "HEAD"
453 help
454 Newest FILO version
455endchoice
456
Stefan Reinauerbccbbe62010-12-19 21:20:14 +0000457config PAYLOAD_FILE
Cristi Magherusanb5034d42009-08-17 14:47:32 +0000458 string "Payload path and filename"
Patrick Georgi0588d192009-08-12 15:00:51 +0000459 depends on PAYLOAD_ELF
460 default "payload.elf"
461 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000462 The path and filename of the ELF executable file to use as payload.
Patrick Georgi0588d192009-08-12 15:00:51 +0000463
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000464config PAYLOAD_FILE
465 depends on PAYLOAD_SEABIOS
Stefan Reinaueraff6dc22012-01-21 10:34:22 -0800466 default "$(obj)/seabios/out/bios.bin.elf"
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000467
Stefan Reinauere50952f2011-04-15 03:34:05 +0000468config PAYLOAD_FILE
469 depends on PAYLOAD_FILO
470 default "payloads/external/FILO/filo/build/filo.elf"
471
Uwe Hermann168b11b2009-10-07 16:15:40 +0000472# TODO: Defined if no payload? Breaks build?
473config COMPRESSED_PAYLOAD_LZMA
474 bool "Use LZMA compression for payloads"
475 default y
Stefan Reinauere50952f2011-04-15 03:34:05 +0000476 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO
Uwe Hermann168b11b2009-10-07 16:15:40 +0000477 help
478 In order to reduce the size payloads take up in the ROM chip
479 coreboot can compress them using the LZMA algorithm.
480
Myles Watson04000f42009-10-16 19:12:49 +0000481config COMPRESSED_PAYLOAD_NRV2B
Peter Stuged7b37b02009-10-17 03:00:04 +0000482 bool
Myles Watson04000f42009-10-16 19:12:49 +0000483 default n
484
Peter Stugea758ca22009-09-17 16:21:31 +0000485endmenu
486
487menu "VGA BIOS"
488
489config VGA_BIOS
490 bool "Add a VGA BIOS image"
491 help
492 Select this option if you have a VGA BIOS image that you would
493 like to add to your ROM.
494
495 You will be able to specify the location and file name of the
496 image later.
497
Stefan Reinauerbccbbe62010-12-19 21:20:14 +0000498config VGA_BIOS_FILE
Cristi Magherusan488c36c2009-08-17 14:46:13 +0000499 string "VGA BIOS path and filename"
500 depends on VGA_BIOS
501 default "vgabios.bin"
502 help
503 The path and filename of the file to use as VGA BIOS.
504
Stefan Reinauerbccbbe62010-12-19 21:20:14 +0000505config VGA_BIOS_ID
Uwe Hermann81b3c0a2009-10-30 12:56:59 +0000506 string "VGA device PCI IDs"
Cristi Magherusan488c36c2009-08-17 14:46:13 +0000507 depends on VGA_BIOS
508 default "1106,3230"
509 help
Uwe Hermann168b11b2009-10-07 16:15:40 +0000510 The comma-separated PCI vendor and device ID that would associate
511 your VGA BIOS to your video card.
512
513 Example: 1106,3230
514
515 In the above example 1106 is the PCI vendor ID (in hex, but without
516 the "0x" prefix) and 3230 specifies the PCI device ID of the
517 video card (also in hex, without "0x" prefix).
Cristi Magherusan488c36c2009-08-17 14:46:13 +0000518
Stefan Reinauer800379f2010-03-01 08:34:19 +0000519config INTEL_MBI
520 bool "Add an MBI image"
521 depends on NORTHBRIDGE_INTEL_I82830
522 help
523 Select this option if you have an Intel MBI image that you would
524 like to add to your ROM.
525
526 You will be able to specify the location and file name of the
527 image later.
528
Stefan Reinauerbccbbe62010-12-19 21:20:14 +0000529config MBI_FILE
Stefan Reinauer800379f2010-03-01 08:34:19 +0000530 string "Intel MBI path and filename"
531 depends on INTEL_MBI
532 default "mbi.bin"
533 help
534 The path and filename of the file to use as VGA BIOS.
535
536endmenu
537
Stefan Reinauerc1efb902011-10-12 14:30:59 -0700538menu "Display"
539 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
540
541config FRAMEBUFFER_SET_VESA_MODE
542 prompt "Set VESA framebuffer mode"
543 bool
544 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
545 help
546 Set VESA framebuffer mode (needed for bootsplash)
547
548# TODO: Turn this into a "choice".
549config FRAMEBUFFER_VESA_MODE
550 prompt "VESA framebuffer video mode"
551 hex
552 default 0x117
553 depends on FRAMEBUFFER_SET_VESA_MODE
554 help
555 This option sets the resolution used for the coreboot framebuffer (and
556 bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will
557 some day make this a "choice".
558
559config FRAMEBUFFER_KEEP_VESA_MODE
560 prompt "Keep VESA framebuffer"
561 bool
562 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
563 help
564 This option keeps the framebuffer mode set after coreboot finishes
565 execution. If this option is enabled, coreboot will pass a
566 framebuffer entry in its coreboot table and the payload will need a
567 framebuffer driver. If this option is disabled, coreboot will switch
568 back to text mode before handing control to a payload.
Stefan Reinauer800379f2010-03-01 08:34:19 +0000569
570config BOOTSPLASH
571 prompt "Show graphical bootsplash"
572 bool
Stefan Reinauerc1efb902011-10-12 14:30:59 -0700573 depends on FRAMEBUFFER_SET_VESA_MODE
Stefan Reinauer800379f2010-03-01 08:34:19 +0000574 help
575 This option shows a graphical bootsplash screen. The grapics are
576 loaded from the CBFS file bootsplash.jpg.
577
Stefan Reinauerbccbbe62010-12-19 21:20:14 +0000578config BOOTSPLASH_FILE
Stefan Reinauer800379f2010-03-01 08:34:19 +0000579 string "Bootsplash path and filename"
580 depends on BOOTSPLASH
581 default "bootsplash.jpg"
582 help
Stefan Reinauer14e22772010-04-27 06:56:47 +0000583 The path and filename of the file to use as graphical bootsplash
584 screen. The file format has to be jpg.
Patrick Georgi0588d192009-08-12 15:00:51 +0000585endmenu
586
Uwe Hermann168b11b2009-10-07 16:15:40 +0000587menu "Debugging"
588
589# TODO: Better help text and detailed instructions.
Patrick Georgi0588d192009-08-12 15:00:51 +0000590config GDB_STUB
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000591 bool "GDB debugging support"
Rudolf Marek65888022012-03-25 20:51:16 +0200592 default n
Patrick Georgi0588d192009-08-12 15:00:51 +0000593 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000594 If enabled, you will be able to set breakpoints for gdb debugging.
Stefan Reinauer8677a232010-12-11 20:33:41 +0000595 See src/arch/x86/lib/c_start.S for details.
Patrick Georgi0588d192009-08-12 15:00:51 +0000596
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000597config HAVE_DEBUG_RAM_SETUP
598 def_bool n
599
Uwe Hermann01ce6012010-03-05 10:03:50 +0000600config DEBUG_RAM_SETUP
601 bool "Output verbose RAM init debug messages"
602 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000603 depends on HAVE_DEBUG_RAM_SETUP
Uwe Hermann01ce6012010-03-05 10:03:50 +0000604 help
605 This option enables additional RAM init related debug messages.
606 It is recommended to enable this when debugging issues on your
607 board which might be RAM init related.
608
609 Note: This option will increase the size of the coreboot image.
610
611 If unsure, say N.
612
Patrick Georgie82618d2010-10-01 14:50:12 +0000613config HAVE_DEBUG_CAR
614 def_bool n
615
Peter Stuge5015f792010-11-10 02:00:32 +0000616config DEBUG_CAR
617 def_bool n
618 depends on HAVE_DEBUG_CAR
619
620if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
Uwe Hermanna953f372010-11-10 00:14:32 +0000621# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
622# printk(BIOS_DEBUG, ...) calls.
Patrick Georgie82618d2010-10-01 14:50:12 +0000623config DEBUG_CAR
624 bool "Output verbose Cache-as-RAM debug messages"
625 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000626 depends on HAVE_DEBUG_CAR
Patrick Georgie82618d2010-10-01 14:50:12 +0000627 help
628 This option enables additional CAR related debug messages.
Peter Stuge5015f792010-11-10 02:00:32 +0000629endif
Patrick Georgie82618d2010-10-01 14:50:12 +0000630
Myles Watson80e914ff2010-06-01 19:25:31 +0000631config DEBUG_PIRQ
632 bool "Check PIRQ table consistency"
633 default n
634 depends on GENERATE_PIRQ_TABLE
635 help
636 If unsure, say N.
637
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000638config HAVE_DEBUG_SMBUS
639 def_bool n
640
Uwe Hermann01ce6012010-03-05 10:03:50 +0000641config DEBUG_SMBUS
642 bool "Output verbose SMBus debug messages"
643 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000644 depends on HAVE_DEBUG_SMBUS
Uwe Hermann01ce6012010-03-05 10:03:50 +0000645 help
646 This option enables additional SMBus (and SPD) debug messages.
647
648 Note: This option will increase the size of the coreboot image.
649
650 If unsure, say N.
651
652config DEBUG_SMI
653 bool "Output verbose SMI debug messages"
654 default n
655 depends on HAVE_SMI_HANDLER
656 help
657 This option enables additional SMI related debug messages.
658
659 Note: This option will increase the size of the coreboot image.
660
661 If unsure, say N.
662
Stefan Reinauerbc0f7a62010-08-01 15:41:14 +0000663config DEBUG_SMM_RELOCATION
664 bool "Debug SMM relocation code"
665 default n
666 depends on HAVE_SMI_HANDLER
667 help
668 This option enables additional SMM handler relocation related
669 debug messages.
670
671 Note: This option will increase the size of the coreboot image.
672
673 If unsure, say N.
674
Peter Stuge5015f792010-11-10 02:00:32 +0000675config DEBUG_MALLOC
676 def_bool n
677
Uwe Hermanna953f372010-11-10 00:14:32 +0000678# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
679# printk(BIOS_DEBUG, ...) calls.
Peter Stuge5015f792010-11-10 02:00:32 +0000680if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
Uwe Hermanna953f372010-11-10 00:14:32 +0000681config DEBUG_MALLOC
682 bool "Output verbose malloc debug messages"
683 default n
Uwe Hermanna953f372010-11-10 00:14:32 +0000684 help
685 This option enables additional malloc related debug messages.
686
687 Note: This option will increase the size of the coreboot image.
688
689 If unsure, say N.
Peter Stuge5015f792010-11-10 02:00:32 +0000690endif
Uwe Hermanna953f372010-11-10 00:14:32 +0000691
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300692config DEBUG_ACPI
693 def_bool n
694
695# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
696# printk(BIOS_DEBUG, ...) calls.
697if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
698config DEBUG_ACPI
699 bool "Output verbose ACPI debug messages"
700 default n
701 help
702 This option enables additional ACPI related debug messages.
703
704 Note: This option will slightly increase the size of the coreboot image.
705
706 If unsure, say N.
707endif
708
Peter Stuge5015f792010-11-10 02:00:32 +0000709config REALMODE_DEBUG
710 def_bool n
711 depends on PCI_OPTION_ROM_RUN_REALMODE
712
713if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
Uwe Hermanna953f372010-11-10 00:14:32 +0000714# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
715# printk(BIOS_DEBUG, ...) calls.
Myles Watson6c9bc012010-09-07 22:30:15 +0000716config REALMODE_DEBUG
717 bool "Enable debug messages for option ROM execution"
718 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000719 depends on PCI_OPTION_ROM_RUN_REALMODE
Myles Watson6c9bc012010-09-07 22:30:15 +0000720 help
721 This option enables additional x86emu related debug messages.
722
723 Note: This option will increase the time to emulate a ROM.
724
725 If unsure, say N.
Peter Stuge5015f792010-11-10 02:00:32 +0000726endif
Myles Watson6c9bc012010-09-07 22:30:15 +0000727
Uwe Hermann01ce6012010-03-05 10:03:50 +0000728config X86EMU_DEBUG
729 bool "Output verbose x86emu debug messages"
730 default n
731 depends on PCI_OPTION_ROM_RUN_YABEL
732 help
733 This option enables additional x86emu related debug messages.
734
735 Note: This option will increase the size of the coreboot image.
736
737 If unsure, say N.
738
739config X86EMU_DEBUG_JMP
740 bool "Trace JMP/RETF"
741 default n
742 depends on X86EMU_DEBUG
743 help
744 Print information about JMP and RETF opcodes from x86emu.
745
746 Note: This option will increase the size of the coreboot image.
747
748 If unsure, say N.
749
750config X86EMU_DEBUG_TRACE
751 bool "Trace all opcodes"
752 default n
753 depends on X86EMU_DEBUG
754 help
755 Print _all_ opcodes that are executed by x86emu.
Stefan Reinauer14e22772010-04-27 06:56:47 +0000756
Uwe Hermann01ce6012010-03-05 10:03:50 +0000757 WARNING: This will produce a LOT of output and take a long time.
758
759 Note: This option will increase the size of the coreboot image.
760
761 If unsure, say N.
762
763config X86EMU_DEBUG_PNP
764 bool "Log Plug&Play accesses"
765 default n
766 depends on X86EMU_DEBUG
767 help
768 Print Plug And Play accesses made by option ROMs.
769
770 Note: This option will increase the size of the coreboot image.
771
772 If unsure, say N.
773
774config X86EMU_DEBUG_DISK
775 bool "Log Disk I/O"
776 default n
777 depends on X86EMU_DEBUG
778 help
779 Print Disk I/O related messages.
780
781 Note: This option will increase the size of the coreboot image.
782
783 If unsure, say N.
784
785config X86EMU_DEBUG_PMM
786 bool "Log PMM"
787 default n
788 depends on X86EMU_DEBUG
789 help
790 Print messages related to POST Memory Manager (PMM).
791
792 Note: This option will increase the size of the coreboot image.
793
794 If unsure, say N.
795
796
797config X86EMU_DEBUG_VBE
798 bool "Debug VESA BIOS Extensions"
799 default n
800 depends on X86EMU_DEBUG
801 help
802 Print messages related to VESA BIOS Extension (VBE) functions.
803
804 Note: This option will increase the size of the coreboot image.
805
806 If unsure, say N.
807
808config X86EMU_DEBUG_INT10
809 bool "Redirect INT10 output to console"
810 default n
811 depends on X86EMU_DEBUG
812 help
813 Let INT10 (i.e. character output) calls print messages to debug output.
814
815 Note: This option will increase the size of the coreboot image.
816
817 If unsure, say N.
818
819config X86EMU_DEBUG_INTERRUPTS
820 bool "Log intXX calls"
821 default n
822 depends on X86EMU_DEBUG
823 help
824 Print messages related to interrupt handling.
825
826 Note: This option will increase the size of the coreboot image.
827
828 If unsure, say N.
829
830config X86EMU_DEBUG_CHECK_VMEM_ACCESS
831 bool "Log special memory accesses"
832 default n
833 depends on X86EMU_DEBUG
834 help
835 Print messages related to accesses to certain areas of the virtual
836 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
837
838 Note: This option will increase the size of the coreboot image.
839
840 If unsure, say N.
841
842config X86EMU_DEBUG_MEM
843 bool "Log all memory accesses"
844 default n
845 depends on X86EMU_DEBUG
846 help
847 Print memory accesses made by option ROM.
848 Note: This also includes accesses to fetch instructions.
849
850 Note: This option will increase the size of the coreboot image.
851
852 If unsure, say N.
853
854config X86EMU_DEBUG_IO
855 bool "Log IO accesses"
856 default n
857 depends on X86EMU_DEBUG
858 help
859 Print I/O accesses made by option ROM.
860
861 Note: This option will increase the size of the coreboot image.
862
863 If unsure, say N.
864
Stefan Reinauerdfb098d2011-11-17 12:50:54 -0800865config DEBUG_TPM
866 bool "Output verbose TPM debug messages"
867 default n
868 depends on TPM
869 help
870 This option enables additional TPM related debug messages.
871
Stefan Reinauer8e073822012-04-04 00:07:22 +0200872if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
873# Only visible with the right southbridge and loglevel.
874config DEBUG_INTEL_ME
875 bool "Verbose logging for Intel Management Engine"
876 default n
877 help
878 Enable verbose logging for Intel Management Engine driver that
879 is present on Intel 6-series chipsets.
880endif
881
Stefan Reinauer5c503922010-03-13 22:07:15 +0000882config LLSHELL
883 bool "Built-in low-level shell"
884 default n
885 help
886 If enabled, you will have a low level shell to examine your machine.
887 Put llshell() in your (romstage) code to start the shell.
Stefan Reinauer8677a232010-12-11 20:33:41 +0000888 See src/arch/x86/llshell/llshell.inc for details.
Stefan Reinauer5c503922010-03-13 22:07:15 +0000889
Rudolf Marek7f0e9302011-09-02 23:23:41 +0200890config TRACE
891 bool "Trace function calls"
892 default n
893 help
894 If enabled, every function will print information to console once
895 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
896 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
897 of calling function. Please note some printk releated functions
898 are omitted from trace to have good looking console dumps.
Uwe Hermann168b11b2009-10-07 16:15:40 +0000899endmenu
900
Myles Watson8f74c582009-10-20 16:10:04 +0000901config LIFT_BSP_APIC_ID
902 bool
903 default n
Myles Watsond73c1b52009-10-26 15:14:07 +0000904
905# These probably belong somewhere else, but they are needed somewhere.
906config AP_CODE_IN_CAR
907 bool
908 default n
909
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000910config RAMINIT_SYSINFO
911 bool
912 default n
913
Myles Watsond73c1b52009-10-26 15:14:07 +0000914config ENABLE_APIC_EXT_ID
915 bool
916 default n
Myles Watson2e672732009-11-12 16:38:03 +0000917
918config WARNINGS_ARE_ERRORS
919 bool
Stefan Reinauer6f57b512010-07-08 16:41:05 +0000920 default y
Patrick Georgi436f99b2009-11-27 16:55:13 +0000921
Peter Stuge51eafde2010-10-13 06:23:02 +0000922# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
923# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
924# mutually exclusive. One of these options must be selected in the
925# mainboard Kconfig if the chipset supports enabling and disabling of
926# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
927# in mainboard/Kconfig to know if the button should be enabled or not.
928
929config POWER_BUTTON_DEFAULT_ENABLE
930 def_bool n
931 help
932 Select when the board has a power button which can optionally be
933 disabled by the user.
934
935config POWER_BUTTON_DEFAULT_DISABLE
936 def_bool n
937 help
938 Select when the board has a power button which can optionally be
939 enabled by the user, e.g. when the board ships with a jumper over
940 the power switch contacts.
941
942config POWER_BUTTON_FORCE_ENABLE
943 def_bool n
944 help
945 Select when the board requires that the power button is always
946 enabled.
947
948config POWER_BUTTON_FORCE_DISABLE
949 def_bool n
950 help
951 Select when the board requires that the power button is always
952 disabled, e.g. when it has been hardwired to ground.
953
954config POWER_BUTTON_IS_OPTIONAL
955 bool
956 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
957 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
958 help
959 Internal option that controls ENABLE_POWER_BUTTON visibility.
960
Patrick Georgicc669262010-03-14 21:31:05 +0000961source src/Kconfig.deprecated_options
Stefan Reinauerb89a7612012-03-30 01:01:51 +0200962source src/vendorcode/Kconfig