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Patrick Georgi0588d192009-08-12 15:00:51 +00001##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00002## This file is part of the coreboot project.
Patrick Georgi0588d192009-08-12 15:00:51 +00003##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00004## Copyright (C) 2009-2010 coresystems GmbH
Patrick Georgi0588d192009-08-12 15:00:51 +00005##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00006## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
17## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Patrick Georgi0588d192009-08-12 15:00:51 +000018##
19
20mainmenu "Coreboot Configuration"
21
Uwe Hermannc04be932009-10-05 13:55:28 +000022menu "General setup"
23
Uwe Hermanna29ad5c2009-10-18 18:35:50 +000024config EXPERT
25 bool "Expert mode"
26 help
27 This allows you to select certain advanced configuration options.
28
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
31
Uwe Hermannc04be932009-10-05 13:55:28 +000032config LOCALVERSION
Uwe Hermann168b11b2009-10-07 16:15:40 +000033 string "Local version string"
Uwe Hermannc04be932009-10-05 13:55:28 +000034 help
35 Append an extra string to the end of the coreboot version.
36
Uwe Hermann168b11b2009-10-07 16:15:40 +000037 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
41
Patrick Georgi4b8a2412010-02-09 19:35:16 +000042config CBFS_PREFIX
43 string "CBFS prefix to use"
44 default "fallback"
45 help
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
48
Uwe Hermannc04be932009-10-05 13:55:28 +000049endmenu
50
Patrick Georgi0588d192009-08-12 15:00:51 +000051source src/mainboard/Kconfig
52source src/arch/i386/Kconfig
Uwe Hermann63a8f2a2009-10-26 21:42:13 +000053
54menu "Chipset"
55
56comment "CPU"
Patrick Georgi0588d192009-08-12 15:00:51 +000057source src/cpu/Kconfig
Uwe Hermann63a8f2a2009-10-26 21:42:13 +000058comment "Northbridge"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +000059
Uwe Hermann2bb4acf2010-03-01 17:19:55 +000060menu "HyperTransport setup"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +000061 depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
62
63choice
Uwe Hermann2bb4acf2010-03-01 17:19:55 +000064 prompt "HyperTransport frequency"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +000065 default LIMIT_HT_SPEED_AUTO
66 help
Uwe Hermann2bb4acf2010-03-01 17:19:55 +000067 This option sets the maximum permissible HyperTransport link
68 frequency.
69
70 Use of this option will only limit the autodetected HT frequency.
71 It will not (and cannot) increase the frequency beyond the
72 autodetected limits.
73
74 This is primarily used to work around poorly designed or laid out
75 HT traces on certain motherboards.
Timothy Pearson55cf7bc2010-03-01 10:30:08 +000076
77config LIMIT_HT_SPEED_200
78 bool "Limit HT frequency to 200MHz"
79config LIMIT_HT_SPEED_400
80 bool "Limit HT frequency to 400MHz"
81config LIMIT_HT_SPEED_600
82 bool "Limit HT frequency to 600MHz"
83config LIMIT_HT_SPEED_800
84 bool "Limit HT frequency to 800MHz"
85config LIMIT_HT_SPEED_1000
86 bool "Limit HT frequency to 1.0GHz"
87config LIMIT_HT_SPEED_1200
88 bool "Limit HT frequency to 1.2GHz"
89config LIMIT_HT_SPEED_1400
90 bool "Limit HT frequency to 1.4GHz"
91config LIMIT_HT_SPEED_1600
92 bool "Limit HT frequency to 1.6GHz"
93config LIMIT_HT_SPEED_1800
Uwe Hermann2bb4acf2010-03-01 17:19:55 +000094 bool "Limit HT frequency to 1.8GHz"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +000095config LIMIT_HT_SPEED_2000
Uwe Hermann2bb4acf2010-03-01 17:19:55 +000096 bool "Limit HT frequency to 2.0GHz"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +000097config LIMIT_HT_SPEED_2200
Uwe Hermann2bb4acf2010-03-01 17:19:55 +000098 bool "Limit HT frequency to 2.2GHz"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +000099config LIMIT_HT_SPEED_2400
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000100 bool "Limit HT frequency to 2.4GHz"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +0000101config LIMIT_HT_SPEED_2600
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000102 bool "Limit HT frequency to 2.6GHz"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +0000103config LIMIT_HT_SPEED_AUTO
104 bool "Autodetect HT frequency"
105endchoice
106
107choice
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000108 prompt "HyperTransport downlink width"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +0000109 default LIMIT_HT_DOWN_WIDTH_16
110 help
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000111 This option sets the maximum permissible HyperTransport
112 downlink width.
113
114 Use of this option will only limit the autodetected HT width.
115 It will not (and cannot) increase the width beyond the autodetected
116 limits.
117
118 This is primarily used to work around poorly designed or laid out HT
119 traces on certain motherboards.
Timothy Pearson55cf7bc2010-03-01 10:30:08 +0000120
121config LIMIT_HT_DOWN_WIDTH_8
122 bool "8 bits"
123config LIMIT_HT_DOWN_WIDTH_16
124 bool "16 bits"
125endchoice
126
127choice
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000128 prompt "HyperTransport uplink width"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +0000129 default LIMIT_HT_UP_WIDTH_16
130 help
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000131 This option sets the maximum permissible HyperTransport
132 uplink width.
133
134 Use of this option will only limit the autodetected HT width.
135 It will not (and cannot) increase the width beyond the autodetected
136 limits.
137
138 This is primarily used to work around poorly designed or laid out HT
139 traces on certain motherboards.
Timothy Pearson55cf7bc2010-03-01 10:30:08 +0000140
141config LIMIT_HT_UP_WIDTH_8
142 bool "8 bits"
143config LIMIT_HT_UP_WIDTH_16
144 bool "16 bits"
145endchoice
146
147endmenu
148
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000149source src/northbridge/Kconfig
150comment "Southbridge"
151source src/southbridge/Kconfig
152comment "Super I/O"
153source src/superio/Kconfig
154comment "Devices"
155source src/devices/Kconfig
156
157endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000158
Patrick Georgi0588d192009-08-12 15:00:51 +0000159config PCI_BUS_SEGN_BITS
Myles Watson74fb8f22009-09-24 15:09:11 +0000160 int
161 default 0
Patrick Georgi892b0912009-09-24 09:03:06 +0000162
Patrick Georgi0588d192009-08-12 15:00:51 +0000163config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000164 hex
Uwe Hermann748475b2009-10-09 11:47:21 +0000165 default 0x0
Patrick Georgi0588d192009-08-12 15:00:51 +0000166
167config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000168 hex
Uwe Hermann748475b2009-10-09 11:47:21 +0000169 default 0x0
Patrick Georgi0588d192009-08-12 15:00:51 +0000170
171config CPU_ADDR_BITS
172 int
173 default 36
174
175config XIP_ROM_BASE
176 hex
177 default 0xfffe0000
178
179config XIP_ROM_SIZE
180 hex
181 default 0x20000
182
183config LB_CKS_RANGE_START
184 int
185 default 49
186
187config LB_CKS_RANGE_END
188 int
189 default 125
190
191config LB_CKS_LOC
192 int
193 default 126
194
195config LOGICAL_CPUS
Myles Watson45bb25f2009-09-22 18:49:08 +0000196 bool
197 default y
Patrick Georgi0588d192009-08-12 15:00:51 +0000198
199config PCI_ROM_RUN
Patrick Georgi698c0e0e2009-08-25 17:38:24 +0000200 bool
201 default n
Patrick Georgi0588d192009-08-12 15:00:51 +0000202
Patrick Georgi0588d192009-08-12 15:00:51 +0000203config HEAP_SIZE
204 hex
Myles Watson04000f42009-10-16 19:12:49 +0000205 default 0x4000
Patrick Georgi0588d192009-08-12 15:00:51 +0000206
Patrick Georgi0588d192009-08-12 15:00:51 +0000207config DEBUG
208 bool
209 default n
210
211config USE_PRINTK_IN_CAR
212 bool
213 default n
214
215config USE_OPTION_TABLE
216 bool
217 default n
218
219config MAX_CPUS
220 int
221 default 1
222
223config MMCONF_SUPPORT_DEFAULT
224 bool
225 default n
226
227config MMCONF_SUPPORT
228 bool
229 default n
230
Myles Watson0f61a4f2009-10-16 16:32:57 +0000231config RAMTOP
Myles Watson3db199c2009-10-12 22:39:08 +0000232 hex
Myles Watson0f61a4f2009-10-16 16:32:57 +0000233 default 0x200000
Patrick Georgi0588d192009-08-12 15:00:51 +0000234
Patrick Georgi91ff0df2009-10-09 12:32:52 +0000235config ATI_RAGE_XL
236 bool
Patrick Georgi91ff0df2009-10-09 12:32:52 +0000237
Patrick Georgi0588d192009-08-12 15:00:51 +0000238source src/console/Kconfig
239
240config HAVE_ACPI_RESUME
241 bool
242 default n
243
244config ACPI_SSDTX_NUM
245 int
246 default 0
247
Patrick Georgi0588d192009-08-12 15:00:51 +0000248config HAVE_FALLBACK_BOOT
249 bool
250 default y
251
252config USE_FALLBACK_IMAGE
253 bool
254 default y
255
Patrick Georgi37ea3412009-10-03 21:04:13 +0000256config HAVE_FAILOVER_BOOT
257 bool
258 default n
259
260config USE_FAILOVER_IMAGE
261 bool
262 default n
263
Patrick Georgi0588d192009-08-12 15:00:51 +0000264config HAVE_HARD_RESET
265 bool
Patrick Georgi37bdb872010-02-27 08:39:04 +0000266 default y if BOARD_HAS_HARD_RESET
Uwe Hermann748475b2009-10-09 11:47:21 +0000267 default n
Patrick Georgi37bdb872010-02-27 08:39:04 +0000268 help
269 This variable specifies whether a given board has a hard_reset
270 function, no matter if it's provided by board code or chipset code.
271
272config BOARD_HAS_HARD_RESET
273 bool
274 default n
275 help
276 This variable specifies whether a given board has a reset.c
277 file containing a hard_reset() function.
Patrick Georgi0588d192009-08-12 15:00:51 +0000278
Patrick Georgi9ea7bff2010-02-28 18:23:00 +0000279config BOARD_HAS_FADT
280 bool
281 default n
282 help
283 This variable specifies whether a given board has a board-local
284 FADT in fadt.c. Long-term, those should be moved to appropriate
285 chipset components (eg. southbridge)
286
287config HAVE_BUS_CONFIG
288 bool
289 default n
290 help
291 This variable specifies whether a given board has a get_bus_conf.c
292 file containing bus configuration data.
293
Patrick Georgi0588d192009-08-12 15:00:51 +0000294config HAVE_INIT_TIMER
295 bool
Patrick Georgi1f807fd2010-01-04 20:09:27 +0000296 default n if UDELAY_IO
Myles Watsond73c1b52009-10-26 15:14:07 +0000297 default y
Patrick Georgi0588d192009-08-12 15:00:51 +0000298
299config HAVE_MAINBOARD_RESOURCES
300 bool
301 default n
302
Patrick Georgi0588d192009-08-12 15:00:51 +0000303config HAVE_OPTION_TABLE
304 bool
305 default y
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000306 help
307 This variable specifies whether a given board has a cmos.layout
308 file containing NVRAM/CMOS bit definitions.
309 It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
Patrick Georgi0588d192009-08-12 15:00:51 +0000310
Patrick Georgi0588d192009-08-12 15:00:51 +0000311config PIRQ_ROUTE
312 bool
313 default n
314
315config HAVE_SMI_HANDLER
316 bool
317 default n
318
319config PCI_IO_CFG_EXT
320 bool
321 default n
322
323config IOAPIC
324 bool
325 default n
326
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000327# TODO: Can probably be removed once all chipsets have kconfig options for it.
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000328config VIDEO_MB
329 int
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000330 default 0
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000331
Myles Watson45bb25f2009-09-22 18:49:08 +0000332config USE_WATCHDOG_ON_BOOT
333 bool
334 default n
335
336config VGA
337 bool
338 default n
339 help
340 Build board-specific VGA code.
341
342config GFXUMA
343 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000344 default n
Myles Watson45bb25f2009-09-22 18:49:08 +0000345 help
346 Enable Unified Memory Architecture for graphics.
347
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000348# TODO
349# menu "Drivers"
Uwe Hermann168b11b2009-10-07 16:15:40 +0000350#
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000351# endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000352
Myles Watsond73c1b52009-10-26 15:14:07 +0000353#TODO Remove this option or make it useful.
354config HAVE_LOW_TABLES
355 bool
356 default y
357 help
358 This Option is unused in the code. Since two boards try to set it to
359 'n', they may be broken. We either need to make the option useful or
360 get rid of it. The broken boards are:
361 asus/m2v-mx_se
362 supermicro/h8dme
363
364config HAVE_HIGH_TABLES
365 bool
Stefan Reinauer13f2bb02010-02-25 13:45:08 +0000366 default y
Myles Watsond73c1b52009-10-26 15:14:07 +0000367 help
368 This variable specifies whether a given northbridge has high table
369 support.
370 It is set in northbridge/*/Kconfig.
371 Whether or not the high tables are actually written by coreboot is
372 configurable by the user via WRITE_HIGH_TABLES.
373
Myles Watsonb8e20272009-10-15 13:35:47 +0000374config HAVE_ACPI_TABLES
375 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000376 help
377 This variable specifies whether a given board has ACPI table support.
378 It is usually set in mainboard/*/Kconfig.
379 Whether or not the ACPI tables are actually generated by coreboot
380 is configurable by the user via GENERATE_ACPI_TABLES.
Myles Watsonb8e20272009-10-15 13:35:47 +0000381
382config HAVE_MP_TABLE
383 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000384 help
385 This variable specifies whether a given board has MP table support.
386 It is usually set in mainboard/*/Kconfig.
387 Whether or not the MP table is actually generated by coreboot
388 is configurable by the user via GENERATE_MP_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000389
390config HAVE_PIRQ_TABLE
391 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000392 help
393 This variable specifies whether a given board has PIRQ table support.
394 It is usually set in mainboard/*/Kconfig.
395 Whether or not the PIRQ table is actually generated by coreboot
396 is configurable by the user via GENERATE_PIRQ_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000397
Myles Watsond73c1b52009-10-26 15:14:07 +0000398#These Options are here to avoid "undefined" warnings.
399#The actual selection and help texts are in the following menu.
400
401config GENERATE_ACPI_TABLES
Myles Watsonb8e20272009-10-15 13:35:47 +0000402 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000403 default HAVE_ACPI_TABLES
404
405config GENERATE_MP_TABLE
406 bool
407 default HAVE_MP_TABLE
408
409config GENERATE_PIRQ_TABLE
410 bool
411 default HAVE_PIRQ_TABLE
412
413config WRITE_HIGH_TABLES
414 bool
415 default HAVE_HIGH_TABLES
Myles Watsonb8e20272009-10-15 13:35:47 +0000416
Uwe Hermann168b11b2009-10-07 16:15:40 +0000417menu "System tables"
Myles Watson45bb25f2009-09-22 18:49:08 +0000418
Myles Watsonb8e20272009-10-15 13:35:47 +0000419config WRITE_HIGH_TABLES
Myles Watson45bb25f2009-09-22 18:49:08 +0000420 bool "Write 'high' tables to avoid being overwritten in F segment"
Myles Watsonb8e20272009-10-15 13:35:47 +0000421 depends on HAVE_HIGH_TABLES
Myles Watson45bb25f2009-09-22 18:49:08 +0000422 default y
423
424config MULTIBOOT
Uwe Hermann168b11b2009-10-07 16:15:40 +0000425 bool "Generate Multiboot tables (for GRUB2)"
Ronald G. Minnich7f91d922009-11-09 17:56:47 +0000426 default y
Myles Watson45bb25f2009-09-22 18:49:08 +0000427
Myles Watsonb8e20272009-10-15 13:35:47 +0000428config GENERATE_ACPI_TABLES
429 depends on HAVE_ACPI_TABLES
Myles Watson45bb25f2009-09-22 18:49:08 +0000430 bool "Generate ACPI tables"
Myles Watsonb8e20272009-10-15 13:35:47 +0000431 default y
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000432 help
433 Generate ACPI tables for this board.
434
435 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000436
Myles Watsonb8e20272009-10-15 13:35:47 +0000437config GENERATE_MP_TABLE
438 depends on HAVE_MP_TABLE
Myles Watson45bb25f2009-09-22 18:49:08 +0000439 bool "Generate an MP table"
Myles Watsonb8e20272009-10-15 13:35:47 +0000440 default y
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000441 help
442 Generate an MP table (conforming to the Intel MultiProcessor
443 specification 1.4) for this board.
444
445 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000446
Myles Watsonb8e20272009-10-15 13:35:47 +0000447config GENERATE_PIRQ_TABLE
448 depends on HAVE_PIRQ_TABLE
Myles Watson45bb25f2009-09-22 18:49:08 +0000449 bool "Generate a PIRQ table"
Myles Watsonb8e20272009-10-15 13:35:47 +0000450 default y
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000451 help
452 Generate a PIRQ table for this board.
453
454 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000455
456endmenu
457
Patrick Georgi0588d192009-08-12 15:00:51 +0000458menu "Payload"
459
Patrick Georgi0588d192009-08-12 15:00:51 +0000460choice
Uwe Hermann168b11b2009-10-07 16:15:40 +0000461 prompt "Add a payload"
Patrick Georgi0588d192009-08-12 15:00:51 +0000462 default PAYLOAD_NONE
463
Uwe Hermann168b11b2009-10-07 16:15:40 +0000464config PAYLOAD_NONE
465 bool "None"
466 help
467 Select this option if you want to create an "empty" coreboot
468 ROM image for a certain mainboard, i.e. a coreboot ROM image
469 which does not yet contain a payload.
470
471 For such an image to be useful, you have to use 'cbfstool'
472 to add a payload to the ROM image later.
473
Patrick Georgi0588d192009-08-12 15:00:51 +0000474config PAYLOAD_ELF
Uwe Hermann168b11b2009-10-07 16:15:40 +0000475 bool "An ELF executable payload"
Patrick Georgi0588d192009-08-12 15:00:51 +0000476 help
477 Select this option if you have a payload image (an ELF file)
478 which coreboot should run as soon as the basic hardware
479 initialization is completed.
480
481 You will be able to specify the location and file name of the
482 payload image later.
Patrick Georgi0588d192009-08-12 15:00:51 +0000483
484endchoice
485
Patrick Georgi0588d192009-08-12 15:00:51 +0000486config FALLBACK_PAYLOAD_FILE
Cristi Magherusanb5034d42009-08-17 14:47:32 +0000487 string "Payload path and filename"
Patrick Georgi0588d192009-08-12 15:00:51 +0000488 depends on PAYLOAD_ELF
489 default "payload.elf"
490 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000491 The path and filename of the ELF executable file to use as payload.
Patrick Georgi0588d192009-08-12 15:00:51 +0000492
Uwe Hermann168b11b2009-10-07 16:15:40 +0000493# TODO: Defined if no payload? Breaks build?
494config COMPRESSED_PAYLOAD_LZMA
495 bool "Use LZMA compression for payloads"
496 default y
497 depends on PAYLOAD_ELF
498 help
499 In order to reduce the size payloads take up in the ROM chip
500 coreboot can compress them using the LZMA algorithm.
501
Myles Watson04000f42009-10-16 19:12:49 +0000502config COMPRESSED_PAYLOAD_NRV2B
Peter Stuged7b37b02009-10-17 03:00:04 +0000503 bool
Myles Watson04000f42009-10-16 19:12:49 +0000504 default n
505
Peter Stugea758ca22009-09-17 16:21:31 +0000506endmenu
507
508menu "VGA BIOS"
509
510config VGA_BIOS
511 bool "Add a VGA BIOS image"
512 help
513 Select this option if you have a VGA BIOS image that you would
514 like to add to your ROM.
515
516 You will be able to specify the location and file name of the
517 image later.
518
Cristi Magherusan488c36c2009-08-17 14:46:13 +0000519config FALLBACK_VGA_BIOS_FILE
520 string "VGA BIOS path and filename"
521 depends on VGA_BIOS
522 default "vgabios.bin"
523 help
524 The path and filename of the file to use as VGA BIOS.
525
526config FALLBACK_VGA_BIOS_ID
Uwe Hermann81b3c0a2009-10-30 12:56:59 +0000527 string "VGA device PCI IDs"
Cristi Magherusan488c36c2009-08-17 14:46:13 +0000528 depends on VGA_BIOS
529 default "1106,3230"
530 help
Uwe Hermann168b11b2009-10-07 16:15:40 +0000531 The comma-separated PCI vendor and device ID that would associate
532 your VGA BIOS to your video card.
533
534 Example: 1106,3230
535
536 In the above example 1106 is the PCI vendor ID (in hex, but without
537 the "0x" prefix) and 3230 specifies the PCI device ID of the
538 video card (also in hex, without "0x" prefix).
Cristi Magherusan488c36c2009-08-17 14:46:13 +0000539
Stefan Reinauer800379f2010-03-01 08:34:19 +0000540config INTEL_MBI
541 bool "Add an MBI image"
542 depends on NORTHBRIDGE_INTEL_I82830
543 help
544 Select this option if you have an Intel MBI image that you would
545 like to add to your ROM.
546
547 You will be able to specify the location and file name of the
548 image later.
549
550config FALLBACK_MBI_FILE
551 string "Intel MBI path and filename"
552 depends on INTEL_MBI
553 default "mbi.bin"
554 help
555 The path and filename of the file to use as VGA BIOS.
556
557endmenu
558
559menu "Bootsplash"
560 depends on PCI_OPTION_ROM_RUN_YABEL
561
562config BOOTSPLASH
563 prompt "Show graphical bootsplash"
564 bool
565 depends on PCI_OPTION_ROM_RUN_YABEL
566 help
567 This option shows a graphical bootsplash screen. The grapics are
568 loaded from the CBFS file bootsplash.jpg.
569
570config FALLBACK_BOOTSPLASH_FILE
571 string "Bootsplash path and filename"
572 depends on BOOTSPLASH
573 default "bootsplash.jpg"
574 help
575 The path and filename of the file to use as graphical bootsplash
576 screen. The file format has to be jpg.
577
578# TODO: Turn this into a "choice".
579config FRAMEBUFFER_VESA_MODE
580 prompt "VESA framebuffer video mode"
581 hex
582 default 0x117
583 depends on BOOTSPLASH
584 help
585 This option sets the resolution used for the coreboot framebuffer and
586 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
587 some day make this a "choice".
588
589config COREBOOT_KEEP_FRAMEBUFFER
590 prompt "Keep VESA framebuffer"
591 bool
592 depends on BOOTSPLASH
593 help
594 This option keeps the framebuffer mode set after coreboot finishes
595 execution. If this option is enabled, coreboot will pass a
596 framebuffer entry in its coreboot table and the payload will need a
597 framebuffer driver. If this option is disabled, coreboot will switch
598 back to text mode before handing control to a payload.
599
Patrick Georgi0588d192009-08-12 15:00:51 +0000600endmenu
601
Uwe Hermann168b11b2009-10-07 16:15:40 +0000602menu "Debugging"
603
604# TODO: Better help text and detailed instructions.
Patrick Georgi0588d192009-08-12 15:00:51 +0000605config GDB_STUB
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000606 bool "GDB debugging support"
Patrick Georgi0588d192009-08-12 15:00:51 +0000607 default y
608 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000609 If enabled, you will be able to set breakpoints for gdb debugging.
610 See src/arch/i386/lib/c_start.S for details.
Patrick Georgi0588d192009-08-12 15:00:51 +0000611
Uwe Hermann01ce6012010-03-05 10:03:50 +0000612config DEBUG_RAM_SETUP
613 bool "Output verbose RAM init debug messages"
614 default n
615 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
616 || NORTHBRIDGE_AMD_AMDK8 \
617 || NORTHBRIDGE_VIA_CN700 \
618 || NORTHBRIDGE_VIA_CX700 \
619 || NORTHBRIDGE_VIA_VX800 \
620 || NORTHBRIDGE_INTEL_E7501 \
621 || NORTHBRIDGE_INTEL_I440BX \
622 || NORTHBRIDGE_INTEL_I82810 \
623 || NORTHBRIDGE_INTEL_I82830 \
624 || NORTHBRIDGE_INTEL_I945)
625 help
626 This option enables additional RAM init related debug messages.
627 It is recommended to enable this when debugging issues on your
628 board which might be RAM init related.
629
630 Note: This option will increase the size of the coreboot image.
631
632 If unsure, say N.
633
634config DEBUG_SMBUS
635 bool "Output verbose SMBus debug messages"
636 default n
637 depends on (SOUTHBRIDGE_VIA_VT8237R \
638 || NORTHBRIDGE_VIA_VX800 \
639 || NORTHBRIDGE_VIA_CX700 \
640 || NORTHBRIDGE_AMD_AMDK8)
641 help
642 This option enables additional SMBus (and SPD) debug messages.
643
644 Note: This option will increase the size of the coreboot image.
645
646 If unsure, say N.
647
648config DEBUG_SMI
649 bool "Output verbose SMI debug messages"
650 default n
651 depends on HAVE_SMI_HANDLER
652 help
653 This option enables additional SMI related debug messages.
654
655 Note: This option will increase the size of the coreboot image.
656
657 If unsure, say N.
658
659config X86EMU_DEBUG
660 bool "Output verbose x86emu debug messages"
661 default n
662 depends on PCI_OPTION_ROM_RUN_YABEL
663 help
664 This option enables additional x86emu related debug messages.
665
666 Note: This option will increase the size of the coreboot image.
667
668 If unsure, say N.
669
670config X86EMU_DEBUG_JMP
671 bool "Trace JMP/RETF"
672 default n
673 depends on X86EMU_DEBUG
674 help
675 Print information about JMP and RETF opcodes from x86emu.
676
677 Note: This option will increase the size of the coreboot image.
678
679 If unsure, say N.
680
681config X86EMU_DEBUG_TRACE
682 bool "Trace all opcodes"
683 default n
684 depends on X86EMU_DEBUG
685 help
686 Print _all_ opcodes that are executed by x86emu.
687
688 WARNING: This will produce a LOT of output and take a long time.
689
690 Note: This option will increase the size of the coreboot image.
691
692 If unsure, say N.
693
694config X86EMU_DEBUG_PNP
695 bool "Log Plug&Play accesses"
696 default n
697 depends on X86EMU_DEBUG
698 help
699 Print Plug And Play accesses made by option ROMs.
700
701 Note: This option will increase the size of the coreboot image.
702
703 If unsure, say N.
704
705config X86EMU_DEBUG_DISK
706 bool "Log Disk I/O"
707 default n
708 depends on X86EMU_DEBUG
709 help
710 Print Disk I/O related messages.
711
712 Note: This option will increase the size of the coreboot image.
713
714 If unsure, say N.
715
716config X86EMU_DEBUG_PMM
717 bool "Log PMM"
718 default n
719 depends on X86EMU_DEBUG
720 help
721 Print messages related to POST Memory Manager (PMM).
722
723 Note: This option will increase the size of the coreboot image.
724
725 If unsure, say N.
726
727
728config X86EMU_DEBUG_VBE
729 bool "Debug VESA BIOS Extensions"
730 default n
731 depends on X86EMU_DEBUG
732 help
733 Print messages related to VESA BIOS Extension (VBE) functions.
734
735 Note: This option will increase the size of the coreboot image.
736
737 If unsure, say N.
738
739config X86EMU_DEBUG_INT10
740 bool "Redirect INT10 output to console"
741 default n
742 depends on X86EMU_DEBUG
743 help
744 Let INT10 (i.e. character output) calls print messages to debug output.
745
746 Note: This option will increase the size of the coreboot image.
747
748 If unsure, say N.
749
750config X86EMU_DEBUG_INTERRUPTS
751 bool "Log intXX calls"
752 default n
753 depends on X86EMU_DEBUG
754 help
755 Print messages related to interrupt handling.
756
757 Note: This option will increase the size of the coreboot image.
758
759 If unsure, say N.
760
761config X86EMU_DEBUG_CHECK_VMEM_ACCESS
762 bool "Log special memory accesses"
763 default n
764 depends on X86EMU_DEBUG
765 help
766 Print messages related to accesses to certain areas of the virtual
767 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
768
769 Note: This option will increase the size of the coreboot image.
770
771 If unsure, say N.
772
773config X86EMU_DEBUG_MEM
774 bool "Log all memory accesses"
775 default n
776 depends on X86EMU_DEBUG
777 help
778 Print memory accesses made by option ROM.
779 Note: This also includes accesses to fetch instructions.
780
781 Note: This option will increase the size of the coreboot image.
782
783 If unsure, say N.
784
785config X86EMU_DEBUG_IO
786 bool "Log IO accesses"
787 default n
788 depends on X86EMU_DEBUG
789 help
790 Print I/O accesses made by option ROM.
791
792 Note: This option will increase the size of the coreboot image.
793
794 If unsure, say N.
795
Uwe Hermann168b11b2009-10-07 16:15:40 +0000796endmenu
797
Myles Watson8f74c582009-10-20 16:10:04 +0000798config LIFT_BSP_APIC_ID
799 bool
800 default n
Myles Watsond73c1b52009-10-26 15:14:07 +0000801
802# These probably belong somewhere else, but they are needed somewhere.
803config AP_CODE_IN_CAR
804 bool
805 default n
806
807config USE_INIT
808 bool
809 default n
810
811config ENABLE_APIC_EXT_ID
812 bool
813 default n
Myles Watson2e672732009-11-12 16:38:03 +0000814
815config WARNINGS_ARE_ERRORS
816 bool
817 default n
Patrick Georgi436f99b2009-11-27 16:55:13 +0000818
819config ID_SECTION_OFFSET
820 hex
821 default 0x10