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review.coreboot.org / coreboot / 0588d19abef62dad63a7794a37bdd6a71c526d9e / . / src / Kconfig
blob: ca7fa61443d353655f7067cfc4185f4f96cd6f3a [file] [log] [blame]
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame^]1##
2## This file is part of the coreboot repair project.
3##
4## Redistribution and use in source and binary forms, with or without
5## modification, are permitted provided that the following conditions
6## are met:
7## 1. Redistributions of source code must retain the above copyright
8## notice, this list of conditions and the following disclaimer.
9## 2. Redistributions in binary form must reproduce the above copyright
10## notice, this list of conditions and the following disclaimer in the
11## documentation and/or other materials provided with the distribution.
12## 3. The name of the author may not be used to endorse or promote products
13## derived from this software without specific prior written permission.
14##
15## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25## SUCH DAMAGE.
26##
27
28mainmenu "Coreboot Configuration"
29
30source src/mainboard/Kconfig
31source src/arch/i386/Kconfig
32source src/arch/ppc/Kconfig
33source src/devices/Kconfig
34source src/northbridge/Kconfig
35source src/southbridge/Kconfig
36source src/superio/Kconfig
37source src/cpu/Kconfig
38
39config CBFS
40 bool
41 default y
42
43config HAVE_HIGH_TABLES
44 bool
45 default y
46
47config PCI_BUS_SEGN_BITS
48 int
49 default 0
50
51config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
52 hex
53 default 0
54
55config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
56 hex
57 default 0
58
59config CPU_ADDR_BITS
60 int
61 default 36
62
63config XIP_ROM_BASE
64 hex
65 default 0xfffe0000
66
67config XIP_ROM_SIZE
68 hex
69 default 0x20000
70
71config LB_CKS_RANGE_START
72 int
73 default 49
74
75config LB_CKS_RANGE_END
76 int
77 default 125
78
79config LB_CKS_LOC
80 int
81 default 126
82
83config LOGICAL_CPUS
84 int
85 default 1
86
87config PCI_ROM_RUN
88 int
89 default 0
90
91config HT_CHAIN_UNITID_BASE
92 int
93 default 1
94
95config HT_CHAIN_END_UNITID_BASE
96 int
97 default 32
98
99config HEAP_SIZE
100 hex
101 default 0x2000
102
103config COREBOOT_V2
104 bool
105 default y
106
107config COREBOOT_V4
108 bool
109 default y
110
111config DEBUG
112 bool
113 default n
114
115config USE_PRINTK_IN_CAR
116 bool
117 default n
118
119config USE_OPTION_TABLE
120 bool
121 default n
122
123config MAX_CPUS
124 int
125 default 1
126
127config MMCONF_SUPPORT_DEFAULT
128 bool
129 default n
130
131config MMCONF_SUPPORT
132 bool
133 default n
134
135config LB_MEM_TOPK
136 int
137 default 2048
138
139config MULTIBOOT
140 bool
141 default n
142
143config COMPRESSED_PAYLOAD_LZMA
144 bool
145 default y
146
147config COMPRESSED_PAYLOAD_NRV2B
148 bool
149 default n
150
151source src/console/Kconfig
152
153config HAVE_ACPI_RESUME
154 bool
155 default n
156
157config ACPI_SSDTX_NUM
158 int
159 default 0
160
161config HAVE_ACPI_TABLES
162 bool
163 default n
164
165config HAVE_FALLBACK_BOOT
166 bool
167 default y
168
169config USE_FALLBACK_IMAGE
170 bool
171 default y
172
173config HAVE_HARD_RESET
174 bool
175 default n
176
177config HAVE_INIT_TIMER
178 bool
179 default n
180
181config HAVE_MAINBOARD_RESOURCES
182 bool
183 default n
184
185config HAVE_MOVNTI
186 bool
187 default y
188
189config HAVE_MP_TABLE
190 bool
191 default n
192
193config HAVE_OPTION_TABLE
194 bool
195 default y
196
197config HAVE_PIRQ_TABLE
198 bool
199 default n
200
201config PIRQ_ROUTE
202 bool
203 default n
204
205config HAVE_SMI_HANDLER
206 bool
207 default n
208
209config PCI_IO_CFG_EXT
210 bool
211 default n
212
213config IOAPIC
214 bool
215 default n
216
217menu "Drivers"
218
219endmenu
220
221menu "Payload"
222
223config COMPRESSED_PAYLOAD_LZMA
224 bool "Use LZMA compression for payloads"
225 default yes
226
227choice
228 prompt "Payload type"
229 default PAYLOAD_NONE
230
231config PAYLOAD_ELF
232 bool "An ELF executable payload file"
233 help
234 Select this option if you have a payload image (an ELF file)
235 which coreboot should run as soon as the basic hardware
236 initialization is completed.
237
238 You will be able to specify the location and file name of the
239 payload image later.
240
241config PAYLOAD_NONE
242 bool "No payload"
243 help
244 Select this option if you want to create an "empty" coreboot
245 ROM image for a certain mainboard, i.e. a coreboot ROM image
246 which does not yet contain a payload.
247
248 For such an image to be useful, you have to use the 'lar' tool
249 to add a payload to the ROM image later.
250
251endchoice
252
253config NORMAL_PAYLOAD_FILE
254 string "Normal payload path and filename"
255 depends on PAYLOAD_ELF
256 default "payload.elf"
257 help
258 The path and filename of the ELF executable file to use as normal payload.
259
260config FALLBACK_PAYLOAD_FILE
261 string "Fallback payload path and filename"
262 depends on PAYLOAD_ELF
263 default "payload.elf"
264 help
265 The path and filename of the ELF executable file to use as fallback payload.
266
267endmenu
268
269config GDB_STUB
270 bool "Enable GDB debugging support"
271 default y
272 help
273 If this is set, then you will be able to set breakpoints for gdb debugging.
274 See: src/arch/i386/lib/c_start.S
275