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Patrick Georgi0588d192009-08-12 15:00:51 +00001##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00002## This file is part of the coreboot project.
Patrick Georgi0588d192009-08-12 15:00:51 +00003##
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -05004## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
Stefan Reinauer16f515a2010-01-20 18:44:30 +00005## Copyright (C) 2009-2010 coresystems GmbH
Patrick Georgi0588d192009-08-12 15:00:51 +00006##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00007## This program is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; version 2 of the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +010018## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Patrick Georgi0588d192009-08-12 15:00:51 +000019##
20
Uwe Hermannad8c95f2012-04-12 22:00:03 +020021mainmenu "coreboot configuration"
Patrick Georgi0588d192009-08-12 15:00:51 +000022
Uwe Hermannc04be932009-10-05 13:55:28 +000023menu "General setup"
24
Uwe Hermanna29ad5c2009-10-18 18:35:50 +000025config EXPERT
26 bool "Expert mode"
27 help
28 This allows you to select certain advanced configuration options.
29
30 Warning: Only enable this option if you really know what you are
31 doing! You have been warned!
32
Uwe Hermannc04be932009-10-05 13:55:28 +000033config LOCALVERSION
Uwe Hermann168b11b2009-10-07 16:15:40 +000034 string "Local version string"
Uwe Hermannc04be932009-10-05 13:55:28 +000035 help
36 Append an extra string to the end of the coreboot version.
37
Uwe Hermann168b11b2009-10-07 16:15:40 +000038 This can be useful if, for instance, you want to append the
39 respective board's hostname or some other identifying string to
40 the coreboot version number, so that you can easily distinguish
41 boot logs of different boards from each other.
42
Patrick Georgi4b8a2412010-02-09 19:35:16 +000043config CBFS_PREFIX
44 string "CBFS prefix to use"
45 default "fallback"
46 help
47 Select the prefix to all files put into the image. It's "fallback"
48 by default, "normal" is a common alternative.
49
Patrick Georgi23d89cc2010-03-16 01:17:19 +000050choice
Uwe Hermannad8c95f2012-04-12 22:00:03 +020051 prompt "Compiler to use"
Patrick Georgi23d89cc2010-03-16 01:17:19 +000052 default COMPILER_GCC
53 help
54 This option allows you to select the compiler used for building
55 coreboot.
56
57config COMPILER_GCC
58 bool "GCC"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020059 help
60 Use the GNU Compiler Collection (GCC) to build coreboot.
61
62 For details see http://gcc.gnu.org.
63
Patrick Georgi23d89cc2010-03-16 01:17:19 +000064config COMPILER_LLVM_CLANG
65 bool "LLVM/clang"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020066 help
67 Use LLVM/clang to build coreboot.
68
69 For details see http://clang.llvm.org.
70
Patrick Georgi23d89cc2010-03-16 01:17:19 +000071endchoice
72
Patrick Georgi9b0de712013-12-29 18:45:23 +010073config ANY_TOOLCHAIN
74 bool "Allow building with any toolchain"
75 default n
76 depends on COMPILER_GCC
77 help
78 Many toolchains break when building coreboot since it uses quite
79 unusual linker features. Unless developers explicitely request it,
80 we'll have to assume that they use their distro compiler by mistake.
81 Make sure that using patched compilers is a conscious decision.
82
Patrick Georgi516a2a72010-03-25 21:45:25 +000083config CCACHE
Uwe Hermannad8c95f2012-04-12 22:00:03 +020084 bool "Use ccache to speed up (re)compilation"
Patrick Georgi516a2a72010-03-25 21:45:25 +000085 default n
86 help
87 Enables the use of ccache for faster builds.
Uwe Hermannad8c95f2012-04-12 22:00:03 +020088
89 Requires the ccache utility in your system $PATH.
90
91 For details see https://ccache.samba.org.
Patrick Georgi516a2a72010-03-25 21:45:25 +000092
Stefan Reinauer9bf78102010-08-09 13:28:18 +000093config SCONFIG_GENPARSER
94 bool "Generate SCONFIG parser using flex and bison"
95 default n
96 depends on EXPERT
97 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +020098 Enable this option if you are working on the sconfig device tree
99 parser and made changes to sconfig.l and sconfig.y.
100
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000101 Otherwise, say N.
102
Joe Korty6d772522010-05-19 18:41:15 +0000103config USE_OPTION_TABLE
104 bool "Use CMOS for configuration values"
105 default n
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000106 depends on HAVE_OPTION_TABLE
Joe Korty6d772522010-05-19 18:41:15 +0000107 help
108 Enable this option if coreboot shall read options from the "CMOS"
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200109 NVRAM instead of using hard-coded values.
Joe Korty6d772522010-05-19 18:41:15 +0000110
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000111config COMPRESS_RAMSTAGE
112 bool "Compress ramstage with LZMA"
113 default y
114 help
115 Compress ramstage to save memory in the flash image. Note
116 that decompression might slow down booting if the boot flash
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200117 is connected through a slow link (i.e. SPI).
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000118
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200119config INCLUDE_CONFIG_FILE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200120 bool "Include the coreboot .config file into the ROM image"
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200121 default y
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200122 help
123 Include the .config file that was used to compile coreboot
124 in the (CBFS) ROM image. This is useful if you want to know which
125 options were used to build a specific coreboot.rom image.
126
Daniele Forsi53847a22014-07-22 18:00:56 +0200127 Saying Y here will increase the image size by 2-3KB.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200128
129 You can use the following command to easily list the options:
130
131 grep -a CONFIG_ coreboot.rom
132
133 Alternatively, you can also use cbfstool to print the image
134 contents (including the raw 'config' item we're looking for).
135
136 Example:
137
138 $ cbfstool coreboot.rom print
139 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
140 offset 0x0
141 Alignment: 64 bytes
Steve Goodrichf0269122012-05-18 11:18:47 -0600142
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200143 Name Offset Type Size
144 cmos_layout.bin 0x0 cmos layout 1159
145 fallback/romstage 0x4c0 stage 339756
Daniele Forsi53847a22014-07-22 18:00:56 +0200146 fallback/ramstage 0x53440 stage 186664
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200147 fallback/payload 0x80dc0 payload 51526
148 config 0x8d740 raw 3324
149 (empty) 0x8e480 null 3610440
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200150
Kyösti Mälkkif8bf5a12013-10-11 22:08:02 +0300151config EARLY_CBMEM_INIT
152 bool
153 default n
154 help
155 Make coreboot initialize the CBMEM structures while running in ROM
156 stage. This is useful when the ROM stage wants to communicate
157 some, for instance, execution timestamps. It needs support in
158 romstage.c and should be enabled by the board's Kconfig.
159
Kyösti Mälkkideb2cb22014-03-28 23:46:45 +0200160config BROKEN_CAR_MIGRATE
161 bool
162 default y if !EARLY_CBMEM_INIT && HAVE_ACPI_RESUME
163 default n
164 help
165 Many boards use CAR_GLOBAL but have no EARLY_CBMEM_INIT and
166 manage CAR migration on S3 resume path only. Couple boards use
167 CAR_GLOBAL and never do CAR migration.
168
Aaron Durbindf3a1092013-03-13 12:41:44 -0500169config DYNAMIC_CBMEM
170 bool "The CBMEM space is dynamically grown."
171 default n
Kyösti Mälkkif8bf5a12013-10-11 22:08:02 +0300172 select EARLY_CBMEM_INIT
Aaron Durbindf3a1092013-03-13 12:41:44 -0500173 help
174 Instead of reserving a static amount of CBMEM space the CBMEM
175 area grows dynamically. CBMEM can be used both in romstage (after
176 memory initialization) and ramstage.
177
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700178config COLLECT_TIMESTAMPS
179 bool "Create a table of timestamps collected during boot"
Kyösti Mälkki26447932013-10-11 21:14:59 +0300180 default n
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700181 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200182 Make coreboot create a table of timer-ID/timer-value pairs to
183 allow measuring time spent at different phases of the boot process.
184
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200185config USE_BLOBS
186 bool "Allow use of binary-only repository"
187 default n
188 help
189 This draws in the blobs repository, which contains binary files that
190 might be required for some chipsets or boards.
191 This flag ensures that a "Free" option remains available for users.
192
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800193config COVERAGE
194 bool "Code coverage support"
195 depends on COMPILER_GCC
196 default n
197 help
198 Add code coverage support for coreboot. This will store code
199 coverage information in CBMEM for extraction from user space.
200 If unsure, say N.
201
Stefan Reinauer58470e32014-10-17 13:08:36 +0200202config RELOCATABLE_MODULES
203 bool "Relocatable Modules"
204 default n
205 help
206 If RELOCATABLE_MODULES is selected then support is enabled for
207 building relocatable modules in the RAM stage. Those modules can be
208 loaded anywhere and all the relocations are handled automatically.
209
210config RELOCATABLE_RAMSTAGE
211 depends on (RELOCATABLE_MODULES && DYNAMIC_CBMEM)
212 bool "Build the ramstage to be relocatable in 32-bit address space."
213 default n
214 help
215 The reloctable ramstage support allows for the ramstage to be built
216 as a relocatable module. The stage loader can identify a place
217 out of the OS way so that copying memory is unnecessary during an S3
218 wake. When selecting this option the romstage is responsible for
219 determing a stack location to use for loading the ramstage.
220
221config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
222 depends on RELOCATABLE_RAMSTAGE
223 bool "Cache the relocated ramstage outside of cbmem."
224 default n
225 help
226 The relocated ramstage is saved in an area specified by the
227 by the board and/or chipset.
228
229choice
230 prompt "Bootblock behaviour"
231 default BOOTBLOCK_SIMPLE
232
233config BOOTBLOCK_SIMPLE
234 bool "Always load fallback"
235
236config BOOTBLOCK_NORMAL
237 bool "Switch to normal if CMOS says so"
238
239endchoice
240
241config BOOTBLOCK_SOURCE
242 string
243 default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
244 default "bootblock_normal.c" if BOOTBLOCK_NORMAL
245
246config UPDATE_IMAGE
247 bool "Update existing coreboot.rom image"
248 default n
249 help
250 If this option is enabled, no new coreboot.rom file
251 is created. Instead it is expected that there already
252 is a suitable file for further processing.
253 The bootblock will not be modified.
254
Uwe Hermannc04be932009-10-05 13:55:28 +0000255endmenu
256
Patrick Georgi0588d192009-08-12 15:00:51 +0000257source src/mainboard/Kconfig
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000258
259# This option is used to set the architecture of a mainboard to X86.
260# It is usually set in mainboard/*/Kconfig.
261config ARCH_X86
262 bool
263 default n
Ronald G. Minnich78a16672012-11-29 16:28:21 -0800264 select PCI
265
Gabe Black51edd542013-09-30 23:00:33 -0700266config ARCH_ARM
David Hendricks5367e472012-11-28 20:16:28 -0800267 bool
268 default n
269
Furquan Shaikh2af76f42014-04-28 16:39:40 -0700270config ARCH_ARM64
271 bool
272 default n
273
Stefan Reinauer8677a232010-12-11 20:33:41 +0000274source src/arch/x86/Kconfig
Gabe Black51edd542013-09-30 23:00:33 -0700275source src/arch/arm/Kconfig
Furquan Shaikh2af76f42014-04-28 16:39:40 -0700276source src/arch/arm64/Kconfig
Gabe Black545c0ca2013-07-07 14:04:26 -0700277
Peter Stuge4d77ed92014-02-07 03:58:24 +0100278source src/vendorcode/Kconfig
279
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200280config SYSTEM_TYPE_LAPTOP
281 default n
282 bool
283
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000284menu "Chipset"
285
286comment "CPU"
Patrick Georgi0588d192009-08-12 15:00:51 +0000287source src/cpu/Kconfig
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000288comment "Northbridge"
289source src/northbridge/Kconfig
290comment "Southbridge"
291source src/southbridge/Kconfig
292comment "Super I/O"
293source src/superio/Kconfig
Sven Schnelle7592e8b2011-01-27 11:43:03 +0000294comment "Embedded Controllers"
295source src/ec/Kconfig
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500296comment "SoC"
297source src/soc/Kconfig
Martin Rotha6427162014-04-25 14:12:13 -0600298source src/drivers/intel/fsp/Kconfig
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000299
300endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000301
Stefan Reinauer8d711552012-11-30 12:34:04 -0800302source src/device/Kconfig
Stefan Reinauer95a63962012-11-13 17:00:01 -0800303
Rudolf Marekd9c25492010-05-16 15:31:53 +0000304menu "Generic Drivers"
305source src/drivers/Kconfig
306endmenu
307
Stefan Reinauer7cb01e02013-08-29 16:05:02 -0700308config TPM
309 bool
310 default n
311 select LPC_TPM if ARCH_X86
Gabe Black51edd542013-09-30 23:00:33 -0700312 select I2C_TPM if ARCH_ARM
Furquan Shaikh2af76f42014-04-28 16:39:40 -0700313 select I2C_TPM if ARCH_ARM64
Stefan Reinauer7cb01e02013-08-29 16:05:02 -0700314 help
315 Enable this option to enable TPM support in coreboot.
316
317 If unsure, say N.
318
Patrick Georgi0588d192009-08-12 15:00:51 +0000319config HEAP_SIZE
320 hex
Myles Watson04000f42009-10-16 19:12:49 +0000321 default 0x4000
Patrick Georgi0588d192009-08-12 15:00:51 +0000322
Patrick Georgi0588d192009-08-12 15:00:51 +0000323config MAX_CPUS
324 int
325 default 1
326
327config MMCONF_SUPPORT_DEFAULT
328 bool
329 default n
330
331config MMCONF_SUPPORT
332 bool
333 default n
334
Kyösti Mälkki5687fc92013-11-28 18:11:49 +0200335config BOOTMODE_STRAPS
336 bool
337 default n
338
Patrick Georgi0588d192009-08-12 15:00:51 +0000339source src/console/Kconfig
340
341config HAVE_ACPI_RESUME
342 bool
343 default n
344
Stefan Reinauerc4f1a772010-06-05 10:03:08 +0000345config HAVE_ACPI_SLIC
346 bool
347 default n
348
Patrick Georgi0588d192009-08-12 15:00:51 +0000349config ACPI_SSDTX_NUM
350 int
351 default 0
352
Patrick Georgi0588d192009-08-12 15:00:51 +0000353config HAVE_HARD_RESET
354 bool
Uwe Hermann748475b2009-10-09 11:47:21 +0000355 default n
Patrick Georgi37bdb872010-02-27 08:39:04 +0000356 help
357 This variable specifies whether a given board has a hard_reset
358 function, no matter if it's provided by board code or chipset code.
359
Aaron Durbina4217912013-04-29 22:31:51 -0500360config HAVE_MONOTONIC_TIMER
361 def_bool n
362 help
363 The board/chipset provides a monotonic timer.
364
Aaron Durbin340ca912013-04-30 09:58:12 -0500365config TIMER_QUEUE
366 def_bool n
367 depends on HAVE_MONOTONIC_TIMER
368 help
Kyösti Mälkkiecd84242013-09-13 07:57:49 +0300369 Provide a timer queue for performing time-based callbacks.
Aaron Durbin340ca912013-04-30 09:58:12 -0500370
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500371config COOP_MULTITASKING
372 def_bool n
Aaron Durbin38c326d2013-05-06 12:22:23 -0500373 depends on TIMER_QUEUE && ARCH_X86
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500374 help
375 Cooperative multitasking allows callbacks to be multiplexed on the
376 main thread of ramstage. With this enabled it allows for multiple
377 execution paths to take place when they have udelay() calls within
378 their code.
379
380config NUM_THREADS
381 int
382 default 4
383 depends on COOP_MULTITASKING
384 help
385 How many execution threads to cooperatively multitask with.
386
Patrick Georgi0588d192009-08-12 15:00:51 +0000387config HAVE_OPTION_TABLE
388 bool
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000389 default n
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000390 help
391 This variable specifies whether a given board has a cmos.layout
392 file containing NVRAM/CMOS bit definitions.
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000393 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
Patrick Georgi0588d192009-08-12 15:00:51 +0000394
Patrick Georgi0588d192009-08-12 15:00:51 +0000395config PIRQ_ROUTE
396 bool
397 default n
398
399config HAVE_SMI_HANDLER
400 bool
401 default n
402
403config PCI_IO_CFG_EXT
404 bool
405 default n
406
407config IOAPIC
408 bool
409 default n
410
Stefan Reinauer5b635792012-08-16 14:05:42 -0700411config CBFS_SIZE
412 hex
413 default ROM_SIZE
414
Kyösti Mälkki107f72e2014-01-06 11:06:26 +0200415config CACHE_ROM_SIZE_OVERRIDE
Stefan Reinauer5b635792012-08-16 14:05:42 -0700416 hex
Kyösti Mälkki107f72e2014-01-06 11:06:26 +0200417 default 0
Stefan Reinauer5b635792012-08-16 14:05:42 -0700418
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000419# TODO: Can probably be removed once all chipsets have kconfig options for it.
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000420config VIDEO_MB
421 int
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000422 default 0
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000423
Myles Watson45bb25f2009-09-22 18:49:08 +0000424config USE_WATCHDOG_ON_BOOT
425 bool
426 default n
427
428config VGA
429 bool
430 default n
431 help
432 Build board-specific VGA code.
433
434config GFXUMA
435 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000436 default n
Myles Watson45bb25f2009-09-22 18:49:08 +0000437 help
438 Enable Unified Memory Architecture for graphics.
439
Myles Watsonb8e20272009-10-15 13:35:47 +0000440config HAVE_ACPI_TABLES
441 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000442 help
443 This variable specifies whether a given board has ACPI table support.
444 It is usually set in mainboard/*/Kconfig.
Myles Watsonb8e20272009-10-15 13:35:47 +0000445
446config HAVE_MP_TABLE
447 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000448 help
449 This variable specifies whether a given board has MP table support.
450 It is usually set in mainboard/*/Kconfig.
451 Whether or not the MP table is actually generated by coreboot
452 is configurable by the user via GENERATE_MP_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000453
454config HAVE_PIRQ_TABLE
455 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000456 help
457 This variable specifies whether a given board has PIRQ table support.
458 It is usually set in mainboard/*/Kconfig.
459 Whether or not the PIRQ table is actually generated by coreboot
460 is configurable by the user via GENERATE_PIRQ_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000461
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -0500462config MAX_PIRQ_LINKS
463 int
464 default 4
465 help
466 This variable specifies the number of PIRQ interrupt links which are
467 routable. On most chipsets, this is 4, INTA through INTD. Some
468 chipsets offer more than four links, commonly up to INTH. They may
469 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
470 table specifies links greater than 4, pirq_route_irqs will not
471 function properly, unless this variable is correctly set.
472
Vladimir Serbinenko2d7bd8a2014-08-30 19:28:05 +0200473config PER_DEVICE_ACPI_TABLES
474 bool
475 default n
476
Myles Watsond73c1b52009-10-26 15:14:07 +0000477#These Options are here to avoid "undefined" warnings.
478#The actual selection and help texts are in the following menu.
479
Uwe Hermann168b11b2009-10-07 16:15:40 +0000480menu "System tables"
Myles Watson45bb25f2009-09-22 18:49:08 +0000481
Myles Watsonb8e20272009-10-15 13:35:47 +0000482config GENERATE_MP_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800483 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
484 bool
485 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000486 help
487 Generate an MP table (conforming to the Intel MultiProcessor
488 specification 1.4) for this board.
489
490 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000491
Myles Watsonb8e20272009-10-15 13:35:47 +0000492config GENERATE_PIRQ_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800493 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
494 bool
495 default HAVE_PIRQ_TABLE
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000496 help
497 Generate a PIRQ table for this board.
498
499 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000500
Sven Schnelle164bcfd2011-08-14 20:56:34 +0200501config GENERATE_SMBIOS_TABLES
502 depends on ARCH_X86
503 bool "Generate SMBIOS tables"
504 default y
505 help
506 Generate SMBIOS tables for this board.
507
508 If unsure, say Y.
509
Myles Watson45bb25f2009-09-22 18:49:08 +0000510endmenu
511
Patrick Georgi0588d192009-08-12 15:00:51 +0000512menu "Payload"
513
Patrick Georgi0588d192009-08-12 15:00:51 +0000514choice
Uwe Hermann168b11b2009-10-07 16:15:40 +0000515 prompt "Add a payload"
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000516 default PAYLOAD_NONE if !ARCH_X86
517 default PAYLOAD_SEABIOS if ARCH_X86
Patrick Georgi0588d192009-08-12 15:00:51 +0000518
Uwe Hermann168b11b2009-10-07 16:15:40 +0000519config PAYLOAD_NONE
520 bool "None"
521 help
522 Select this option if you want to create an "empty" coreboot
523 ROM image for a certain mainboard, i.e. a coreboot ROM image
524 which does not yet contain a payload.
525
526 For such an image to be useful, you have to use 'cbfstool'
527 to add a payload to the ROM image later.
528
Patrick Georgi0588d192009-08-12 15:00:51 +0000529config PAYLOAD_ELF
Uwe Hermann168b11b2009-10-07 16:15:40 +0000530 bool "An ELF executable payload"
Patrick Georgi0588d192009-08-12 15:00:51 +0000531 help
532 Select this option if you have a payload image (an ELF file)
533 which coreboot should run as soon as the basic hardware
534 initialization is completed.
535
536 You will be able to specify the location and file name of the
537 payload image later.
Patrick Georgi0588d192009-08-12 15:00:51 +0000538
Patrick Georgi16ae95c2013-08-31 08:26:52 +0200539config PAYLOAD_LINUX
540 bool "A Linux payload"
541 help
542 Select this option if you have a Linux bzImage which coreboot
543 should run as soon as the basic hardware initialization
544 is completed.
545
546 You will be able to specify the location and file name of the
547 payload image later.
548
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000549config PAYLOAD_SEABIOS
550 bool "SeaBIOS"
551 depends on ARCH_X86
552 help
553 Select this option if you want to build a coreboot image
554 with a SeaBIOS payload. If you don't know what this is
555 about, just leave it enabled.
556
557 See http://coreboot.org/Payloads for more information.
558
Stefan Reinauere50952f2011-04-15 03:34:05 +0000559config PAYLOAD_FILO
560 bool "FILO"
561 help
562 Select this option if you want to build a coreboot image
563 with a FILO payload. If you don't know what this is
564 about, just leave it enabled.
565
566 See http://coreboot.org/Payloads for more information.
567
Vladimir Serbinenko113a3662013-11-14 12:10:08 +0100568config PAYLOAD_GRUB2
569 bool "GRUB2"
570 help
571 Select this option if you want to build a coreboot image
572 with a GRUB2 payload. If you don't know what this is
573 about, just leave it enabled.
574
575 See http://coreboot.org/Payloads for more information.
576
Stefan Reinauercc5b3442013-01-15 17:02:58 -0800577config PAYLOAD_TIANOCORE
578 bool "Tiano Core"
579 help
580 Select this option if you want to build a coreboot image
581 with a Tiano Core payload. If you don't know what this is
582 about, just leave it enabled.
583
584 See http://coreboot.org/Payloads for more information.
585
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000586endchoice
587
588choice
589 prompt "SeaBIOS version"
590 default SEABIOS_STABLE
591 depends on PAYLOAD_SEABIOS
592
593config SEABIOS_STABLE
Edward O'Callaghanaca67ed2014-09-13 20:43:45 +1000594 bool "1.7.5"
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000595 help
596 Stable SeaBIOS version
597config SEABIOS_MASTER
598 bool "master"
599 help
600 Newest SeaBIOS version
Daniele Forsi53847a22014-07-22 18:00:56 +0200601
Patrick Georgi0588d192009-08-12 15:00:51 +0000602endchoice
603
Peter Stugef0408582013-07-09 19:43:09 +0200604config SEABIOS_PS2_TIMEOUT
605 prompt "PS/2 keyboard controller initialization timeout (milliseconds)" if PAYLOAD_SEABIOS
Patrick Georgi1e44c3f2013-08-16 10:14:38 +0200606 default 0
Peter Stugef0408582013-07-09 19:43:09 +0200607 depends on EXPERT
608 int
609 help
610 Some PS/2 keyboard controllers don't respond to commands immediately
611 after powering on. This specifies how long SeaBIOS will wait for the
612 keyboard controller to become ready before giving up.
613
Idwer Vollering7c1a49b2014-04-01 22:47:33 +0000614config SEABIOS_THREAD_OPTIONROMS
615 prompt "Hardware init during option ROM execution" if PAYLOAD_SEABIOS
616 default n
617 bool
618 help
619 Allow hardware init to run in parallel with optionrom execution.
620
621 This can reduce boot time, but can cause some timing
622 variations during option ROM code execution. It is not
623 known if all option ROMs will behave properly with this option.
624
Martin Roth4d7d25f2014-07-25 14:39:05 -0600625config SEABIOS_MALLOC_UPPERMEMORY
626 bool
627 default y
628 depends on PAYLOAD_SEABIOS
629 help
630 Use the "Upper Memory Block" area (0xc0000-0xf0000) for internal
631 "low memory" allocations. If this is not selected, the memory is
632 instead allocated from the "9-segment" (0x90000-0xa0000).
633 This is not typically needed, but may be required on some platforms
634 to allow USB and SATA buffers to be written correctly by the
635 hardware. In general, if this is desired, the option will be
636 set to 'N' by the chipset Kconfig.
637
Edward O'Callaghana296f9e2014-09-13 03:43:49 +1000638config SEABIOS_VGA_COREBOOT
639 prompt "Include generated option rom that implements legacy VGA BIOS compatibility" if PAYLOAD_SEABIOS
640 default n
641 depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT
642 bool
643 help
644 Coreboot can initialize the GPU of some mainboards.
645
646 After initializing the GPU, the information about it can be passed to the payload.
647 Provide an option rom that implements this legacy VGA BIOS compatibility requirement.
648
Stefan Reinauere50952f2011-04-15 03:34:05 +0000649choice
Vladimir Serbinenko113a3662013-11-14 12:10:08 +0100650 prompt "GRUB2 version"
651 default GRUB2_MASTER
652 depends on PAYLOAD_GRUB2
653
654config GRUB2_MASTER
655 bool "HEAD"
656 help
657 Newest GRUB2 version
Daniele Forsi53847a22014-07-22 18:00:56 +0200658
Vladimir Serbinenko113a3662013-11-14 12:10:08 +0100659endchoice
660
661choice
Stefan Reinauere50952f2011-04-15 03:34:05 +0000662 prompt "FILO version"
663 default FILO_STABLE
664 depends on PAYLOAD_FILO
665
666config FILO_STABLE
667 bool "0.6.0"
668 help
669 Stable FILO version
Daniele Forsi53847a22014-07-22 18:00:56 +0200670
Stefan Reinauere50952f2011-04-15 03:34:05 +0000671config FILO_MASTER
672 bool "HEAD"
673 help
674 Newest FILO version
Daniele Forsi53847a22014-07-22 18:00:56 +0200675
Stefan Reinauere50952f2011-04-15 03:34:05 +0000676endchoice
677
Stefan Reinauerbccbbe62010-12-19 21:20:14 +0000678config PAYLOAD_FILE
Cristi Magherusanb5034d42009-08-17 14:47:32 +0000679 string "Payload path and filename"
Patrick Georgi0588d192009-08-12 15:00:51 +0000680 depends on PAYLOAD_ELF
681 default "payload.elf"
682 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000683 The path and filename of the ELF executable file to use as payload.
Patrick Georgi0588d192009-08-12 15:00:51 +0000684
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000685config PAYLOAD_FILE
Patrick Georgi16ae95c2013-08-31 08:26:52 +0200686 string "Linux path and filename"
687 depends on PAYLOAD_LINUX
688 default "bzImage"
689 help
690 The path and filename of the bzImage kernel to use as payload.
691
692config PAYLOAD_FILE
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000693 depends on PAYLOAD_SEABIOS
Idwer Volleringab11a6a92014-08-11 16:09:07 +0200694 default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000695
Edward O'Callaghana296f9e2014-09-13 03:43:49 +1000696config PAYLOAD_VGABIOS_FILE
697 string
698 depends on PAYLOAD_SEABIOS && SEABIOS_VGA_COREBOOT
699 default "payloads/external/SeaBIOS/seabios/out/vgabios.bin"
700
Stefan Reinauere50952f2011-04-15 03:34:05 +0000701config PAYLOAD_FILE
702 depends on PAYLOAD_FILO
703 default "payloads/external/FILO/filo/build/filo.elf"
704
Stefan Reinauer275fb632013-02-05 13:58:29 -0800705config PAYLOAD_FILE
Vladimir Serbinenko113a3662013-11-14 12:10:08 +0100706 depends on PAYLOAD_GRUB2
707 default "payloads/external/GRUB2/grub2/build/default_payload.elf"
708
709config PAYLOAD_FILE
Stefan Reinauer275fb632013-02-05 13:58:29 -0800710 string "Tianocore firmware volume"
711 depends on PAYLOAD_TIANOCORE
712 default "COREBOOT.fd"
713 help
714 The result of a corebootPkg build
715
Uwe Hermann168b11b2009-10-07 16:15:40 +0000716# TODO: Defined if no payload? Breaks build?
717config COMPRESSED_PAYLOAD_LZMA
718 bool "Use LZMA compression for payloads"
719 default y
Vladimir Serbinenko113a3662013-11-14 12:10:08 +0100720 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO || PAYLOAD_TIANOCORE || PAYLOAD_GRUB2
Uwe Hermann168b11b2009-10-07 16:15:40 +0000721 help
722 In order to reduce the size payloads take up in the ROM chip
723 coreboot can compress them using the LZMA algorithm.
724
Patrick Georgi16ae95c2013-08-31 08:26:52 +0200725config LINUX_COMMAND_LINE
726 string "Linux command line"
727 depends on PAYLOAD_LINUX
728 default ""
729 help
730 A command line to add to the Linux kernel.
731
732config LINUX_INITRD
733 string "Linux initrd"
734 depends on PAYLOAD_LINUX
735 default ""
736 help
737 An initrd image to add to the Linux kernel.
738
Peter Stugea758ca22009-09-17 16:21:31 +0000739endmenu
740
Uwe Hermann168b11b2009-10-07 16:15:40 +0000741menu "Debugging"
742
743# TODO: Better help text and detailed instructions.
Patrick Georgi0588d192009-08-12 15:00:51 +0000744config GDB_STUB
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000745 bool "GDB debugging support"
Rudolf Marek65888022012-03-25 20:51:16 +0200746 default n
Patrick Georgi0588d192009-08-12 15:00:51 +0000747 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000748 If enabled, you will be able to set breakpoints for gdb debugging.
Stefan Reinauer8677a232010-12-11 20:33:41 +0000749 See src/arch/x86/lib/c_start.S for details.
Patrick Georgi0588d192009-08-12 15:00:51 +0000750
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200751config GDB_WAIT
752 bool "Wait for a GDB connection"
753 default n
754 depends on GDB_STUB
755 help
756 If enabled, coreboot will wait for a GDB connection.
757
Stefan Reinauerfe422182012-05-02 16:33:18 -0700758config DEBUG_CBFS
759 bool "Output verbose CBFS debug messages"
760 default n
Stefan Reinauerfe422182012-05-02 16:33:18 -0700761 help
762 This option enables additional CBFS related debug messages.
763
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000764config HAVE_DEBUG_RAM_SETUP
765 def_bool n
766
Uwe Hermann01ce6012010-03-05 10:03:50 +0000767config DEBUG_RAM_SETUP
768 bool "Output verbose RAM init debug messages"
769 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000770 depends on HAVE_DEBUG_RAM_SETUP
Uwe Hermann01ce6012010-03-05 10:03:50 +0000771 help
772 This option enables additional RAM init related debug messages.
773 It is recommended to enable this when debugging issues on your
774 board which might be RAM init related.
775
776 Note: This option will increase the size of the coreboot image.
777
778 If unsure, say N.
779
Patrick Georgie82618d2010-10-01 14:50:12 +0000780config HAVE_DEBUG_CAR
781 def_bool n
782
Peter Stuge5015f792010-11-10 02:00:32 +0000783config DEBUG_CAR
784 def_bool n
785 depends on HAVE_DEBUG_CAR
786
787if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
Uwe Hermanna953f372010-11-10 00:14:32 +0000788# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
789# printk(BIOS_DEBUG, ...) calls.
Patrick Georgie82618d2010-10-01 14:50:12 +0000790config DEBUG_CAR
791 bool "Output verbose Cache-as-RAM debug messages"
792 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000793 depends on HAVE_DEBUG_CAR
Patrick Georgie82618d2010-10-01 14:50:12 +0000794 help
795 This option enables additional CAR related debug messages.
Peter Stuge5015f792010-11-10 02:00:32 +0000796endif
Patrick Georgie82618d2010-10-01 14:50:12 +0000797
Myles Watson80e914ff2010-06-01 19:25:31 +0000798config DEBUG_PIRQ
799 bool "Check PIRQ table consistency"
800 default n
801 depends on GENERATE_PIRQ_TABLE
802 help
803 If unsure, say N.
804
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000805config HAVE_DEBUG_SMBUS
806 def_bool n
807
Uwe Hermann01ce6012010-03-05 10:03:50 +0000808config DEBUG_SMBUS
809 bool "Output verbose SMBus debug messages"
810 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000811 depends on HAVE_DEBUG_SMBUS
Uwe Hermann01ce6012010-03-05 10:03:50 +0000812 help
813 This option enables additional SMBus (and SPD) debug messages.
814
815 Note: This option will increase the size of the coreboot image.
816
817 If unsure, say N.
818
819config DEBUG_SMI
820 bool "Output verbose SMI debug messages"
821 default n
822 depends on HAVE_SMI_HANDLER
823 help
824 This option enables additional SMI related debug messages.
825
826 Note: This option will increase the size of the coreboot image.
827
828 If unsure, say N.
829
Stefan Reinauerbc0f7a62010-08-01 15:41:14 +0000830config DEBUG_SMM_RELOCATION
831 bool "Debug SMM relocation code"
832 default n
833 depends on HAVE_SMI_HANDLER
834 help
835 This option enables additional SMM handler relocation related
836 debug messages.
837
838 Note: This option will increase the size of the coreboot image.
839
840 If unsure, say N.
841
Uwe Hermanna953f372010-11-10 00:14:32 +0000842# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
843# printk(BIOS_DEBUG, ...) calls.
844config DEBUG_MALLOC
Stefan Reinauer95a63962012-11-13 17:00:01 -0800845 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
846 bool
Uwe Hermanna953f372010-11-10 00:14:32 +0000847 default n
Uwe Hermanna953f372010-11-10 00:14:32 +0000848 help
849 This option enables additional malloc related debug messages.
850
851 Note: This option will increase the size of the coreboot image.
852
853 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300854
855# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
856# printk(BIOS_DEBUG, ...) calls.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300857config DEBUG_ACPI
Stefan Reinauer95a63962012-11-13 17:00:01 -0800858 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
859 bool
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300860 default n
861 help
862 This option enables additional ACPI related debug messages.
863
864 Note: This option will slightly increase the size of the coreboot image.
865
866 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300867
Uwe Hermanna953f372010-11-10 00:14:32 +0000868# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
869# printk(BIOS_DEBUG, ...) calls.
Myles Watson6c9bc012010-09-07 22:30:15 +0000870config REALMODE_DEBUG
Stefan Reinauer95a63962012-11-13 17:00:01 -0800871 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
872 bool
Myles Watson6c9bc012010-09-07 22:30:15 +0000873 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000874 depends on PCI_OPTION_ROM_RUN_REALMODE
Myles Watson6c9bc012010-09-07 22:30:15 +0000875 help
876 This option enables additional x86emu related debug messages.
877
878 Note: This option will increase the time to emulate a ROM.
879
880 If unsure, say N.
881
Uwe Hermann01ce6012010-03-05 10:03:50 +0000882config X86EMU_DEBUG
883 bool "Output verbose x86emu debug messages"
884 default n
885 depends on PCI_OPTION_ROM_RUN_YABEL
886 help
887 This option enables additional x86emu related debug messages.
888
889 Note: This option will increase the size of the coreboot image.
890
891 If unsure, say N.
892
893config X86EMU_DEBUG_JMP
894 bool "Trace JMP/RETF"
895 default n
896 depends on X86EMU_DEBUG
897 help
898 Print information about JMP and RETF opcodes from x86emu.
899
900 Note: This option will increase the size of the coreboot image.
901
902 If unsure, say N.
903
904config X86EMU_DEBUG_TRACE
905 bool "Trace all opcodes"
906 default n
907 depends on X86EMU_DEBUG
908 help
909 Print _all_ opcodes that are executed by x86emu.
Stefan Reinauer14e22772010-04-27 06:56:47 +0000910
Uwe Hermann01ce6012010-03-05 10:03:50 +0000911 WARNING: This will produce a LOT of output and take a long time.
912
913 Note: This option will increase the size of the coreboot image.
914
915 If unsure, say N.
916
917config X86EMU_DEBUG_PNP
918 bool "Log Plug&Play accesses"
919 default n
920 depends on X86EMU_DEBUG
921 help
922 Print Plug And Play accesses made by option ROMs.
923
924 Note: This option will increase the size of the coreboot image.
925
926 If unsure, say N.
927
928config X86EMU_DEBUG_DISK
929 bool "Log Disk I/O"
930 default n
931 depends on X86EMU_DEBUG
932 help
933 Print Disk I/O related messages.
934
935 Note: This option will increase the size of the coreboot image.
936
937 If unsure, say N.
938
939config X86EMU_DEBUG_PMM
940 bool "Log PMM"
941 default n
942 depends on X86EMU_DEBUG
943 help
944 Print messages related to POST Memory Manager (PMM).
945
946 Note: This option will increase the size of the coreboot image.
947
948 If unsure, say N.
949
950
951config X86EMU_DEBUG_VBE
952 bool "Debug VESA BIOS Extensions"
953 default n
954 depends on X86EMU_DEBUG
955 help
956 Print messages related to VESA BIOS Extension (VBE) functions.
957
958 Note: This option will increase the size of the coreboot image.
959
960 If unsure, say N.
961
962config X86EMU_DEBUG_INT10
963 bool "Redirect INT10 output to console"
964 default n
965 depends on X86EMU_DEBUG
966 help
967 Let INT10 (i.e. character output) calls print messages to debug output.
968
969 Note: This option will increase the size of the coreboot image.
970
971 If unsure, say N.
972
973config X86EMU_DEBUG_INTERRUPTS
974 bool "Log intXX calls"
975 default n
976 depends on X86EMU_DEBUG
977 help
978 Print messages related to interrupt handling.
979
980 Note: This option will increase the size of the coreboot image.
981
982 If unsure, say N.
983
984config X86EMU_DEBUG_CHECK_VMEM_ACCESS
985 bool "Log special memory accesses"
986 default n
987 depends on X86EMU_DEBUG
988 help
989 Print messages related to accesses to certain areas of the virtual
990 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
991
992 Note: This option will increase the size of the coreboot image.
993
994 If unsure, say N.
995
996config X86EMU_DEBUG_MEM
997 bool "Log all memory accesses"
998 default n
999 depends on X86EMU_DEBUG
1000 help
1001 Print memory accesses made by option ROM.
1002 Note: This also includes accesses to fetch instructions.
1003
1004 Note: This option will increase the size of the coreboot image.
1005
1006 If unsure, say N.
1007
1008config X86EMU_DEBUG_IO
1009 bool "Log IO accesses"
1010 default n
1011 depends on X86EMU_DEBUG
1012 help
1013 Print I/O accesses made by option ROM.
1014
1015 Note: This option will increase the size of the coreboot image.
1016
1017 If unsure, say N.
1018
Denis 'GNUtoo' Carikli4cdc5d62013-05-15 00:19:49 +02001019config X86EMU_DEBUG_TIMINGS
1020 bool "Output timing information"
1021 default n
1022 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
1023 help
1024 Print timing information needed by i915tool.
1025
1026 If unsure, say N.
1027
Stefan Reinauerdfb098d2011-11-17 12:50:54 -08001028config DEBUG_TPM
1029 bool "Output verbose TPM debug messages"
1030 default n
1031 depends on TPM
1032 help
1033 This option enables additional TPM related debug messages.
1034
Stefan Reinauer1c56d9b2012-05-10 11:27:32 -07001035config DEBUG_SPI_FLASH
1036 bool "Output verbose SPI flash debug messages"
1037 default n
1038 depends on SPI_FLASH
1039 help
1040 This option enables additional SPI flash related debug messages.
1041
Kyösti Mälkki3be80cc2013-06-06 10:46:37 +03001042config DEBUG_USBDEBUG
1043 bool "Output verbose USB 2.0 EHCI debug dongle messages"
1044 default n
1045 depends on USBDEBUG
1046 help
1047 This option enables additional USB 2.0 debug dongle related messages.
1048
1049 Select this to debug the connection of usbdebug dongle. Note that
1050 you need some other working console to receive the messages.
1051
Stefan Reinauer8e073822012-04-04 00:07:22 +02001052if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1053# Only visible with the right southbridge and loglevel.
1054config DEBUG_INTEL_ME
1055 bool "Verbose logging for Intel Management Engine"
1056 default n
1057 help
1058 Enable verbose logging for Intel Management Engine driver that
1059 is present on Intel 6-series chipsets.
1060endif
1061
Rudolf Marek7f0e9302011-09-02 23:23:41 +02001062config TRACE
1063 bool "Trace function calls"
1064 default n
1065 help
1066 If enabled, every function will print information to console once
1067 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1068 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1069 of calling function. Please note some printk releated functions
1070 are omitted from trace to have good looking console dumps.
Stefan Reinauerd37ab452012-12-18 16:23:28 -08001071
1072config DEBUG_COVERAGE
1073 bool "Debug code coverage"
1074 default n
1075 depends on COVERAGE
1076 help
1077 If enabled, the code coverage hooks in coreboot will output some
1078 information about the coverage data that is dumped.
1079
Uwe Hermann168b11b2009-10-07 16:15:40 +00001080endmenu
1081
Myles Watsond73c1b52009-10-26 15:14:07 +00001082# These probably belong somewhere else, but they are needed somewhere.
Myles Watsond73c1b52009-10-26 15:14:07 +00001083config ENABLE_APIC_EXT_ID
1084 bool
1085 default n
Myles Watson2e672732009-11-12 16:38:03 +00001086
1087config WARNINGS_ARE_ERRORS
1088 bool
Stefan Reinauer6f57b512010-07-08 16:41:05 +00001089 default y
Patrick Georgi436f99b2009-11-27 16:55:13 +00001090
Peter Stuge51eafde2010-10-13 06:23:02 +00001091# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1092# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1093# mutually exclusive. One of these options must be selected in the
1094# mainboard Kconfig if the chipset supports enabling and disabling of
1095# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1096# in mainboard/Kconfig to know if the button should be enabled or not.
1097
1098config POWER_BUTTON_DEFAULT_ENABLE
1099 def_bool n
1100 help
1101 Select when the board has a power button which can optionally be
1102 disabled by the user.
1103
1104config POWER_BUTTON_DEFAULT_DISABLE
1105 def_bool n
1106 help
1107 Select when the board has a power button which can optionally be
1108 enabled by the user, e.g. when the board ships with a jumper over
1109 the power switch contacts.
1110
1111config POWER_BUTTON_FORCE_ENABLE
1112 def_bool n
1113 help
1114 Select when the board requires that the power button is always
1115 enabled.
1116
1117config POWER_BUTTON_FORCE_DISABLE
1118 def_bool n
1119 help
1120 Select when the board requires that the power button is always
1121 disabled, e.g. when it has been hardwired to ground.
1122
1123config POWER_BUTTON_IS_OPTIONAL
1124 bool
1125 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1126 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1127 help
1128 Internal option that controls ENABLE_POWER_BUTTON visibility.
Duncan Laurie72748002013-10-31 08:26:23 -07001129
1130config REG_SCRIPT
1131 bool
1132 default y if ARCH_X86
1133 default n
1134 help
1135 Internal option that controls whether we compile in register scripts.
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001136
1137# Maximum reboot count
1138# TODO: Improve description.
1139config MAX_REBOOT_CNT
1140 int
1141 default 3