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Subrata Banikb3ced6a2020-08-04 13:34:03 +05301config SOC_INTEL_ALDERLAKE
2 bool
3 help
Angel Ponsdb925aa2021-12-01 11:44:09 +01004 Intel Alderlake support. Mainboards should specify the PCH
5 type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead
6 of selecting this option directly.
Subrata Banikb3ced6a2020-08-04 13:34:03 +05307
Varshit Pandyab5df56f2021-01-18 09:44:35 +05308config SOC_INTEL_ALDERLAKE_PCH_M
9 bool
Angel Ponsdb925aa2021-12-01 11:44:09 +010010 select SOC_INTEL_ALDERLAKE
Varshit Pandyab5df56f2021-01-18 09:44:35 +053011 help
Angel Ponsdb925aa2021-12-01 11:44:09 +010012 Choose this option if your mainboard has a PCH-M chipset.
13
Usha P78c9b672021-11-30 11:27:38 +053014config SOC_INTEL_ALDERLAKE_PCH_N
15 bool
16 select SOC_INTEL_ALDERLAKE
17 help
18 Choose this option if your mainboard has a PCH-N chipset.
19
Angel Ponsdb925aa2021-12-01 11:44:09 +010020config SOC_INTEL_ALDERLAKE_PCH_P
21 bool
22 select SOC_INTEL_ALDERLAKE
23 help
24 Choose this option if your mainboard has a PCH-P chipset.
Varshit Pandyab5df56f2021-01-18 09:44:35 +053025
Michał Żygowskia1636d72022-04-07 14:56:10 +020026config SOC_INTEL_ALDERLAKE_PCH_S
27 bool
28 select SOC_INTEL_ALDERLAKE
29 help
30 Choose this option if your mainboard has a PCH-S chipset.
31
Subrata Banikb3ced6a2020-08-04 13:34:03 +053032if SOC_INTEL_ALDERLAKE
33
34config CPU_SPECIFIC_OPTIONS
35 def_bool y
Angel Ponsa25eaff2020-09-23 15:37:15 +020036 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Sugnan Prabhu Sdcf04592021-12-03 19:07:04 +053037 select ACPI_ADL_IPU_ES_SUPPORT
Angel Pons8e035e32021-06-22 12:58:20 +020038 select ARCH_X86
Subrata Banikb3ced6a2020-08-04 13:34:03 +053039 select BOOT_DEVICE_SUPPORTS_WRITES
Subrata Banik292afef2020-09-09 13:34:18 +053040 select CACHE_MRC_SETTINGS
41 select CPU_INTEL_COMMON
Subrata Banik2871e0e2020-09-27 11:30:58 +053042 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
Michael Niewöhner5307f122021-09-19 00:32:37 +020043 select CPU_SUPPORTS_INTEL_TME
Michael Niewöhnerfe6070f2020-10-04 15:16:04 +020044 select CPU_SUPPORTS_PM_TIMER_EMULATION
Subrata Banik34f26b22022-02-10 12:38:02 +053045 select DISPLAY_FSP_VERSION_INFO
Eric Lai4ea47c32020-12-21 16:57:49 +080046 select DRIVERS_USB_ACPI
Subrata Banik2871e0e2020-09-27 11:30:58 +053047 select FSP_COMPRESS_FSP_S_LZ4
Subrata Banik683c95e2020-12-19 19:36:45 +053048 select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
Subrata Banik292afef2020-09-09 13:34:18 +053049 select FSP_M_XIP
Subrata Banik4ed9f9a2020-10-31 22:01:55 +053050 select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
Subrata Banike4cf3fa2022-03-23 01:41:36 +053051 select FSP_USES_CB_DEBUG_EVENT_HANDLER
Subrata Banik298b3592021-09-14 12:38:08 +053052 select FSPS_HAS_ARCH_UPD
Subrata Banik2871e0e2020-09-27 11:30:58 +053053 select GENERIC_GPIO_LIB
Subrata Banikb4a169a2021-12-29 18:36:23 +000054 select HAVE_DEBUG_RAM_SETUP
Subrata Banik2871e0e2020-09-27 11:30:58 +053055 select HAVE_FSP_GOP
Subrata Banikb3ced6a2020-08-04 13:34:03 +053056 select INTEL_DESCRIPTOR_MODE_CAPABLE
Subrata Banik2871e0e2020-09-27 11:30:58 +053057 select HAVE_SMI_HANDLER
Subrata Banikb3ced6a2020-08-04 13:34:03 +053058 select IDT_IN_EVERY_STAGE
Subrata Banik2871e0e2020-09-27 11:30:58 +053059 select INTEL_GMA_ACPI
60 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
Meera Ravindranath81d367f2021-07-08 09:39:11 +053061 select INTEL_GMA_OPREGION_2_1
Subrata Banik0aed4e52020-10-12 17:27:31 +053062 select INTEL_TME
Aamir Bohra30cca6c2021-02-04 20:57:51 +053063 select MP_SERVICES_PPI_V2
Subrata Banik292afef2020-09-09 13:34:18 +053064 select MRC_SETTINGS_PROTECT
Subrata Banik2871e0e2020-09-27 11:30:58 +053065 select PARALLEL_MP_AP_WORK
Subrata Banikb3ced6a2020-08-04 13:34:03 +053066 select MICROCODE_BLOB_UNDISCLOSED
Michał Żygowski02315f92022-04-07 14:58:11 +020067 select PLATFORM_USES_FSP2_2 if !SOC_INTEL_ALDERLAKE_PCH_S
68 select PLATFORM_USES_FSP2_3 if SOC_INTEL_ALDERLAKE_PCH_S
Subrata Banik2871e0e2020-09-27 11:30:58 +053069 select PMC_GLOBAL_RESET_ENABLE_LOCK
Subrata Banikb3ced6a2020-08-04 13:34:03 +053070 select SOC_INTEL_COMMON
Subrata Banik08089922020-10-03 13:02:06 +053071 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
Subrata Banikb3ced6a2020-08-04 13:34:03 +053072 select SOC_INTEL_COMMON_BLOCK
Subrata Banik08089922020-10-03 13:02:06 +053073 select SOC_INTEL_COMMON_BLOCK_ACPI
ravindr174596572021-03-29 19:41:25 +053074 select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
Sridahr Siricilla73b90c62021-11-11 01:10:16 +053075 select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID
Angel Pons98f672a2021-02-19 19:42:10 +010076 select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
Tim Wawrzynczak5faee2e2021-07-01 08:24:18 -060077 select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
78 select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ
Subrata Banik21974ab2020-10-31 21:40:43 +053079 select SOC_INTEL_COMMON_BLOCK_CAR
Subrata Banik292afef2020-09-09 13:34:18 +053080 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
Varshit B Pandya2938c462022-02-16 20:38:10 +053081 select SOC_INTEL_COMMON_BLOCK_CNVI
Subrata Banikb3ced6a2020-08-04 13:34:03 +053082 select SOC_INTEL_COMMON_BLOCK_CPU
Subrata Banik2871e0e2020-09-27 11:30:58 +053083 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
Angel Ponsa4cd9112021-02-19 19:23:38 +010084 select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
Subrata Banik2871e0e2020-09-27 11:30:58 +053085 select SOC_INTEL_COMMON_BLOCK_DTT
86 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
Subrata Banikaf2f8b92022-01-10 10:26:52 +000087 select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI
Subrata Banikb3ced6a2020-08-04 13:34:03 +053088 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
Krishna Prasad Bhat01e426d2022-01-16 22:37:21 +053089 select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N
Subrata Banik2871e0e2020-09-27 11:30:58 +053090 select SOC_INTEL_COMMON_BLOCK_HDA
Subrata Banik5a49f3a2022-01-28 23:49:31 +053091 select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT
Tim Wawrzynczak0c057c22021-03-04 10:56:28 -070092 select SOC_INTEL_COMMON_BLOCK_IPU
Tim Wawrzynczak43607e42021-05-18 09:04:42 -060093 select SOC_INTEL_COMMON_BLOCK_IRQ
Furquan Shaikha1c247b2020-12-31 22:50:14 -080094 select SOC_INTEL_COMMON_BLOCK_MEMINIT
Rizwan Qureshi307be992021-04-08 20:35:29 +053095 select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
Lean Sheng Tan75020002021-06-30 01:47:48 -070096 select SOC_INTEL_COMMON_BLOCK_PMC_EPOC
Sumeet R Pawnikar77298c62021-03-10 21:09:37 +053097 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
Subrata Banikb3ced6a2020-08-04 13:34:03 +053098 select SOC_INTEL_COMMON_BLOCK_SA
Subrata Banik2871e0e2020-09-27 11:30:58 +053099 select SOC_INTEL_COMMON_BLOCK_SMM
100 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
Subrata Banik8407c342021-09-08 20:15:36 +0530101 select SOC_INTEL_COMMON_BLOCK_TCSS
Subrata Banikb2e8bd82021-11-17 15:35:05 +0530102 select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC
Eric Lai4ea47c32020-12-21 16:57:49 +0800103 select SOC_INTEL_COMMON_BLOCK_USB4
104 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
105 select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
Tim Wawrzynczak242da792020-11-10 10:13:54 -0700106 select SOC_INTEL_COMMON_BLOCK_XHCI
107 select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
Sridhar Siricillaf5e94b62022-03-08 23:39:20 +0530108 select SOC_INTEL_COMMON_BASECODE
Subrata Banik4ed9f9a2020-10-31 22:01:55 +0530109 select SOC_INTEL_COMMON_FSP_RESET
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530110 select SOC_INTEL_COMMON_PCH_BASE
111 select SOC_INTEL_COMMON_RESET
MAULIK V VAGHELAed6f7e42022-02-22 19:59:42 +0530112 select SOC_INTEL_CSE_SEND_EOP_EARLY
Tim Wawrzynczakc0e82e72021-06-17 12:42:35 -0600113 select SOC_INTEL_CSE_SET_EOP
Subrata Banikaf27ac22022-02-18 00:44:15 +0530114 select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530115 select SSE2
116 select SUPPORT_CPU_UCODE_IN_CBFS
117 select TSC_MONOTONIC_TIMER
118 select UDELAY_TSC
Subrata Banikee735942020-09-07 17:52:23 +0530119 select UDK_202005_BINDING
Subrata Banik34f26b22022-02-10 12:38:02 +0530120 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
Subrata Banik2871e0e2020-09-27 11:30:58 +0530121
Reka Normane790f922022-04-06 20:33:54 +1000122config ALDERLAKE_CONFIGURE_DESCRIPTOR
123 bool
124 help
125 Select this if the descriptor needs to be updated at runtime. This
126 can only be done if the descriptor region is writable, and should only
127 be used as a temporary workaround.
128
Subrata Banik095e2a72021-07-05 20:56:15 +0530129config ALDERLAKE_CAR_ENHANCED_NEM
130 bool
131 default y if !INTEL_CAR_NEM
132 select INTEL_CAR_NEM_ENHANCED
133 select CAR_HAS_SF_MASKS
134 select COS_MAPPED_TO_MSB
135 select CAR_HAS_L3_PROTECTED_WAYS
136
Subrata Banik2871e0e2020-09-27 11:30:58 +0530137config MAX_CPUS
138 int
139 default 24
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530140
141config DCACHE_RAM_BASE
142 default 0xfef00000
143
144config DCACHE_RAM_SIZE
Subrata Banik191bd822020-11-21 19:30:57 +0530145 default 0xc0000
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530146 help
147 The size of the cache-as-ram region required during bootblock
148 and/or romstage.
149
150config DCACHE_BSP_STACK_SIZE
151 hex
Subrata Banik191bd822020-11-21 19:30:57 +0530152 default 0x80400
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530153 help
154 The amount of anticipated stack usage in CAR by bootblock and
155 other stages. In the case of FSP_USES_CB_STACK default value will be
Subrata Banik191bd822020-11-21 19:30:57 +0530156 sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530157 (~1KiB).
158
159config FSP_TEMP_RAM_SIZE
160 hex
161 default 0x20000
162 help
163 The amount of anticipated heap usage in CAR by FSP.
164 Refer to Platform FSP integration guide document to know
165 the exact FSP requirement for Heap setup.
166
Tim Wawrzynczak092813a2020-11-24 13:48:56 -0700167config CHIPSET_DEVICETREE
168 string
169 default "soc/intel/alderlake/chipset.cb"
170
Subrata Banik683c95e2020-12-19 19:36:45 +0530171config EXT_BIOS_WIN_BASE
172 default 0xf8000000
173
174config EXT_BIOS_WIN_SIZE
175 default 0x2000000
176
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530177config IFD_CHIPSET
178 string
179 default "adl"
180
181config IED_REGION_SIZE
182 hex
183 default 0x400000
184
185config HEAP_SIZE
186 hex
187 default 0x10000
188
Tim Wawrzynczak8d11cdc2021-03-12 12:46:02 -0700189# Intel recommends reserving the following resources per PCIe TBT root port,
190# from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5
191# - 42 buses
192# - 194 MiB Non-prefetchable memory
193# - 448 MiB Prefetchable memory
Furquan Shaikhd9f5d902021-08-24 13:53:43 -0700194if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
Tim Wawrzynczak8d11cdc2021-03-12 12:46:02 -0700195
196config PCIEXP_HOTPLUG_BUSES
197 int
198 default 42
199
200config PCIEXP_HOTPLUG_MEM
201 hex
202 default 0xc200000
203
204config PCIEXP_HOTPLUG_PREFETCH_MEM
205 hex
206 default 0x1c000000
207
Furquan Shaikhd9f5d902021-08-24 13:53:43 -0700208endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
Tim Wawrzynczak8d11cdc2021-03-12 12:46:02 -0700209
Subrata Banik85144d92021-01-09 16:17:45 +0530210config MAX_PCH_ROOT_PORTS
Subrata Banik2871e0e2020-09-27 11:30:58 +0530211 int
Varshit Pandyab5df56f2021-01-18 09:44:35 +0530212 default 10 if SOC_INTEL_ALDERLAKE_PCH_M
Usha P78c9b672021-11-30 11:27:38 +0530213 default 12 if SOC_INTEL_ALDERLAKE_PCH_N
Angel Ponsdb925aa2021-12-01 11:44:09 +0100214 default 12 if SOC_INTEL_ALDERLAKE_PCH_P
Subrata Banik2871e0e2020-09-27 11:30:58 +0530215
Subrata Banik85144d92021-01-09 16:17:45 +0530216config MAX_CPU_ROOT_PORTS
217 int
Varshit Pandyab5df56f2021-01-18 09:44:35 +0530218 default 1 if SOC_INTEL_ALDERLAKE_PCH_M
Usha P78c9b672021-11-30 11:27:38 +0530219 default 0 if SOC_INTEL_ALDERLAKE_PCH_N
Angel Ponsdb925aa2021-12-01 11:44:09 +0100220 default 3 if SOC_INTEL_ALDERLAKE_PCH_P
Subrata Banik85144d92021-01-09 16:17:45 +0530221
MAULIK V VAGHELA3e4f28f2022-01-21 14:17:53 +0530222config MAX_TBT_ROOT_PORTS
223 int
224 default 0 if SOC_INTEL_ALDERLAKE_PCH_N
225 default 2 if SOC_INTEL_ALDERLAKE_PCH_M
226 default 4 if SOC_INTEL_ALDERLAKE_PCH_P
227
Subrata Banik85144d92021-01-09 16:17:45 +0530228config MAX_ROOT_PORTS
229 int
230 default MAX_PCH_ROOT_PORTS
231
Subrata Banikcffc9382021-01-29 18:41:35 +0530232config MAX_PCIE_CLOCK_SRC
Subrata Banik2871e0e2020-09-27 11:30:58 +0530233 int
Subrata Banikcffc9382021-01-29 18:41:35 +0530234 default 6 if SOC_INTEL_ALDERLAKE_PCH_M
Usha P78c9b672021-11-30 11:27:38 +0530235 default 5 if SOC_INTEL_ALDERLAKE_PCH_N
Angel Ponsdb925aa2021-12-01 11:44:09 +0100236 default 7 if SOC_INTEL_ALDERLAKE_PCH_P
Subrata Banikcffc9382021-01-29 18:41:35 +0530237
238config MAX_PCIE_CLOCK_REQ
239 int
Angel Ponsdb925aa2021-12-01 11:44:09 +0100240 default 6 if SOC_INTEL_ALDERLAKE_PCH_M
Usha P78c9b672021-11-30 11:27:38 +0530241 default 5 if SOC_INTEL_ALDERLAKE_PCH_N
Angel Ponsdb925aa2021-12-01 11:44:09 +0100242 default 10 if SOC_INTEL_ALDERLAKE_PCH_P
Subrata Banik2871e0e2020-09-27 11:30:58 +0530243
244config SMM_TSEG_SIZE
245 hex
246 default 0x800000
247
248config SMM_RESERVED_SIZE
249 hex
250 default 0x200000
251
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530252config PCR_BASE_ADDRESS
253 hex
254 default 0xfd000000
255 help
256 This option allows you to select MMIO Base Address of sideband bus.
257
Shelley Chen4e9bb332021-10-20 15:43:45 -0700258config ECAM_MMCONF_BASE_ADDRESS
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530259 default 0xc0000000
260
261config CPU_BCLK_MHZ
262 int
263 default 100
264
265config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
266 int
267 default 120
268
Michael Niewöhnerdadcbfb2020-10-04 14:48:05 +0200269config CPU_XTAL_HZ
270 default 38400000
271
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530272config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
273 int
274 default 133
275
276config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
277 int
278 default 7
279
280config SOC_INTEL_I2C_DEV_MAX
281 int
Varshit B Pandya339f0e72021-07-14 11:08:23 +0530282 default 8
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530283
284config SOC_INTEL_UART_DEV_MAX
285 int
286 default 7
287
288config CONSOLE_UART_BASE_ADDRESS
289 hex
Bora Guvendik2a704192020-11-16 11:23:48 -0800290 default 0xfe03e000
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530291 depends on INTEL_LPSS_UART_FOR_CONSOLE
292
Maulik V Vaghela996bab42021-02-05 12:03:19 +0530293config VBT_DATA_SIZE_KB
294 int
295 default 9
296
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530297# Clock divider parameters for 115200 baud rate
298# Baudrate = (UART source clcok * M) /(N *16)
299# ADL UART source clock: 120MHz
300config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
301 hex
302 default 0x25a
303
304config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
305 hex
306 default 0x7fff
307
Subrata Banik292afef2020-09-09 13:34:18 +0530308config VBOOT
309 select VBOOT_SEPARATE_VERSTAGE
310 select VBOOT_MUST_REQUEST_DISPLAY
311 select VBOOT_STARTS_IN_BOOTBLOCK
312 select VBOOT_VBNV_CMOS
313 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
Subrata Banik34237862021-06-17 23:36:02 +0530314 select VBOOT_X86_SHA256_ACCELERATION
Subrata Banik292afef2020-09-09 13:34:18 +0530315
MAULIK V VAGHELA84532da2021-08-25 16:41:23 +0530316# Default hash block size is 1KiB. Increasing it to 4KiB to improve
317# hashing time as well as read time. This helps in improving
318# boot time for Alder Lake.
319config VBOOT_HASH_BLOCK_SIZE
320 hex
321 default 0x1000
322
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530323config CBFS_SIZE
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530324 default 0x200000
325
326config PRERAM_CBMEM_CONSOLE_SIZE
327 hex
Subrata Banikbf750552021-07-10 20:30:57 +0530328 default 0x2000
Subrata Banik2871e0e2020-09-27 11:30:58 +0530329
Subrata Banikee735942020-09-07 17:52:23 +0530330config FSP_HEADER_PATH
331 string "Location of FSP headers"
Ronak Kanabarecdc7142022-02-02 16:12:00 +0530332 default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N
Subrata Banikee735942020-09-07 17:52:23 +0530333 default "src/vendorcode/intel/fsp/fsp2_0/alderlake/"
334
335config FSP_FD_PATH
336 string
337 depends on FSP_USE_REPO
338 default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd"
Subrata Banik292afef2020-09-09 13:34:18 +0530339
340config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT
341 int "Debug Consent for ADL"
Subrata Banik0cd553b2021-12-29 08:09:37 +0000342 # USB DBC is more common for developers so make this default to 2 if
Subrata Banik292afef2020-09-09 13:34:18 +0530343 # SOC_INTEL_DEBUG_CONSENT=y
Kane Chen0e9a6162021-11-23 14:42:48 +0800344 default 2 if SOC_INTEL_DEBUG_CONSENT
Subrata Banik292afef2020-09-09 13:34:18 +0530345 default 0
346 help
347 This is to control debug interface on SOC.
348 Setting non-zero value will allow to use DBC or DCI to debug SOC.
349 PlatformDebugConsent in FspmUpd.h has the details.
350
351 Desired platform debug type are
Kane Chen0e9a6162021-11-23 14:42:48 +0800352 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power),
353 7:Manual
Furquan Shaikha1c247b2020-12-31 22:50:14 -0800354
355config DATA_BUS_WIDTH
356 int
357 default 128
358
359config DIMMS_PER_CHANNEL
360 int
361 default 2
362
363config MRC_CHANNEL_WIDTH
364 int
365 default 16
366
Sugnan Prabhu Sdcf04592021-12-03 19:07:04 +0530367config ACPI_ADL_IPU_ES_SUPPORT
368 def_bool n
369 help
370 Enables ACPI entry to provide silicon type information to IPU kernel driver.
371
Furquan Shaikhf888c682021-10-05 21:37:33 -0700372if STITCH_ME_BIN
373
374config CSE_BPDT_VERSION
375 default "1.7"
376
377endif
378
Sridhar Siricillab24c5282022-02-23 12:19:04 +0530379config SI_DESC_REGION
380 string "Descriptor Region name"
381 default "SI_DESC"
382 help
383 Name of Descriptor Region in the FMAP
384
385config SI_DESC_REGION_SZ
386 int
387 default 4096
388 help
389 Size of Descriptor Region in the FMAP
390
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530391endif