Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2 | |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 3 | #include <assert.h> |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 4 | #include <stdint.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 7 | #include <console/console.h> |
| 8 | #include <commonlib/helpers.h> |
| 9 | #include <delay.h> |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 10 | #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 11 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 12 | #else |
| 13 | #include <southbridge/intel/i82801jx/i82801jx.h> |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 14 | #endif |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 15 | #include <string.h> |
Angel Pons | 41e66ac | 2020-09-15 13:17:23 +0200 | [diff] [blame] | 16 | #include "raminit.h" |
Martin Roth | cbe3892 | 2016-01-05 19:40:41 -0700 | [diff] [blame] | 17 | #include "x4x.h" |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 18 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 19 | #define ME_UMA_SIZEMB 0 |
| 20 | |
Elyes HAOUAS | e951e8e | 2019-06-15 11:03:00 +0200 | [diff] [blame] | 21 | u32 fsb_to_mhz(u32 speed) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 22 | { |
| 23 | return (speed * 267) + 800; |
| 24 | } |
| 25 | |
Elyes HAOUAS | e951e8e | 2019-06-15 11:03:00 +0200 | [diff] [blame] | 26 | u32 ddr_to_mhz(u32 speed) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 27 | { |
| 28 | static const u16 mhz[] = { 0, 0, 667, 800, 1067, 1333 }; |
| 29 | |
Jacob Garber | 5033d6c | 2019-06-11 15:23:23 -0600 | [diff] [blame] | 30 | if (speed <= 1 || speed >= ARRAY_SIZE(mhz)) |
| 31 | die("RAM init: invalid memory speed %u\n", speed); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 32 | |
| 33 | return mhz[speed]; |
| 34 | } |
| 35 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 36 | static void program_crossclock(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 37 | { |
| 38 | u8 i, j; |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 39 | u32 reg32; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 40 | MCHBAR16_OR(0xc1c, (1 << 15)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 41 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 42 | static const u32 clkxtab[6][3][13] = { |
Arthur Heymans | 8a3514d | 2016-10-27 23:56:08 +0200 | [diff] [blame] | 43 | /* MEMCLK 400 N/A */ |
| 44 | {{}, {}, {} }, |
| 45 | /* MEMCLK 533 N/A */ |
| 46 | {{}, {}, {} }, |
| 47 | /* MEMCLK 667 |
| 48 | * FSB 800 */ |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 49 | {{0x1f1f1f1f, 0x0d07070b, 0x00000000, 0x10000000, |
Arthur Heymans | 8a3514d | 2016-10-27 23:56:08 +0200 | [diff] [blame] | 50 | 0x20010208, 0x04080000, 0x10010002, 0x00000000, |
| 51 | 0x00000000, 0x02000000, 0x04000100, 0x08000000, |
| 52 | 0x10200204}, |
| 53 | /* FSB 1067 */ |
| 54 | {0x6d5b1f1f, 0x0f0f0f0f, 0x00000000, 0x20000000, |
| 55 | 0x80020410, 0x02040008, 0x10000100, 0x00000000, |
| 56 | 0x00000000, 0x04000000, 0x08000102, 0x20000000, |
| 57 | 0x40010208}, |
| 58 | /* FSB 1333 */ |
| 59 | {0x05050303, 0xffffffff, 0xffff0000, 0x00000000, |
| 60 | 0x08020000, 0x00000000, 0x00020001, 0x00000000, |
| 61 | 0x00000000, 0x00000000, 0x08010204, 0x00000000, |
| 62 | 0x04010000} }, |
| 63 | /* MEMCLK 800 |
| 64 | * FSB 800 */ |
| 65 | {{0xffffffff, 0x05030305, 0x0000ffff, 0x0000000, |
| 66 | 0x08010204, 0x00000000, 0x08010204, 0x0000000, |
| 67 | 0x00000000, 0x00000000, 0x00020001, 0x0000000, |
| 68 | 0x04080102}, |
| 69 | /* FSB 1067 */ |
| 70 | {0x07070707, 0x06030303, 0x00000000, 0x00000000, |
| 71 | 0x08010200, 0x00000000, 0x04000102, 0x00000000, |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 72 | 0x00000000, 0x00000000, 0x00020100, 0x00000000, |
| 73 | 0x04080100}, |
Arthur Heymans | 8a3514d | 2016-10-27 23:56:08 +0200 | [diff] [blame] | 74 | /* FSB 1333 */ |
| 75 | {0x0d0b0707, 0x3e1f1f2f, 0x01010000, 0x00000000, |
| 76 | 0x10020400, 0x02000000, 0x00040100, 0x00000000, |
| 77 | 0x00000000, 0x04080000, 0x00100102, 0x00000000, |
| 78 | 0x08100200} }, |
| 79 | /* MEMCLK 1067 */ |
| 80 | {{}, |
| 81 | /* FSB 1067 */ |
| 82 | {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000, |
| 83 | 0x04080102, 0x00000000, 0x08010204, 0x00000000, |
| 84 | 0x00000000, 0x00000000, 0x00020001, 0x00000000, |
| 85 | 0x02040801}, |
| 86 | /* FSB 1333 */ |
| 87 | {0x0f0f0f0f, 0x5b1f1f6d, 0x00000000, 0x00000000, |
| 88 | 0x08010204, 0x04000000, 0x00080102, 0x00000000, |
| 89 | 0x00000000, 0x02000408, 0x00100001, 0x00000000, |
| 90 | 0x04080102} }, |
| 91 | /* MEMCLK 1333 */ |
| 92 | {{}, {}, |
| 93 | /* FSB 1333 */ |
| 94 | {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000, |
| 95 | 0x04080102, 0x00000000, 0x04080102, 0x00000000, |
| 96 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 97 | 0x02040801} } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 98 | }; |
| 99 | |
| 100 | i = (u8)s->selected_timings.mem_clk; |
| 101 | j = (u8)s->selected_timings.fsb_clk; |
| 102 | |
| 103 | MCHBAR32(0xc04) = clkxtab[i][j][0]; |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 104 | reg32 = clkxtab[i][j][1]; |
| 105 | if (s->spd_type == DDR3 && s->max_fsb == FSB_CLOCK_1333MHz |
| 106 | && s->selected_timings.mem_clk == MEM_CLOCK_800MHz) { |
| 107 | reg32 &= ~(0xff << 24); |
| 108 | reg32 |= 0x3d << 24; |
| 109 | } |
| 110 | MCHBAR32(0xc50) = reg32; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 111 | MCHBAR32(0xc54) = clkxtab[i][j][2]; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 112 | MCHBAR8_OR(0xc08, (1 << 7)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 113 | MCHBAR32(0x6d8) = clkxtab[i][j][3]; |
| 114 | MCHBAR32(0x6e0) = clkxtab[i][j][3]; |
| 115 | MCHBAR32(0x6dc) = clkxtab[i][j][4]; |
| 116 | MCHBAR32(0x6e4) = clkxtab[i][j][4]; |
| 117 | MCHBAR32(0x6e8) = clkxtab[i][j][5]; |
| 118 | MCHBAR32(0x6f0) = clkxtab[i][j][5]; |
| 119 | MCHBAR32(0x6ec) = clkxtab[i][j][6]; |
| 120 | MCHBAR32(0x6f4) = clkxtab[i][j][6]; |
| 121 | MCHBAR32(0x6f8) = clkxtab[i][j][7]; |
| 122 | MCHBAR32(0x6fc) = clkxtab[i][j][8]; |
| 123 | MCHBAR32(0x708) = clkxtab[i][j][11]; |
| 124 | MCHBAR32(0x70c) = clkxtab[i][j][12]; |
| 125 | } |
| 126 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 127 | static void setioclk_dram(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 128 | { |
| 129 | MCHBAR32(0x1bc) = 0x08060402; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 130 | MCHBAR16_OR(0x1c0, 0x200); |
| 131 | MCHBAR16_OR(0x1c0, 0x100); |
| 132 | MCHBAR16_OR(0x1c0, 0x20); |
| 133 | MCHBAR16_AND(0x1c0, ~1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 134 | switch (s->selected_timings.mem_clk) { |
| 135 | default: |
| 136 | case MEM_CLOCK_800MHz: |
| 137 | case MEM_CLOCK_1066MHz: |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 138 | MCHBAR8_AND_OR(0x5d9, ~0x2, 0x2); |
| 139 | MCHBAR8_AND_OR(0x9d9, ~0x2, 0x2); |
| 140 | MCHBAR8_AND_OR(0x189, ~0xf0, 0xc0); |
| 141 | MCHBAR8_AND_OR(0x189, ~0xf0, 0xe0); |
| 142 | MCHBAR8_AND_OR(0x189, ~0xf0, 0xa0); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 143 | break; |
| 144 | case MEM_CLOCK_667MHz: |
| 145 | case MEM_CLOCK_1333MHz: |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 146 | MCHBAR8_AND(0x5d9, ~0x2); |
| 147 | MCHBAR8_AND(0x9d9, ~0x2); |
| 148 | MCHBAR8_AND_OR(0x189, ~0xf0, 0x40); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 149 | break; |
| 150 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 151 | MCHBAR32_OR(0x594, 1 << 31); |
| 152 | MCHBAR32_OR(0x994, 1 << 31); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 153 | } |
| 154 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 155 | static void launch_dram(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 156 | { |
| 157 | u8 i; |
Arthur Heymans | 7a3a319 | 2017-05-15 10:26:29 +0200 | [diff] [blame] | 158 | u32 launch1; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 159 | u32 launch2 = 0; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 160 | |
Arthur Heymans | 7a3a319 | 2017-05-15 10:26:29 +0200 | [diff] [blame] | 161 | static const u32 ddr3_launch1_tab[2][3] = { |
| 162 | /* 1N */ |
| 163 | {0x58000007, /* DDR3 800 */ |
| 164 | 0x58000007, /* DDR3 1067 */ |
| 165 | 0x58100107}, /* DDR3 1333 */ |
| 166 | /* 2N */ |
| 167 | {0x58001117, /* DDR3 800 */ |
| 168 | 0x58001117, /* DDR3 1067 */ |
| 169 | 0x58001117} /* DDR3 1333 */ |
| 170 | }; |
| 171 | |
| 172 | static const u32 ddr3_launch2_tab[2][3][6] = { |
| 173 | { /* 1N */ |
| 174 | /* DDR3 800 */ |
| 175 | {0x08030000, /* CL = 5 */ |
| 176 | 0x0C040100}, /* CL = 6 */ |
| 177 | /* DDR3 1066 */ |
| 178 | {0x00000000, /* CL = 5 */ |
| 179 | 0x00000000, /* CL = 6 */ |
| 180 | 0x10050100, /* CL = 7 */ |
| 181 | 0x14260200}, /* CL = 8 */ |
| 182 | /* DDR3 1333 */ |
| 183 | {0x00000000, /* CL = 5 */ |
| 184 | 0x00000000, /* CL = 6 */ |
| 185 | 0x00000000, /* CL = 7 */ |
| 186 | 0x14060000, /* CL = 8 */ |
| 187 | 0x18070100, /* CL = 9 */ |
| 188 | 0x1C280200}, /* CL = 10 */ |
| 189 | |
| 190 | }, |
| 191 | { /* 2N */ |
| 192 | /* DDR3 800 */ |
| 193 | {0x00040101, /* CL = 5 */ |
| 194 | 0x00250201}, /* CL = 6 */ |
| 195 | /* DDR3 1066 */ |
| 196 | {0x00000000, /* CL = 5 */ |
| 197 | 0x00050101, /* CL = 6 */ |
| 198 | 0x04260201, /* CL = 7 */ |
| 199 | 0x08470301}, /* CL = 8 */ |
| 200 | /* DDR3 1333 */ |
| 201 | {0x00000000, /* CL = 5 */ |
| 202 | 0x00000000, /* CL = 6 */ |
| 203 | 0x00000000, /* CL = 7 */ |
| 204 | 0x08070100, /* CL = 8 */ |
| 205 | 0x0C280200, /* CL = 9 */ |
| 206 | 0x10490300} /* CL = 10 */ |
| 207 | } |
| 208 | }; |
| 209 | |
| 210 | if (s->spd_type == DDR2) { |
| 211 | launch1 = 0x58001117; |
| 212 | if (s->selected_timings.CAS == 5) |
| 213 | launch2 = 0x00220201; |
| 214 | else if (s->selected_timings.CAS == 6) |
| 215 | launch2 = 0x00230302; |
| 216 | else |
| 217 | die("Unsupported CAS\n"); |
| 218 | } else { /* DDR3 */ |
| 219 | /* Default 2N mode */ |
| 220 | s->nmode = 2; |
| 221 | |
| 222 | if (s->selected_timings.mem_clk <= MEM_CLOCK_1066MHz) |
| 223 | s->nmode = 1; |
Elyes HAOUAS | 6538d91 | 2021-01-16 15:01:23 +0100 | [diff] [blame] | 224 | /* 2N on DDR3 1066 with 2 dimms per channel */ |
Arthur Heymans | 7a3a319 | 2017-05-15 10:26:29 +0200 | [diff] [blame] | 225 | if ((s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) && |
| 226 | (BOTH_DIMMS_ARE_POPULATED(s->dimms, 0) || |
| 227 | BOTH_DIMMS_ARE_POPULATED(s->dimms, 1))) |
| 228 | s->nmode = 2; |
| 229 | launch1 = ddr3_launch1_tab[s->nmode - 1] |
| 230 | [s->selected_timings.mem_clk - MEM_CLOCK_800MHz]; |
| 231 | launch2 = ddr3_launch2_tab[s->nmode - 1] |
| 232 | [s->selected_timings.mem_clk - MEM_CLOCK_800MHz] |
| 233 | [s->selected_timings.CAS - 5]; |
| 234 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 235 | |
| 236 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
| 237 | MCHBAR32(0x400*i + 0x220) = launch1; |
| 238 | MCHBAR32(0x400*i + 0x224) = launch2; |
Arthur Heymans | 7a3a319 | 2017-05-15 10:26:29 +0200 | [diff] [blame] | 239 | MCHBAR32(0x400*i + 0x21c) = 0; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 240 | MCHBAR32_OR(0x400*i + 0x248, 1 << 23); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 241 | } |
| 242 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 243 | MCHBAR32_AND_OR(0x2c0, ~0x58000000, 0x48000000); |
| 244 | MCHBAR32_OR(0x2c0, 0x1e0); |
| 245 | MCHBAR32_AND_OR(0x2c4, ~0xf, 0xc); |
Arthur Heymans | 7a3a319 | 2017-05-15 10:26:29 +0200 | [diff] [blame] | 246 | if (s->spd_type == DDR3) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 247 | MCHBAR32_OR(0x2c4, 0x100); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 248 | } |
| 249 | |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 250 | static void write_txdll_tap_pi(u8 ch, u16 reg, u8 tap, u8 pi) |
| 251 | { |
| 252 | MCHBAR8_AND_OR(0x400 * ch + reg, ~0x7f, pi << 4 | tap); |
| 253 | } |
| 254 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 255 | static void clkset0(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 256 | { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 257 | MCHBAR16_AND_OR(0x400*ch + 0x5a0, ~0xc440, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 258 | (setting->clk_delay << 14) | |
| 259 | (setting->db_sel << 6) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 260 | (setting->db_en << 10)); |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 261 | write_txdll_tap_pi(ch, 0x581, setting->tap, setting->pi); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 262 | } |
| 263 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 264 | static void clkset1(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 265 | { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 266 | MCHBAR32_AND_OR(0x400*ch + 0x5a0, ~0x30880, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 267 | (setting->clk_delay << 16) | |
| 268 | (setting->db_sel << 7) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 269 | (setting->db_en << 11)); |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 270 | write_txdll_tap_pi(ch, 0x582, setting->tap, setting->pi); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 271 | } |
| 272 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 273 | static void ctrlset0(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 274 | { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 275 | MCHBAR32_AND_OR(0x400*ch + 0x59c, ~0x3300000, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 276 | (setting->clk_delay << 24) | |
| 277 | (setting->db_sel << 20) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 278 | (setting->db_en << 21)); |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 279 | write_txdll_tap_pi(ch, 0x584, setting->tap, setting->pi); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 280 | } |
| 281 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 282 | static void ctrlset1(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 283 | { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 284 | MCHBAR32_AND_OR(0x400*ch + 0x59c, ~0x18c00000, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 285 | (setting->clk_delay << 27) | |
| 286 | (setting->db_sel << 22) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 287 | (setting->db_en << 23)); |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 288 | write_txdll_tap_pi(ch, 0x585, setting->tap, setting->pi); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 289 | } |
| 290 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 291 | static void ctrlset2(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 292 | { |
Angel Pons | 22fd0dc | 2021-01-13 14:27:14 +0100 | [diff] [blame] | 293 | /* |
| 294 | * MRC uses an incorrect mask when programming this register, but |
| 295 | * the reset default value is zero and it is only programmed once. |
| 296 | * As it makes no difference, we can safely use the correct mask. |
| 297 | */ |
| 298 | MCHBAR32_AND_OR(0x400*ch + 0x598, ~0xf000, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 299 | (setting->clk_delay << 14) | |
| 300 | (setting->db_sel << 12) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 301 | (setting->db_en << 13)); |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 302 | write_txdll_tap_pi(ch, 0x586, setting->tap, setting->pi); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 303 | } |
| 304 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 305 | static void ctrlset3(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 306 | { |
Angel Pons | 22fd0dc | 2021-01-13 14:27:14 +0100 | [diff] [blame] | 307 | /* |
| 308 | * MRC uses an incorrect mask when programming this register, but |
| 309 | * the reset default value is zero and it is only programmed once. |
| 310 | * As it makes no difference, we can safely use the correct mask. |
| 311 | */ |
| 312 | MCHBAR32_AND_OR(0x400*ch + 0x598, ~0xf00, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 313 | (setting->clk_delay << 10) | |
| 314 | (setting->db_sel << 8) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 315 | (setting->db_en << 9)); |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 316 | write_txdll_tap_pi(ch, 0x587, setting->tap, setting->pi); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 317 | } |
| 318 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 319 | static void cmdset(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 320 | { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 321 | MCHBAR8_AND_OR(0x400*ch + 0x598, ~0x30, setting->clk_delay << 4); |
| 322 | MCHBAR8_AND_OR(0x400*ch + 0x594, ~0x60, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 323 | (setting->db_sel << 5) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 324 | (setting->db_en << 6)); |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 325 | write_txdll_tap_pi(ch, 0x580, setting->tap, setting->pi); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 326 | } |
| 327 | |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 328 | /** |
| 329 | * All finer DQ and DQS DLL settings are set to the same value |
| 330 | * for each rank in a channel, while coarse is common. |
| 331 | */ |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 332 | void dqsset(u8 ch, u8 lane, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 333 | { |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 334 | int rank; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 335 | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 336 | MCHBAR32_AND_OR(0x400 * ch + 0x5fc, ~(1 << (lane * 4 + 1)), |
| 337 | setting->coarse << (lane * 4 + 1)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 338 | |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 339 | for (rank = 0; rank < 4; rank++) { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 340 | MCHBAR32_AND_OR(0x400 * ch + 0x5b4 + rank * 4, ~(0x201 << lane), |
| 341 | (setting->db_en << (9 + lane)) | |
| 342 | (setting->db_sel << lane)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 343 | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 344 | MCHBAR32_AND_OR(0x400*ch + 0x5c8 + rank * 4, |
| 345 | ~(0x3 << (16 + lane * 2)), |
| 346 | setting->clk_delay << (16+lane * 2)); |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 347 | |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 348 | write_txdll_tap_pi(ch, 0x520 + lane * 4 + rank, setting->tap, setting->pi); |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 349 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 350 | } |
| 351 | |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 352 | void dqset(u8 ch, u8 lane, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 353 | { |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 354 | int rank; |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 355 | MCHBAR32_AND_OR(0x400 * ch + 0x5fc, ~(1 << (lane * 4)), |
| 356 | setting->coarse << (lane * 4)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 357 | |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 358 | for (rank = 0; rank < 4; rank++) { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 359 | MCHBAR32_AND_OR(0x400 * ch + 0x5a4 + rank * 4, ~(0x201 << lane), |
| 360 | (setting->db_en << (9 + lane)) | |
| 361 | (setting->db_sel << lane)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 362 | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 363 | MCHBAR32_AND_OR(0x400 * ch + 0x5c8 + rank * 4, |
| 364 | ~(0x3 << (lane * 2)), setting->clk_delay << (2 * lane)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 365 | |
Angel Pons | 43a5e0c | 2021-01-13 14:39:20 +0100 | [diff] [blame] | 366 | write_txdll_tap_pi(ch, 0x500 + lane * 4 + rank, setting->tap, setting->pi); |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 367 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 368 | } |
| 369 | |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 370 | void rt_set_dqs(u8 channel, u8 lane, u8 rank, |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 371 | struct rt_dqs_setting *dqs_setting) |
| 372 | { |
| 373 | u16 saved_tap = MCHBAR16(0x540 + 0x400 * channel + lane * 4); |
| 374 | u16 saved_pi = MCHBAR16(0x542 + 0x400 * channel + lane * 4); |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 375 | printk(RAM_SPEW, "RT DQS: ch%d, r%d, L%d: %d.%d\n", channel, rank, lane, |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 376 | dqs_setting->tap, |
| 377 | dqs_setting->pi); |
| 378 | |
| 379 | saved_tap &= ~(0xf << (rank * 4)); |
| 380 | saved_tap |= dqs_setting->tap << (rank * 4); |
| 381 | MCHBAR16(0x540 + 0x400 * channel + lane * 4) = saved_tap; |
| 382 | |
| 383 | saved_pi &= ~(0x7 << (rank * 3)); |
| 384 | saved_pi |= dqs_setting->pi << (rank * 3); |
| 385 | MCHBAR16(0x542 + 0x400 * channel + lane * 4) = saved_pi; |
| 386 | } |
| 387 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 388 | static void program_timings(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 389 | { |
| 390 | u8 i; |
| 391 | u8 twl, ta1, ta2, ta3, ta4; |
| 392 | u8 reg8; |
| 393 | u8 flag1 = 0; |
| 394 | u8 flag2 = 0; |
| 395 | u16 reg16; |
| 396 | u32 reg32; |
| 397 | u16 ddr, fsb; |
| 398 | u8 trpmod = 0; |
| 399 | u8 bankmod = 1; |
| 400 | u8 pagemod = 0; |
Arthur Heymans | eee4f6b | 2017-01-03 00:49:45 +0100 | [diff] [blame] | 401 | u8 adjusted_cas; |
| 402 | |
| 403 | adjusted_cas = s->selected_timings.CAS - 3; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 404 | |
Elyes HAOUAS | e951e8e | 2019-06-15 11:03:00 +0200 | [diff] [blame] | 405 | u16 fsb_to_ps[3] = { |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 406 | 5000, /* 800 */ |
| 407 | 3750, /* 1067 */ |
| 408 | 3000 /* 1333 */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 409 | }; |
| 410 | |
Elyes HAOUAS | e951e8e | 2019-06-15 11:03:00 +0200 | [diff] [blame] | 411 | u16 ddr_to_ps[6] = { |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 412 | 5000, /* 400 */ |
| 413 | 3750, /* 533 */ |
| 414 | 3000, /* 667 */ |
| 415 | 2500, /* 800 */ |
| 416 | 1875, /* 1067 */ |
| 417 | 1500 /* 1333 */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 418 | }; |
| 419 | |
| 420 | u16 lut1[6] = { |
| 421 | 0, |
| 422 | 0, |
| 423 | 2600, |
| 424 | 3120, |
| 425 | 4171, |
| 426 | 5200 |
| 427 | }; |
| 428 | |
Elyes HAOUAS | 68ec3eb | 2019-06-22 09:21:18 +0200 | [diff] [blame] | 429 | static const u8 ddr3_turnaround_tab[3][6][4] = { |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 430 | { /* DDR3 800 */ |
Angel Pons | 06d224f | 2021-01-13 13:05:26 +0100 | [diff] [blame] | 431 | {0x9, 0x7, 0x9, 0x7}, /* CL = 5 */ |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 432 | {0x9, 0x7, 0x8, 0x8}, /* CL = 6 */ |
| 433 | }, |
| 434 | { /* DDR3 1066 */ |
| 435 | {0x0, 0x0, 0x0, 0x0}, /* CL = 5 - Not supported */ |
Angel Pons | 06d224f | 2021-01-13 13:05:26 +0100 | [diff] [blame] | 436 | {0x9, 0x7, 0x9, 0x7}, /* CL = 6 */ |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 437 | {0x9, 0x7, 0x8, 0x8}, /* CL = 7 */ |
Angel Pons | 06d224f | 2021-01-13 13:05:26 +0100 | [diff] [blame] | 438 | {0x9, 0x7, 0x7, 0x9} /* CL = 8 */ |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 439 | }, |
| 440 | { /* DDR3 1333 */ |
| 441 | {0x0, 0x0, 0x0, 0x0}, /* CL = 5 - Not supported */ |
| 442 | {0x0, 0x0, 0x0, 0x0}, /* CL = 6 - Not supported */ |
| 443 | {0x0, 0x0, 0x0, 0x0}, /* CL = 7 - Not supported */ |
Angel Pons | 06d224f | 2021-01-13 13:05:26 +0100 | [diff] [blame] | 444 | {0x9, 0x7, 0x8, 0x9}, /* CL = 8 */ |
| 445 | {0x9, 0x7, 0x7, 0xa}, /* CL = 9 */ |
| 446 | {0x9, 0x7, 0x6, 0xb}, /* CL = 10 */ |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 447 | } |
| 448 | }; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 449 | |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 450 | /* [DDR freq][0x26F & 1][pagemod] */ |
Elyes HAOUAS | 68ec3eb | 2019-06-22 09:21:18 +0200 | [diff] [blame] | 451 | static const u8 ddr2_x252_tab[2][2][2] = { |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 452 | { /* DDR2 667 */ |
| 453 | {12, 16}, |
| 454 | {14, 18} |
| 455 | }, |
| 456 | { /* DDR2 800 */ |
| 457 | {14, 18}, |
| 458 | {16, 20} |
| 459 | } |
| 460 | }; |
| 461 | |
Elyes HAOUAS | 68ec3eb | 2019-06-22 09:21:18 +0200 | [diff] [blame] | 462 | static const u8 ddr3_x252_tab[3][2][2] = { |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 463 | { /* DDR3 800 */ |
| 464 | {16, 20}, |
| 465 | {18, 22} |
| 466 | }, |
| 467 | { /* DDR3 1067 */ |
| 468 | {20, 26}, |
| 469 | {26, 26} |
| 470 | }, |
| 471 | { /* DDR3 1333 */ |
| 472 | {20, 30}, |
| 473 | {22, 32}, |
| 474 | } |
| 475 | }; |
| 476 | |
| 477 | if (s->spd_type == DDR2) { |
| 478 | ta1 = 6; |
| 479 | ta2 = 6; |
| 480 | ta3 = 5; |
| 481 | ta4 = 8; |
| 482 | } else { |
| 483 | int ddr3_idx = s->selected_timings.mem_clk - MEM_CLOCK_800MHz; |
| 484 | int cas_idx = s->selected_timings.CAS - 5; |
| 485 | ta1 = ddr3_turnaround_tab[ddr3_idx][cas_idx][0]; |
| 486 | ta2 = ddr3_turnaround_tab[ddr3_idx][cas_idx][1]; |
| 487 | ta3 = ddr3_turnaround_tab[ddr3_idx][cas_idx][2]; |
| 488 | ta4 = ddr3_turnaround_tab[ddr3_idx][cas_idx][3]; |
| 489 | } |
| 490 | |
| 491 | if (s->spd_type == DDR2) |
| 492 | twl = s->selected_timings.CAS - 1; |
| 493 | else /* DDR3 */ |
| 494 | twl = s->selected_timings.mem_clk - MEM_CLOCK_800MHz + 5; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 495 | |
| 496 | FOR_EACH_POPULATED_DIMM(s->dimms, i) { |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 497 | if (s->dimms[i].n_banks == N_BANKS_8) { |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 498 | trpmod = 1; |
| 499 | bankmod = 0; |
| 500 | } |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 501 | if (s->dimms[i].page_size == 2048) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 502 | pagemod = 1; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 503 | } |
| 504 | |
| 505 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 506 | MCHBAR8_OR(0x400*i + 0x26f, 0x3); |
| 507 | MCHBAR8_AND_OR(0x400*i + 0x228, ~0x7, 0x2); |
| 508 | /* tWL - x ?? */ |
| 509 | MCHBAR8_AND_OR(0x400*i + 0x240, ~0xf0, 0 << 4); |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 510 | MCHBAR8_AND_OR(0x400*i + 0x240, ~0xf, adjusted_cas); |
| 511 | MCHBAR16_AND_OR(0x400*i + 0x265, ~0x3f00, |
| 512 | (adjusted_cas + 9) << 8); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 513 | |
| 514 | reg16 = (s->selected_timings.tRAS << 11) | |
| 515 | ((twl + 4 + s->selected_timings.tWR) << 6) | |
| 516 | ((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1; |
| 517 | MCHBAR16(0x400*i + 0x250) = reg16; |
| 518 | |
| 519 | reg32 = (bankmod << 21) | |
| 520 | (s->selected_timings.tRRD << 17) | |
| 521 | (s->selected_timings.tRP << 13) | |
| 522 | ((s->selected_timings.tRP + trpmod) << 9) | |
| 523 | s->selected_timings.tRFC; |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 524 | if (bankmod == 0) { |
| 525 | reg8 = (MCHBAR8(0x400*i + 0x26f) >> 1) & 1; |
| 526 | if (s->spd_type == DDR2) |
| 527 | reg32 |= ddr2_x252_tab[s->selected_timings.mem_clk |
| 528 | - MEM_CLOCK_667MHz][reg8][pagemod] |
| 529 | << 22; |
| 530 | else |
| 531 | reg32 |= ddr3_x252_tab[s->selected_timings.mem_clk |
| 532 | - MEM_CLOCK_800MHz][reg8][pagemod] |
| 533 | << 22; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 534 | } |
| 535 | MCHBAR32(0x400*i + 0x252) = reg32; |
| 536 | |
| 537 | MCHBAR16(0x400*i + 0x256) = (s->selected_timings.tRCD << 12) | |
| 538 | (0x4 << 8) | (ta2 << 4) | ta4; |
| 539 | |
| 540 | MCHBAR32(0x400*i + 0x258) = (s->selected_timings.tRCD << 17) | |
| 541 | ((twl + 4 + s->selected_timings.tWTR) << 12) | |
| 542 | (ta3 << 8) | (4 << 4) | ta1; |
| 543 | |
| 544 | MCHBAR16(0x400*i + 0x25b) = ((s->selected_timings.tRP + trpmod) << 9) | |
| 545 | s->selected_timings.tRFC; |
| 546 | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 547 | MCHBAR16_AND_OR(0x400*i + 0x260, ~0x3fe, |
| 548 | (s->spd_type == DDR2 ? 100 : 256) << 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 549 | MCHBAR8(0x400*i + 0x264) = 0xff; |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 550 | MCHBAR8_AND_OR(0x400*i + 0x25d, ~0x3f, |
| 551 | s->selected_timings.tRAS); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 552 | MCHBAR16(0x400*i + 0x244) = 0x2310; |
| 553 | |
| 554 | switch (s->selected_timings.mem_clk) { |
| 555 | case MEM_CLOCK_667MHz: |
| 556 | reg8 = 0; |
| 557 | break; |
| 558 | default: |
| 559 | reg8 = 1; |
| 560 | break; |
| 561 | } |
| 562 | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 563 | MCHBAR8_AND_OR(0x400*i + 0x246, ~0x1f, (reg8 << 2) | 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 564 | |
Elyes HAOUAS | e951e8e | 2019-06-15 11:03:00 +0200 | [diff] [blame] | 565 | fsb = fsb_to_ps[s->selected_timings.fsb_clk]; |
| 566 | ddr = ddr_to_ps[s->selected_timings.mem_clk]; |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 567 | reg32 = (u32)((s->selected_timings.CAS + 7 + reg8) * ddr); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 568 | reg32 = (u32)((reg32 / fsb) << 8); |
| 569 | reg32 |= 0x0e000000; |
Elyes HAOUAS | e951e8e | 2019-06-15 11:03:00 +0200 | [diff] [blame] | 570 | if ((fsb_to_mhz(s->selected_timings.fsb_clk) / |
| 571 | ddr_to_mhz(s->selected_timings.mem_clk)) > 2) { |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 572 | reg32 |= 1 << 24; |
| 573 | } |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 574 | MCHBAR32_AND_OR(0x400*i + 0x248, ~0x0f001f00, reg32); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 575 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 576 | if (twl > 2) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 577 | flag1 = 1; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 578 | |
| 579 | if (s->selected_timings.mem_clk >= MEM_CLOCK_800MHz) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 580 | flag2 = 1; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 581 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 582 | reg16 = (u8)(twl - 1 - flag1 - flag2); |
| 583 | reg16 |= reg16 << 4; |
| 584 | if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 585 | if (reg16) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 586 | reg16--; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 587 | } |
| 588 | reg16 |= flag1 << 8; |
| 589 | reg16 |= flag2 << 9; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 590 | MCHBAR16_AND_OR(0x400*i + 0x24d, ~0x1ff, reg16); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 591 | MCHBAR16(0x400*i + 0x25e) = 0x15a5; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 592 | MCHBAR32_AND(0x400*i + 0x265, ~0x1f); |
| 593 | MCHBAR32_AND_OR(0x400*i + 0x269, ~0x000fffff, |
| 594 | (0x3f << 14) | lut1[s->selected_timings.mem_clk]); |
| 595 | MCHBAR8_OR(0x400*i + 0x274, 1); |
| 596 | MCHBAR8_AND(0x400*i + 0x24c, ~0x3); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 597 | |
| 598 | reg16 = 0; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 599 | if (s->spd_type == DDR2) { |
| 600 | switch (s->selected_timings.mem_clk) { |
| 601 | default: |
| 602 | case MEM_CLOCK_667MHz: |
| 603 | reg16 = 0x99; |
| 604 | break; |
| 605 | case MEM_CLOCK_800MHz: |
| 606 | if (s->selected_timings.CAS == 5) |
| 607 | reg16 = 0x19a; |
| 608 | else if (s->selected_timings.CAS == 6) |
| 609 | reg16 = 0x9a; |
| 610 | break; |
| 611 | } |
| 612 | } else { /* DDR3 */ |
| 613 | switch (s->selected_timings.mem_clk) { |
| 614 | default: |
| 615 | case MEM_CLOCK_800MHz: |
| 616 | case MEM_CLOCK_1066MHz: |
| 617 | reg16 = 1; |
| 618 | break; |
| 619 | case MEM_CLOCK_1333MHz: |
| 620 | reg16 = 2; |
| 621 | break; |
| 622 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 623 | } |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 624 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 625 | reg16 &= 0x7; |
| 626 | reg16 += twl + 9; |
| 627 | reg16 <<= 10; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 628 | MCHBAR16_AND_OR(0x400*i + 0x24d, ~0x7c00, reg16); |
| 629 | MCHBAR8_AND_OR(0x400*i + 0x267, ~0x3f, 0x13); |
| 630 | MCHBAR8_AND_OR(0x400*i + 0x268, ~0xff, 0x4a); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 631 | |
| 632 | reg16 = (MCHBAR16(0x400*i + 0x269) & 0xc000) >> 2; |
| 633 | reg16 += 2 << 12; |
| 634 | reg16 |= (0x15 << 6) | 0x1f; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 635 | MCHBAR16_AND_OR(0x400*i + 0x26d, ~0x7fff, reg16); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 636 | |
| 637 | reg32 = (1 << 25) | (6 << 27); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 638 | MCHBAR32_AND_OR(0x400*i + 0x269, ~0xfa300000, reg32); |
| 639 | MCHBAR8_AND(0x400*i + 0x271, ~0x80); |
| 640 | MCHBAR8_AND(0x400*i + 0x274, ~0x6); |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 641 | } /* END EACH POPULATED CHANNEL */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 642 | |
| 643 | reg16 = 0x1f << 5; |
| 644 | reg16 |= 0xe << 10; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 645 | MCHBAR16_AND_OR(0x125, ~0x3fe0, reg16); |
| 646 | MCHBAR16_AND_OR(0x127, ~0x7ff, 0x540); |
| 647 | MCHBAR8_OR(0x129, 0x1f); |
| 648 | MCHBAR8_OR(0x12c, 0xa0); |
| 649 | MCHBAR32_AND_OR(0x241, ~0x1ffff, 0x11); |
| 650 | MCHBAR32_AND_OR(0x641, ~0x1ffff, 0x11); |
| 651 | MCHBAR8_AND(0x246, ~0x10); |
| 652 | MCHBAR8_AND(0x646, ~0x10); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 653 | MCHBAR32(0x120) = (2 << 29) | (1 << 28) | (1 << 23) | 0xd7f5f; |
| 654 | reg8 = (u8)((MCHBAR32(0x252) & 0x1e000) >> 13); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 655 | MCHBAR8_AND_OR(0x12d, ~0xf0, reg8 << 4); |
Arthur Heymans | eee4f6b | 2017-01-03 00:49:45 +0100 | [diff] [blame] | 656 | reg8 = (u8)((MCHBAR32(0x258) & 0x1e0000) >> 17); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 657 | MCHBAR8_AND_OR(0x12d, ~0xf, reg8); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 658 | MCHBAR8(0x12f) = 0x4c; |
| 659 | reg32 = (1 << 31) | (0x80 << 14) | (1 << 13) | (0xa << 9); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 660 | if (s->spd_type == DDR3) { |
| 661 | MCHBAR8(0x114) = 0x42; |
| 662 | reg16 = (512 - MAX(5, s->selected_timings.tRFC + 10000 |
Elyes HAOUAS | e951e8e | 2019-06-15 11:03:00 +0200 | [diff] [blame] | 663 | / ddr_to_ps[s->selected_timings.mem_clk])) |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 664 | / 2; |
| 665 | reg16 &= 0x1ff; |
| 666 | reg32 = (reg16 << 22) | (0x80 << 14) | (0xa << 9); |
| 667 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 668 | MCHBAR32_AND_OR(0x6c0, ~0xffffff00, reg32); |
| 669 | MCHBAR8_AND_OR(0x6c4, ~0x7, 0x2); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 670 | } |
| 671 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 672 | static void program_dll(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 673 | { |
Arthur Heymans | 37689fa | 2017-05-17 14:07:10 +0200 | [diff] [blame] | 674 | u8 i, j, r, reg8, clk, async = 0; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 675 | u16 reg16 = 0; |
| 676 | u32 reg32 = 0; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 677 | |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 678 | const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04, |
| 679 | 0x08, 0x10 }; |
| 680 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 681 | MCHBAR16_AND_OR(0x180, ~0x7e06, 0xc04); |
| 682 | MCHBAR16_AND_OR(0x182, ~0x3ff, 0xc8); |
| 683 | MCHBAR16_AND_OR(0x18a, ~0x1f1f, 0x0f0f); |
| 684 | MCHBAR16_AND_OR(0x1b4, ~0x8020, 0x100); |
| 685 | MCHBAR8_AND_OR(0x194, ~0x77, 0x33); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 686 | switch (s->selected_timings.mem_clk) { |
| 687 | default: |
| 688 | case MEM_CLOCK_667MHz: |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 689 | case MEM_CLOCK_1333MHz: |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 690 | reg16 = (0xa << 9) | 0xa; |
| 691 | break; |
| 692 | case MEM_CLOCK_800MHz: |
| 693 | reg16 = (0x9 << 9) | 0x9; |
| 694 | break; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 695 | case MEM_CLOCK_1066MHz: |
| 696 | reg16 = (0x7 << 9) | 0x7; |
| 697 | break; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 698 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 699 | MCHBAR16_AND_OR(0x19c, ~0x1e0f, reg16); |
| 700 | MCHBAR16_AND_OR(0x19c, ~0x2030, 0x2010); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 701 | udelay(1); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 702 | MCHBAR16_AND(0x198, ~0x100); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 703 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 704 | MCHBAR16_AND_OR(0x1c8, ~0x1f, 0xd); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 705 | |
| 706 | udelay(1); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 707 | MCHBAR8_AND(0x190, ~1); |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 708 | udelay(1); /* 533ns */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 709 | MCHBAR32_AND(0x198, ~0x11554000); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 710 | udelay(1); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 711 | MCHBAR32_AND(0x198, ~0x1455); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 712 | udelay(1); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 713 | MCHBAR8_AND(0x583, ~0x1c); |
| 714 | MCHBAR8_AND(0x983, ~0x1c); |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 715 | udelay(1); /* 533ns */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 716 | MCHBAR8_AND(0x583, ~0x3); |
| 717 | MCHBAR8_AND(0x983, ~0x3); |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 718 | udelay(1); /* 533ns */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 719 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 720 | /* ME related */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 721 | MCHBAR32_AND_OR(0x1a0, ~0x7ffffff, |
| 722 | s->spd_type == DDR2 ? 0x551803 : 0x555801); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 723 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 724 | MCHBAR16_AND(0x1b4, ~0x800); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 725 | if (s->spd_type == DDR2) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 726 | MCHBAR8_OR(0x1a8, 0xf0); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 727 | } else { /* DDR3 */ |
| 728 | reg8 = 0x9; /* 0x9 << 4 ?? */ |
| 729 | if (s->dimms[0].ranks == 2) |
| 730 | reg8 &= ~0x80; |
| 731 | if (s->dimms[3].ranks == 2) |
| 732 | reg8 &= ~0x10; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 733 | MCHBAR8_AND_OR(0x1a8, ~0xf0, reg8); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 734 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 735 | |
| 736 | FOR_EACH_CHANNEL(i) { |
| 737 | reg16 = 0; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 738 | if ((s->spd_type == DDR3) && (i == 0)) |
| 739 | reg16 = (0x3 << 12); |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 740 | MCHBAR16_AND_OR(0x400*i + 0x59c, ~0x3000, reg16); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 741 | |
| 742 | reg32 = 0; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 743 | FOR_EACH_RANK_IN_CHANNEL(r) { |
| 744 | if (!RANK_IS_POPULATED(s->dimms, i, r)) |
| 745 | reg32 |= 0x111 << r; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 746 | } |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 747 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 748 | MCHBAR32_AND_OR(0x400*i + 0x59c, ~0xfff, reg32); |
| 749 | MCHBAR8_AND(0x400*i + 0x594, ~1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 750 | |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 751 | if (s->spd_type == DDR2) { |
| 752 | if (!CHANNEL_IS_POPULATED(s->dimms, i)) { |
| 753 | printk(BIOS_DEBUG, |
| 754 | "No dimms in channel %d\n", i); |
| 755 | reg8 = 0x3f; |
| 756 | } else if (ONLY_DIMMA_IS_POPULATED(s->dimms, i)) { |
| 757 | printk(BIOS_DEBUG, |
| 758 | "DimmA populated only in channel %d\n", |
| 759 | i); |
| 760 | reg8 = 0x38; |
| 761 | } else if (ONLY_DIMMB_IS_POPULATED(s->dimms, i)) { |
| 762 | printk(BIOS_DEBUG, |
| 763 | "DimmB populated only in channel %d\n", |
| 764 | i); |
| 765 | reg8 = 0x7; |
| 766 | } else if (BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { |
| 767 | printk(BIOS_DEBUG, |
| 768 | "Both dimms populated in channel %d\n", |
| 769 | i); |
| 770 | reg8 = 0; |
| 771 | } else { |
| 772 | die("Unhandled case\n"); |
| 773 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 774 | MCHBAR32_AND_OR(0x400*i + 0x5a0, ~0x3f000000, |
| 775 | (u32)(reg8 << 24)); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 776 | |
| 777 | } else { /* DDR3 */ |
| 778 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 779 | MCHBAR8_AND(0x400 * i + 0x5a0 + 3, |
| 780 | ~rank2clken[r + i * 4]); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 781 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 782 | } |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 783 | } /* END EACH CHANNEL */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 784 | |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 785 | if (s->spd_type == DDR2) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 786 | MCHBAR8_OR(0x1a8, 1); |
| 787 | MCHBAR8_AND(0x1a8, ~0x4); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 788 | } else { /* DDR3 */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 789 | MCHBAR8_AND(0x1a8, ~1); |
| 790 | MCHBAR8_OR(0x1a8, 0x4); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 791 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 792 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 793 | /* Update DLL timing */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 794 | MCHBAR8_AND(0x1a4, ~0x80); |
| 795 | MCHBAR8_OR(0x1a4, 0x40); |
| 796 | MCHBAR16_AND_OR(0x5f0, ~0x400, 0x400); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 797 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 798 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 799 | MCHBAR16_AND_OR(0x400*i + 0x5f0, ~0x3fc, 0x3fc); |
| 800 | MCHBAR32_AND(0x400*i + 0x5fc, ~0xcccccccc); |
| 801 | MCHBAR8_AND_OR(0x400*i + 0x5d9, ~0xf0, |
| 802 | s->spd_type == DDR2 ? 0x70 : 0x60); |
| 803 | MCHBAR16_AND_OR(0x400*i + 0x590, ~0xffff, |
| 804 | s->spd_type == DDR2 ? 0x5555 : 0xa955); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 805 | } |
| 806 | |
| 807 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Jonathan Neuschäfer | 7be74db | 2018-02-12 12:00:40 +0100 | [diff] [blame] | 808 | const struct dll_setting *setting; |
| 809 | |
Elyes HAOUAS | 0ce41f1 | 2018-11-13 10:03:31 +0100 | [diff] [blame] | 810 | switch (s->selected_timings.mem_clk) { |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 811 | default: /* Should not happen */ |
| 812 | case MEM_CLOCK_667MHz: |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 813 | setting = default_ddr2_667_ctrl; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 814 | break; |
| 815 | case MEM_CLOCK_800MHz: |
| 816 | if (s->spd_type == DDR2) |
| 817 | setting = default_ddr2_800_ctrl; |
| 818 | else |
| 819 | setting = default_ddr3_800_ctrl[s->nmode - 1]; |
| 820 | break; |
| 821 | case MEM_CLOCK_1066MHz: |
| 822 | setting = default_ddr3_1067_ctrl[s->nmode - 1]; |
| 823 | break; |
| 824 | case MEM_CLOCK_1333MHz: |
| 825 | setting = default_ddr3_1333_ctrl[s->nmode - 1]; |
| 826 | break; |
| 827 | } |
Jonathan Neuschäfer | 7be74db | 2018-02-12 12:00:40 +0100 | [diff] [blame] | 828 | |
| 829 | clkset0(i, &setting[CLKSET0]); |
| 830 | clkset1(i, &setting[CLKSET1]); |
| 831 | ctrlset0(i, &setting[CTRL0]); |
| 832 | ctrlset1(i, &setting[CTRL1]); |
| 833 | ctrlset2(i, &setting[CTRL2]); |
| 834 | ctrlset3(i, &setting[CTRL3]); |
| 835 | cmdset(i, &setting[CMD]); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 836 | } |
| 837 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 838 | /* XXX if not async mode */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 839 | MCHBAR16_AND(0x180, ~0x8200); |
| 840 | MCHBAR8_OR(0x180, 0x4); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 841 | j = 0; |
| 842 | for (i = 0; i < 16; i++) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 843 | MCHBAR8_AND_OR(0x1c8, ~0x1f, i); |
| 844 | MCHBAR8_OR(0x180, 0x10); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 845 | while (MCHBAR8(0x180) & 0x10) |
| 846 | ; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 847 | if (MCHBAR32(0x184) == 0xffffffff) { |
| 848 | j++; |
| 849 | if (j >= 2) |
| 850 | break; |
| 851 | |
| 852 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { |
| 853 | j = 2; |
| 854 | break; |
| 855 | } |
| 856 | } else { |
| 857 | j = 0; |
| 858 | } |
| 859 | } |
| 860 | if (i == 1 || ((i == 0) && s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { |
| 861 | j = 0; |
| 862 | i++; |
| 863 | for (; i < 16; i++) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 864 | MCHBAR8_AND_OR(0x1c8, ~0x1f, i); |
| 865 | MCHBAR8_OR(0x180, 0x4); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 866 | while (MCHBAR8(0x180) & 0x10) |
| 867 | ; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 868 | if (MCHBAR32(0x184) == 0) { |
| 869 | i++; |
| 870 | break; |
| 871 | } |
| 872 | } |
| 873 | for (; i < 16; i++) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 874 | MCHBAR8_AND_OR(0x1c8, ~0x1f, i); |
| 875 | MCHBAR8_OR(0x180, 0x10); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 876 | while (MCHBAR8(0x180) & 0x10) |
| 877 | ; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 878 | if (MCHBAR32(0x184) == 0xffffffff) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 879 | j++; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 880 | if (j >= 2) |
| 881 | break; |
| 882 | } else { |
| 883 | j = 0; |
| 884 | } |
| 885 | } |
| 886 | if (j < 2) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 887 | MCHBAR8_AND(0x1c8, ~0x1f); |
| 888 | MCHBAR8_OR(0x180, 0x10); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 889 | while (MCHBAR8(0x180) & 0x10) |
| 890 | ; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 891 | j = 2; |
| 892 | } |
| 893 | } |
| 894 | |
| 895 | if (j < 2) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 896 | MCHBAR8_AND(0x1c8, ~0x1f); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 897 | async = 1; |
Angel Pons | 6b17794 | 2021-01-13 17:00:48 +0100 | [diff] [blame] | 898 | printk(BIOS_NOTICE, "HMC failed, using async mode\n"); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 899 | } |
| 900 | |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 901 | switch (s->selected_timings.mem_clk) { |
| 902 | case MEM_CLOCK_667MHz: |
| 903 | clk = 0x1a; |
| 904 | if (async != 1) { |
| 905 | if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) |
| 906 | clk = 0x10; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 907 | } |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 908 | break; |
| 909 | case MEM_CLOCK_800MHz: |
| 910 | case MEM_CLOCK_1066MHz: |
| 911 | if (async != 1) |
| 912 | clk = 0x10; |
| 913 | else |
| 914 | clk = 0x1a; |
| 915 | break; |
| 916 | case MEM_CLOCK_1333MHz: |
| 917 | clk = 0x18; |
| 918 | break; |
| 919 | default: |
| 920 | clk = 0x1a; |
| 921 | break; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 922 | } |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 923 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 924 | MCHBAR8_AND(0x180, ~0x80); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 925 | |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 926 | if ((s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) |
| 927 | || (s->spd_type == DDR2 && s->selected_timings.fsb_clk == FSB_CLOCK_800MHz |
| 928 | && s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { |
Arthur Heymans | 24798a1 | 2017-08-13 16:02:09 +0200 | [diff] [blame] | 929 | i = MCHBAR8(0x1c8) & 0xf; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 930 | if (s->spd_type == DDR2) |
| 931 | i = (i + 10) % 14; |
| 932 | else /* DDR3 */ |
| 933 | i = (i + 3) % 12; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 934 | MCHBAR8_AND_OR(0x1c8, ~0x1f, i); |
| 935 | MCHBAR8_OR(0x180, 0x10); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 936 | while (MCHBAR8(0x180) & 0x10) |
| 937 | ; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 938 | } |
| 939 | |
| 940 | reg8 = MCHBAR8(0x188) & ~1; |
| 941 | MCHBAR8(0x188) = reg8; |
| 942 | reg8 &= ~0x3e; |
| 943 | reg8 |= clk; |
| 944 | MCHBAR8(0x188) = reg8; |
| 945 | reg8 |= 1; |
| 946 | MCHBAR8(0x188) = reg8; |
| 947 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 948 | if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 949 | MCHBAR8_OR(0x18c, 1); |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 950 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 951 | |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 952 | static void select_default_dq_dqs_settings(struct sysinfo *s) |
| 953 | { |
| 954 | int ch, lane; |
| 955 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 956 | FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(s->dimms, ch, lane) { |
| 957 | switch (s->selected_timings.mem_clk) { |
| 958 | case MEM_CLOCK_667MHz: |
| 959 | memcpy(s->dqs_settings[ch], |
| 960 | default_ddr2_667_dqs, |
| 961 | sizeof(s->dqs_settings[ch])); |
| 962 | memcpy(s->dq_settings[ch], |
| 963 | default_ddr2_667_dq, |
| 964 | sizeof(s->dq_settings[ch])); |
| 965 | s->rt_dqs[ch][lane].tap = 7; |
| 966 | s->rt_dqs[ch][lane].pi = 2; |
| 967 | break; |
| 968 | case MEM_CLOCK_800MHz: |
| 969 | if (s->spd_type == DDR2) { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 970 | memcpy(s->dqs_settings[ch], |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 971 | default_ddr2_800_dqs, |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 972 | sizeof(s->dqs_settings[ch])); |
| 973 | memcpy(s->dq_settings[ch], |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 974 | default_ddr2_800_dq, |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 975 | sizeof(s->dq_settings[ch])); |
| 976 | s->rt_dqs[ch][lane].tap = 7; |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 977 | s->rt_dqs[ch][lane].pi = 0; |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 978 | } else { /* DDR3 */ |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 979 | memcpy(s->dqs_settings[ch], |
| 980 | default_ddr3_800_dqs[s->nmode - 1], |
| 981 | sizeof(s->dqs_settings[ch])); |
| 982 | memcpy(s->dq_settings[ch], |
| 983 | default_ddr3_800_dq[s->nmode - 1], |
| 984 | sizeof(s->dq_settings[ch])); |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 985 | s->rt_dqs[ch][lane].tap = 6; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 986 | s->rt_dqs[ch][lane].pi = 3; |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 987 | } |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 988 | break; |
| 989 | case MEM_CLOCK_1066MHz: |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 990 | memcpy(s->dqs_settings[ch], |
| 991 | default_ddr3_1067_dqs[s->nmode - 1], |
| 992 | sizeof(s->dqs_settings[ch])); |
| 993 | memcpy(s->dq_settings[ch], |
| 994 | default_ddr3_1067_dq[s->nmode - 1], |
| 995 | sizeof(s->dq_settings[ch])); |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 996 | s->rt_dqs[ch][lane].tap = 5; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 997 | s->rt_dqs[ch][lane].pi = 3; |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 998 | break; |
| 999 | case MEM_CLOCK_1333MHz: |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 1000 | memcpy(s->dqs_settings[ch], |
| 1001 | default_ddr3_1333_dqs[s->nmode - 1], |
| 1002 | sizeof(s->dqs_settings[ch])); |
| 1003 | memcpy(s->dq_settings[ch], |
| 1004 | default_ddr3_1333_dq[s->nmode - 1], |
| 1005 | sizeof(s->dq_settings[ch])); |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 1006 | s->rt_dqs[ch][lane].tap = 7; |
| 1007 | s->rt_dqs[ch][lane].pi = 0; |
| 1008 | break; |
| 1009 | default: /* not supported */ |
| 1010 | break; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1011 | } |
| 1012 | } |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 1013 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1014 | |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 1015 | /* |
| 1016 | * It looks like only the RT DQS register for the first rank |
| 1017 | * is used for all ranks. Just set all the 'unused' RT DQS registers |
| 1018 | * to the same as rank 0, out of precaution. |
| 1019 | */ |
| 1020 | static void set_all_dq_dqs_dll_settings(struct sysinfo *s) |
| 1021 | { |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1022 | /* Program DQ/DQS dll settings */ |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 1023 | int ch, lane, rank; |
| 1024 | |
| 1025 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 1026 | FOR_EACH_BYTELANE(lane) { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 1027 | FOR_EACH_RANK_IN_CHANNEL(rank) { |
| 1028 | rt_set_dqs(ch, lane, rank, |
| 1029 | &s->rt_dqs[ch][lane]); |
| 1030 | } |
| 1031 | dqsset(ch, lane, &s->dqs_settings[ch][lane]); |
| 1032 | dqset(ch, lane, &s->dq_settings[ch][lane]); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1033 | } |
| 1034 | } |
| 1035 | } |
| 1036 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1037 | static void prog_rcomp(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1038 | { |
Arthur Heymans | 0d1c9b0 | 2017-05-15 10:40:42 +0200 | [diff] [blame] | 1039 | u8 i, j, k, reg8; |
Angel Pons | 7d3bd6b | 2021-01-13 17:57:39 +0100 | [diff] [blame] | 1040 | const u32 ddr2_x32a[8] = { 0x04040404, 0x06050505, 0x09090807, 0x0d0c0b0a, |
| 1041 | 0x04040404, 0x08070605, 0x0c0b0a09, 0x100f0e0d }; |
| 1042 | const u16 ddr2_x378[5] = { 0xaaaa, 0x7777, 0x7777, 0x7777, 0x7777 }; |
Angel Pons | a0b97f3 | 2021-01-13 17:50:27 +0100 | [diff] [blame] | 1043 | const u32 ddr2_x382[5] = { 0x02020202, 0x02020202, 0x02020202, 0x04030303, 0x04030303 }; |
| 1044 | const u32 ddr2_x386[5] = { 0x03020202, 0x03020202, 0x03020202, 0x05040404, 0x05040404 }; |
| 1045 | const u32 ddr2_x38a[5] = { 0x04040303, 0x04040303, 0x04040303, 0x07070605, 0x07070605 }; |
| 1046 | const u32 ddr2_x38e[5] = { 0x06060505, 0x06060505, 0x06060505, 0x09090808, 0x09090808 }; |
| 1047 | const u32 ddr2_x392[5] = { 0x02020202, 0x02020202, 0x02020202, 0x03030202, 0x03030202 }; |
| 1048 | const u32 ddr2_x396[5] = { 0x03030202, 0x03030202, 0x03030202, 0x05040303, 0x05040303 }; |
| 1049 | const u32 ddr2_x39a[5] = { 0x04040403, 0x04040403, 0x04040403, 0x07070605, 0x07070605 }; |
| 1050 | const u32 ddr2_x39e[5] = { 0x06060505, 0x06060505, 0x06060505, 0x08080808, 0x08080808 }; |
Arthur Heymans | 0d1c9b0 | 2017-05-15 10:40:42 +0200 | [diff] [blame] | 1051 | |
Angel Pons | 7d3bd6b | 2021-01-13 17:57:39 +0100 | [diff] [blame] | 1052 | const u32 ddr3_x32a[8] = { 0x06060606, 0x06060606, 0x0b090807, 0x12110f0d, |
| 1053 | 0x06060606, 0x08070606, 0x0d0b0a09, 0x16161511 }; |
| 1054 | const u16 ddr3_x378[5] = { 0xbbbb, 0x6666, 0x6666, 0x6666, 0x6666 }; |
| 1055 | const u32 ddr3_x382[5] = { 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434 }; |
| 1056 | const u32 ddr3_x386[5] = { 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434 }; |
| 1057 | const u32 ddr3_x38a[5] = { 0x06060605, 0x07060504, 0x07060504, 0x34343434, 0x34343434 }; |
| 1058 | const u32 ddr3_x38e[5] = { 0x09080707, 0x09090808, 0x09090808, 0x34343434, 0x34343434 }; |
| 1059 | const u32 ddr3_x392[5] = { 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434 }; |
| 1060 | const u32 ddr3_x396[5] = { 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434 }; |
| 1061 | const u32 ddr3_x39a[5] = { 0x07060606, 0x08070605, 0x08070605, 0x34343434, 0x34343434 }; |
| 1062 | const u32 ddr3_x39e[5] = { 0x09090807, 0x0b0b0a09, 0x0b0b0a09, 0x34343434, 0x34343434 }; |
Arthur Heymans | 0d1c9b0 | 2017-05-15 10:40:42 +0200 | [diff] [blame] | 1063 | |
| 1064 | const u16 *x378; |
| 1065 | const u32 *x32a, *x382, *x386, *x38a, *x38e; |
| 1066 | const u32 *x392, *x396, *x39a, *x39e; |
| 1067 | |
Angel Pons | a0b97f3 | 2021-01-13 17:50:27 +0100 | [diff] [blame] | 1068 | const u16 addr[5] = { 0x374, 0x3a2, 0x3d0, 0x3fe, 0x42c }; |
Angel Pons | 7d3bd6b | 2021-01-13 17:57:39 +0100 | [diff] [blame] | 1069 | const u8 bit[5] = { 0, 1, 1, 0, 0 }; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1070 | |
Arthur Heymans | 0d1c9b0 | 2017-05-15 10:40:42 +0200 | [diff] [blame] | 1071 | if (s->spd_type == DDR2) { |
| 1072 | x32a = ddr2_x32a; |
| 1073 | x378 = ddr2_x378; |
| 1074 | x382 = ddr2_x382; |
| 1075 | x386 = ddr2_x386; |
| 1076 | x38a = ddr2_x38a; |
| 1077 | x38e = ddr2_x38e; |
| 1078 | x392 = ddr2_x392; |
| 1079 | x396 = ddr2_x396; |
| 1080 | x39a = ddr2_x39a; |
| 1081 | x39e = ddr2_x39e; |
| 1082 | } else { /* DDR3 */ |
| 1083 | x32a = ddr3_x32a; |
| 1084 | x378 = ddr3_x378; |
| 1085 | x382 = ddr3_x382; |
| 1086 | x386 = ddr3_x386; |
| 1087 | x38a = ddr3_x38a; |
| 1088 | x38e = ddr3_x38e; |
| 1089 | x392 = ddr3_x392; |
| 1090 | x396 = ddr3_x396; |
| 1091 | x39a = ddr3_x39a; |
| 1092 | x39e = ddr3_x39e; |
| 1093 | } |
| 1094 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1095 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Angel Pons | 244391a | 2021-01-13 17:28:31 +0100 | [diff] [blame] | 1096 | /* RCOMP data group is special, program it separately */ |
Angel Pons | 7d3bd6b | 2021-01-13 17:57:39 +0100 | [diff] [blame] | 1097 | MCHBAR32_AND_OR(0x400*i + 0x31c, ~0xff000, 0xaa000); |
| 1098 | MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff, 0x6666); |
Angel Pons | 244391a | 2021-01-13 17:28:31 +0100 | [diff] [blame] | 1099 | for (k = 0; k < 8; k++) { |
Angel Pons | 7d3bd6b | 2021-01-13 17:57:39 +0100 | [diff] [blame] | 1100 | MCHBAR32_AND_OR(0x400*i + 0x32a + (k << 2), ~0x3f3f3f3f, x32a[k]); |
| 1101 | MCHBAR32_AND_OR(0x400*i + 0x34a + (k << 2), ~0x3f3f3f3f, x32a[k]); |
Angel Pons | 244391a | 2021-01-13 17:28:31 +0100 | [diff] [blame] | 1102 | } |
| 1103 | MCHBAR8_AND_OR(0x400*i + 0x31c, ~1, 0); |
| 1104 | |
| 1105 | /* Now program the other RCOMP groups */ |
Angel Pons | a0b97f3 | 2021-01-13 17:50:27 +0100 | [diff] [blame] | 1106 | for (j = 0; j < ARRAY_SIZE(addr); j++) { |
Angel Pons | 7d3bd6b | 2021-01-13 17:57:39 +0100 | [diff] [blame] | 1107 | MCHBAR16_AND_OR(0x400*i + addr[j] + 0, ~0xf000, 0xa000); |
| 1108 | MCHBAR16_AND_OR(0x400*i + addr[j] + 4, ~0xffff, x378[j]); |
| 1109 | |
| 1110 | MCHBAR32_AND_OR(0x400*i + addr[j] + 0x0e, ~0x3f3f3f3f, x382[j]); |
| 1111 | MCHBAR32_AND_OR(0x400*i + addr[j] + 0x12, ~0x3f3f3f3f, x386[j]); |
| 1112 | MCHBAR32_AND_OR(0x400*i + addr[j] + 0x16, ~0x3f3f3f3f, x38a[j]); |
| 1113 | MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1a, ~0x3f3f3f3f, x38e[j]); |
| 1114 | MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1e, ~0x3f3f3f3f, x392[j]); |
| 1115 | MCHBAR32_AND_OR(0x400*i + addr[j] + 0x22, ~0x3f3f3f3f, x396[j]); |
| 1116 | MCHBAR32_AND_OR(0x400*i + addr[j] + 0x26, ~0x3f3f3f3f, x39a[j]); |
| 1117 | MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a, ~0x3f3f3f3f, x39e[j]); |
Angel Pons | 244391a | 2021-01-13 17:28:31 +0100 | [diff] [blame] | 1118 | |
| 1119 | /* Override command group strength multiplier */ |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 1120 | if (s->spd_type == DDR3 && |
| 1121 | BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { |
Angel Pons | 7d3bd6b | 2021-01-13 17:57:39 +0100 | [diff] [blame] | 1122 | MCHBAR16_AND_OR(0x378 + 0x400 * i, ~0xffff, 0xcccc); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1123 | } |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 1124 | MCHBAR8_AND_OR(0x400*i + addr[j], ~1, bit[j]); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1125 | } |
Arthur Heymans | 0d1c9b0 | 2017-05-15 10:40:42 +0200 | [diff] [blame] | 1126 | reg8 = (s->spd_type == DDR2) ? 0x12 : 0x36; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1127 | MCHBAR8_AND_OR(0x400*i + 0x45a, ~0x3f, reg8); |
| 1128 | MCHBAR8_AND_OR(0x400*i + 0x45e, ~0x3f, reg8); |
| 1129 | MCHBAR8_AND_OR(0x400*i + 0x462, ~0x3f, reg8); |
| 1130 | MCHBAR8_AND_OR(0x400*i + 0x466, ~0x3f, reg8); |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1131 | } /* END EACH POPULATED CHANNEL */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1132 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1133 | MCHBAR32_AND_OR(0x134, ~0x63c00, 0x63c00); |
| 1134 | MCHBAR16_AND_OR(0x174, ~0x63ff, 0x63ff); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1135 | MCHBAR16(0x178) = 0x0135; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1136 | MCHBAR32_AND_OR(0x130, ~0x7bdffe0, 0x7a9ffa0); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1137 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1138 | if (!CHANNEL_IS_POPULATED(s->dimms, 0)) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1139 | MCHBAR32_AND(0x130, ~(1 << 27)); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1140 | if (!CHANNEL_IS_POPULATED(s->dimms, 1)) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1141 | MCHBAR32_AND(0x130, ~(1 << 28)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1142 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1143 | MCHBAR8_OR(0x130, 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1144 | } |
| 1145 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1146 | static void program_odt(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1147 | { |
| 1148 | u8 i; |
Angel Pons | b35adab | 2021-01-13 18:08:58 +0100 | [diff] [blame] | 1149 | static const u16 ddr2_odt[16][2] = { |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1150 | { 0x0000, 0x0000 }, /* NC_NC */ |
| 1151 | { 0x0000, 0x0001 }, /* x8SS_NC */ |
| 1152 | { 0x0000, 0x0011 }, /* x8DS_NC */ |
| 1153 | { 0x0000, 0x0001 }, /* x16SS_NC */ |
| 1154 | { 0x0004, 0x0000 }, /* NC_x8SS */ |
| 1155 | { 0x0101, 0x0404 }, /* x8SS_x8SS */ |
| 1156 | { 0x0101, 0x4444 }, /* x8DS_x8SS */ |
| 1157 | { 0x0101, 0x0404 }, /* x16SS_x8SS */ |
| 1158 | { 0x0044, 0x0000 }, /* NC_x8DS */ |
| 1159 | { 0x1111, 0x0404 }, /* x8SS_x8DS */ |
| 1160 | { 0x1111, 0x4444 }, /* x8DS_x8DS */ |
| 1161 | { 0x1111, 0x0404 }, /* x16SS_x8DS */ |
| 1162 | { 0x0004, 0x0000 }, /* NC_x16SS */ |
| 1163 | { 0x0101, 0x0404 }, /* x8SS_x16SS */ |
| 1164 | { 0x0101, 0x4444 }, /* x8DS_x16SS */ |
| 1165 | { 0x0101, 0x0404 }, /* x16SS_x16SS */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1166 | }; |
| 1167 | |
Arthur Heymans | e6cc21e | 2017-05-15 10:43:20 +0200 | [diff] [blame] | 1168 | static const u16 ddr3_odt[16][2] = { |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1169 | { 0x0000, 0x0000 }, /* NC_NC */ |
| 1170 | { 0x0000, 0x0001 }, /* x8SS_NC */ |
| 1171 | { 0x0000, 0x0021 }, /* x8DS_NC */ |
| 1172 | { 0x0000, 0x0001 }, /* x16SS_NC */ |
| 1173 | { 0x0004, 0x0000 }, /* NC_x8SS */ |
| 1174 | { 0x0105, 0x0405 }, /* x8SS_x8SS */ |
| 1175 | { 0x0105, 0x4465 }, /* x8DS_x8SS */ |
| 1176 | { 0x0105, 0x0405 }, /* x16SS_x8SS */ |
| 1177 | { 0x0084, 0x0000 }, /* NC_x8DS */ |
| 1178 | { 0x1195, 0x0405 }, /* x8SS_x8DS */ |
| 1179 | { 0x1195, 0x4465 }, /* x8DS_x8DS */ |
| 1180 | { 0x1195, 0x0405 }, /* x16SS_x8DS */ |
| 1181 | { 0x0004, 0x0000 }, /* NC_x16SS */ |
| 1182 | { 0x0105, 0x0405 }, /* x8SS_x16SS */ |
| 1183 | { 0x0105, 0x4465 }, /* x8DS_x16SS */ |
| 1184 | { 0x0105, 0x0405 }, /* x16SS_x16SS */ |
Arthur Heymans | e6cc21e | 2017-05-15 10:43:20 +0200 | [diff] [blame] | 1185 | }; |
| 1186 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1187 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Arthur Heymans | e6cc21e | 2017-05-15 10:43:20 +0200 | [diff] [blame] | 1188 | if (s->spd_type == DDR2) { |
| 1189 | MCHBAR16(0x400 * i + 0x298) = |
| 1190 | ddr2_odt[s->dimm_config[i]][1]; |
| 1191 | MCHBAR16(0x400 * i + 0x294) = |
| 1192 | ddr2_odt[s->dimm_config[i]][0]; |
| 1193 | } else { |
| 1194 | MCHBAR16(0x400 * i + 0x298) = |
| 1195 | ddr3_odt[s->dimm_config[i]][1]; |
| 1196 | MCHBAR16(0x400 * i + 0x294) = |
| 1197 | ddr3_odt[s->dimm_config[i]][0]; |
| 1198 | } |
| 1199 | u16 reg16 = MCHBAR16(0x400*i + 0x29c); |
| 1200 | reg16 &= ~0xfff; |
| 1201 | reg16 |= (s->spd_type == DDR2 ? 0x66b : 0x778); |
| 1202 | MCHBAR16(0x400*i + 0x29c) = reg16; |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 1203 | MCHBAR32_AND_OR(0x400*i + 0x260, ~0x70e3c00, 0x3063c00); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1204 | } |
| 1205 | } |
| 1206 | |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1207 | static void pre_jedec_memory_map(void) |
| 1208 | { |
| 1209 | /* |
| 1210 | * Configure the memory mapping in stacked mode (channel 1 being mapped |
| 1211 | * above channel 0) and with 128M per rank. |
| 1212 | * This simplifies dram trainings a lot since those need a test address. |
| 1213 | * |
| 1214 | * +-------------+ => 0 |
| 1215 | * | ch 0, rank 0| |
| 1216 | * +-------------+ => 0x8000000 (128M) |
| 1217 | * | ch 0, rank 1| |
| 1218 | * +-------------+ => 0x10000000 (256M) |
| 1219 | * | ch 0, rank 2| |
| 1220 | * +-------------+ => 0x18000000 (384M) |
| 1221 | * | ch 0, rank 3| |
| 1222 | * +-------------+ => 0x20000000 (512M) |
| 1223 | * | ch 1, rank 0| |
| 1224 | * +-------------+ => 0x28000000 (640M) |
| 1225 | * | ch 1, rank 1| |
| 1226 | * +-------------+ => 0x30000000 (768M) |
| 1227 | * | ch 1, rank 2| |
| 1228 | * +-------------+ => 0x38000000 (896M) |
| 1229 | * | ch 1, rank 3| |
| 1230 | * +-------------+ |
| 1231 | * |
| 1232 | * After all trainings are done this is set to the real values specified |
| 1233 | * by the SPD. |
| 1234 | */ |
| 1235 | /* Set rank 0-3 populated */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1236 | MCHBAR32_AND_OR(C0CKECTRL, ~1, 0xf00000); |
| 1237 | MCHBAR32_AND_OR(C1CKECTRL, ~1, 0xf00000); |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1238 | /* Set size of each rank to 128M */ |
| 1239 | MCHBAR16(C0DRA01) = 0x0101; |
| 1240 | MCHBAR16(C0DRA23) = 0x0101; |
| 1241 | MCHBAR16(C1DRA01) = 0x0101; |
| 1242 | MCHBAR16(C1DRA23) = 0x0101; |
| 1243 | MCHBAR16(C0DRB0) = 0x0002; |
| 1244 | MCHBAR16(C0DRB1) = 0x0004; |
| 1245 | MCHBAR16(C0DRB2) = 0x0006; |
| 1246 | MCHBAR16(C0DRB3) = 0x0008; |
| 1247 | MCHBAR16(C1DRB0) = 0x0002; |
| 1248 | MCHBAR16(C1DRB1) = 0x0004; |
| 1249 | MCHBAR16(C1DRB2) = 0x0006; |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1250 | /* In stacked mode the last present rank on ch1 needs to have its |
| 1251 | size doubled in c1drbx */ |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1252 | MCHBAR16(C1DRB3) = 0x0010; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1253 | MCHBAR8_OR(0x111, STACKED_MEM); |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1254 | MCHBAR32(0x104) = 0; |
| 1255 | MCHBAR16(0x102) = 0x400; |
| 1256 | MCHBAR8(0x110) = (2 << 5) | (3 << 3); |
| 1257 | MCHBAR16(0x10e) = 0; |
| 1258 | MCHBAR32(0x108) = 0; |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1259 | pci_write_config16(HOST_BRIDGE, D0F0_TOLUD, 0x4000); |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1260 | /* TOM(64M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */ |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1261 | pci_write_config16(HOST_BRIDGE, D0F0_TOM, 0x10); |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1262 | /* TOUUD(1M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */ |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1263 | pci_write_config16(HOST_BRIDGE, D0F0_TOUUD, 0x0400); |
| 1264 | pci_write_config32(HOST_BRIDGE, D0F0_GBSM, 0x40000000); |
| 1265 | pci_write_config32(HOST_BRIDGE, D0F0_BGSM, 0x40000000); |
| 1266 | pci_write_config32(HOST_BRIDGE, D0F0_TSEG, 0x40000000); |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1267 | } |
| 1268 | |
| 1269 | u32 test_address(int channel, int rank) |
| 1270 | { |
| 1271 | ASSERT(channel <= 1 && rank < 4); |
| 1272 | return channel * 512 * MiB + rank * 128 * MiB; |
| 1273 | } |
| 1274 | |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1275 | /* DDR3 Rank1 Address mirror |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1276 | swap the following pins: |
| 1277 | A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1278 | static u32 mirror_shift_bit(const u32 data, u8 bit) |
| 1279 | { |
| 1280 | u32 temp0 = data, temp1 = data; |
| 1281 | temp0 &= 1 << bit; |
| 1282 | temp0 <<= 1; |
| 1283 | temp1 &= 1 << (bit + 1); |
| 1284 | temp1 >>= 1; |
| 1285 | return (data & ~(3 << bit)) | temp0 | temp1; |
| 1286 | } |
| 1287 | |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 1288 | void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1289 | { |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1290 | u32 addr = test_address(ch, r); |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1291 | u8 data8 = cmd; |
| 1292 | u32 data32; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1293 | |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1294 | if (s->spd_type == DDR3 && (r & 1) |
| 1295 | && s->dimms[ch * 2 + (r >> 1)].mirrored) { |
| 1296 | data8 = (u8)mirror_shift_bit(data8, 4); |
| 1297 | } |
| 1298 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1299 | MCHBAR8_AND_OR(0x271, ~0x3e, data8); |
| 1300 | MCHBAR8_AND_OR(0x671, ~0x3e, data8); |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1301 | data32 = val; |
| 1302 | if (s->spd_type == DDR3 && (r & 1) |
| 1303 | && s->dimms[ch * 2 + (r >> 1)].mirrored) { |
| 1304 | data32 = mirror_shift_bit(data32, 3); |
| 1305 | data32 = mirror_shift_bit(data32, 5); |
| 1306 | data32 = mirror_shift_bit(data32, 7); |
| 1307 | } |
| 1308 | data32 <<= 3; |
| 1309 | |
Elyes HAOUAS | c53665c | 2019-05-22 20:06:30 +0200 | [diff] [blame] | 1310 | read32((void *)((data32 | addr))); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1311 | udelay(10); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1312 | MCHBAR8_AND_OR(0x271, ~0x3e, NORMALOP_CMD); |
| 1313 | MCHBAR8_AND_OR(0x671, ~0x3e, NORMALOP_CMD); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1314 | } |
| 1315 | |
| 1316 | static void jedec_ddr2(struct sysinfo *s) |
| 1317 | { |
| 1318 | u8 i; |
| 1319 | u16 mrsval, ch, r, v; |
| 1320 | |
| 1321 | u8 odt[16][4] = { |
| 1322 | {0x00, 0x00, 0x00, 0x00}, |
| 1323 | {0x01, 0x00, 0x00, 0x00}, |
| 1324 | {0x01, 0x01, 0x00, 0x00}, |
| 1325 | {0x01, 0x00, 0x00, 0x00}, |
| 1326 | {0x00, 0x00, 0x01, 0x00}, |
| 1327 | {0x11, 0x00, 0x11, 0x00}, |
| 1328 | {0x11, 0x11, 0x11, 0x00}, |
| 1329 | {0x11, 0x00, 0x11, 0x00}, |
| 1330 | {0x00, 0x00, 0x01, 0x01}, |
| 1331 | {0x11, 0x00, 0x11, 0x11}, |
| 1332 | {0x11, 0x11, 0x11, 0x11}, |
| 1333 | {0x11, 0x00, 0x11, 0x11}, |
| 1334 | {0x00, 0x00, 0x01, 0x00}, |
| 1335 | {0x11, 0x00, 0x11, 0x00}, |
| 1336 | {0x11, 0x11, 0x11, 0x00}, |
| 1337 | {0x11, 0x00, 0x11, 0x00} |
| 1338 | }; |
| 1339 | |
| 1340 | u16 jedec[12][2] = { |
| 1341 | {NOP_CMD, 0x0}, |
| 1342 | {PRECHARGE_CMD, 0x0}, |
| 1343 | {EMRS2_CMD, 0x0}, |
| 1344 | {EMRS3_CMD, 0x0}, |
| 1345 | {EMRS1_CMD, 0x0}, |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1346 | {MRS_CMD, 0x100}, /* DLL Reset */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1347 | {PRECHARGE_CMD, 0x0}, |
| 1348 | {CBR_CMD, 0x0}, |
| 1349 | {CBR_CMD, 0x0}, |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1350 | {MRS_CMD, 0x0}, /* DLL out of reset */ |
| 1351 | {EMRS1_CMD, 0x380}, /* OCD calib default */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1352 | {EMRS1_CMD, 0x0} |
| 1353 | }; |
| 1354 | |
| 1355 | mrsval = (s->selected_timings.CAS << 4) | ((s->selected_timings.tWR - 1) << 9) | 0xb; |
| 1356 | |
| 1357 | printk(BIOS_DEBUG, "MRS...\n"); |
| 1358 | |
| 1359 | udelay(200); |
| 1360 | |
| 1361 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
| 1362 | printk(BIOS_DEBUG, "CH%d: Found Rank %d\n", ch, r); |
| 1363 | for (i = 0; i < 12; i++) { |
| 1364 | v = jedec[i][1]; |
| 1365 | switch (jedec[i][0]) { |
| 1366 | case EMRS1_CMD: |
| 1367 | v |= (odt[s->dimm_config[ch]][r] << 2); |
| 1368 | break; |
| 1369 | case MRS_CMD: |
| 1370 | v |= mrsval; |
| 1371 | break; |
| 1372 | default: |
| 1373 | break; |
| 1374 | } |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1375 | send_jedec_cmd(s, r, ch, jedec[i][0], v); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1376 | udelay(1); |
Arthur Heymans | cfa2eaa | 2017-03-20 16:32:07 +0100 | [diff] [blame] | 1377 | printk(RAM_SPEW, "Jedec step %d\n", i); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1378 | } |
| 1379 | } |
| 1380 | printk(BIOS_DEBUG, "MRS done\n"); |
| 1381 | } |
| 1382 | |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1383 | static void jedec_ddr3(struct sysinfo *s) |
| 1384 | { |
| 1385 | int ch, r, dimmconfig, cmd, ddr3_freq; |
| 1386 | |
| 1387 | u8 ddr3_emrs2_rtt_wr_config[16][4] = { /* [config][Rank] */ |
| 1388 | {0, 0, 0, 0}, /* NC_NC */ |
| 1389 | {0, 0, 0, 0}, /* x8ss_NC */ |
| 1390 | {0, 0, 0, 0}, /* x8ds_NC */ |
| 1391 | {0, 0, 0, 0}, /* x16ss_NC */ |
| 1392 | {0, 0, 0, 0}, /* NC_x8ss */ |
| 1393 | {2, 0, 2, 0}, /* x8ss_x8ss */ |
| 1394 | {2, 2, 2, 0}, /* x8ds_x8ss */ |
| 1395 | {2, 0, 2, 0}, /* x16ss_x8ss */ |
| 1396 | {0, 0, 0, 0}, /* NC_x8ss */ |
| 1397 | {2, 0, 2, 2}, /* x8ss_x8ds */ |
| 1398 | {2, 2, 2, 2}, /* x8ds_x8ds */ |
| 1399 | {2, 0, 2, 2}, /* x16ss_x8ds */ |
| 1400 | {0, 0, 0, 0}, /* NC_x16ss */ |
| 1401 | {2, 0, 2, 0}, /* x8ss_x16ss */ |
| 1402 | {2, 2, 2, 0}, /* x8ds_x16ss */ |
| 1403 | {2, 0, 2, 0}, /* x16ss_x16ss */ |
| 1404 | }; |
| 1405 | |
| 1406 | printk(BIOS_DEBUG, "MRS...\n"); |
| 1407 | |
| 1408 | ddr3_freq = s->selected_timings.mem_clk - MEM_CLOCK_800MHz; |
| 1409 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
| 1410 | printk(BIOS_DEBUG, "CH%d: Found Rank %d\n", ch, r); |
| 1411 | send_jedec_cmd(s, r, ch, NOP_CMD, 0); |
| 1412 | udelay(200); |
| 1413 | dimmconfig = s->dimm_config[ch]; |
| 1414 | cmd = ddr3_freq << 3; /* actually twl - 5 which is same */ |
| 1415 | cmd |= ddr3_emrs2_rtt_wr_config[dimmconfig][r] << 9; |
| 1416 | send_jedec_cmd(s, r, ch, EMRS2_CMD, cmd); |
| 1417 | send_jedec_cmd(s, r, ch, EMRS3_CMD, 0); |
| 1418 | cmd = ddr3_emrs1_rtt_nom_config[dimmconfig][r] << 2; |
| 1419 | /* Hardcode output drive strength to 34 Ohm / RZQ/7 (why??) */ |
| 1420 | cmd |= (1 << 1); |
| 1421 | send_jedec_cmd(s, r, ch, EMRS1_CMD, cmd); |
| 1422 | /* Burst type interleaved, burst length 8, Reset DLL, |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1423 | Precharge PD: DLL on */ |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1424 | send_jedec_cmd(s, r, ch, MRS_CMD, (1 << 3) | (1 << 8) |
| 1425 | | (1 << 12) | ((s->selected_timings.CAS - 4) << 4) |
| 1426 | | ((s->selected_timings.tWR - 4) << 9)); |
| 1427 | send_jedec_cmd(s, r, ch, ZQCAL_CMD, (1 << 10)); |
| 1428 | } |
| 1429 | printk(BIOS_DEBUG, "MRS done\n"); |
| 1430 | } |
| 1431 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1432 | static void sdram_recover_receive_enable(const struct sysinfo *s) |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1433 | { |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1434 | u32 reg32; |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1435 | u16 medium, coarse_offset; |
| 1436 | u8 pi_tap; |
| 1437 | int lane, channel; |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1438 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1439 | FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) { |
| 1440 | medium = 0; |
| 1441 | coarse_offset = 0; |
| 1442 | reg32 = MCHBAR32(0x400 * channel + 0x248); |
| 1443 | reg32 &= ~0xf0000; |
| 1444 | reg32 |= s->rcven_t[channel].min_common_coarse << 16; |
| 1445 | MCHBAR32(0x400 * channel + 0x248) = reg32; |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1446 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 1447 | FOR_EACH_BYTELANE(lane) { |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1448 | medium |= s->rcven_t[channel].medium[lane] |
| 1449 | << (lane * 2); |
| 1450 | coarse_offset |= |
| 1451 | (s->rcven_t[channel].coarse_offset[lane] & 0x3) |
| 1452 | << (lane * 2); |
| 1453 | |
| 1454 | pi_tap = MCHBAR8(0x400 * channel + 0x560 + lane * 4); |
| 1455 | pi_tap &= ~0x7f; |
| 1456 | pi_tap |= s->rcven_t[channel].tap[lane]; |
| 1457 | pi_tap |= s->rcven_t[channel].pi[lane] << 4; |
| 1458 | MCHBAR8(0x400 * channel + 0x560 + lane * 4) = pi_tap; |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1459 | } |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1460 | MCHBAR16(0x400 * channel + 0x58c) = medium; |
| 1461 | MCHBAR16(0x400 * channel + 0x5fa) = coarse_offset; |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1462 | } |
| 1463 | } |
| 1464 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1465 | static void sdram_program_receive_enable(struct sysinfo *s, int fast_boot) |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1466 | { |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1467 | /* Program Receive Enable Timings */ |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1468 | if (fast_boot) |
| 1469 | sdram_recover_receive_enable(s); |
| 1470 | else |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 1471 | rcven(s); |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1472 | } |
| 1473 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1474 | static void set_dradrb(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1475 | { |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1476 | u8 map, i, ch, r, rankpop0, rankpop1, lastrank_ch1; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1477 | u32 c0dra = 0; |
| 1478 | u32 c1dra = 0; |
| 1479 | u32 c0drb = 0; |
| 1480 | u32 c1drb = 0; |
| 1481 | u32 dra; |
| 1482 | u32 dra0; |
| 1483 | u32 dra1; |
| 1484 | u16 totalmemorymb; |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1485 | u32 dual_channel_size, single_channel_size, single_channel_offset; |
| 1486 | u32 size_ch0, size_ch1, size_me; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1487 | u8 dratab[2][2][2][4] = { |
| 1488 | { |
| 1489 | { |
| 1490 | {0xff, 0xff, 0xff, 0xff}, |
| 1491 | {0xff, 0x00, 0x02, 0xff} |
| 1492 | }, |
| 1493 | { |
| 1494 | {0xff, 0x01, 0xff, 0xff}, |
| 1495 | {0xff, 0x03, 0xff, 0xff} |
| 1496 | } |
| 1497 | }, |
| 1498 | { |
| 1499 | { |
| 1500 | {0xff, 0xff, 0xff, 0xff}, |
| 1501 | {0xff, 0x04, 0x06, 0x08} |
| 1502 | }, |
| 1503 | { |
| 1504 | {0xff, 0xff, 0xff, 0xff}, |
| 1505 | {0x05, 0x07, 0x09, 0xff} |
| 1506 | } |
| 1507 | } |
| 1508 | }; |
| 1509 | |
| 1510 | u8 drbtab[10] = {0x04, 0x02, 0x08, 0x04, 0x08, 0x04, 0x10, 0x08, 0x20, 0x10}; |
| 1511 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1512 | /* DRA */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1513 | rankpop0 = 0; |
| 1514 | rankpop1 = 0; |
| 1515 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1516 | if (s->dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED |
| 1517 | && (r) < s->dimms[ch<<1].ranks) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1518 | i = ch << 1; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1519 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1520 | i = (ch << 1) + 1; |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 1521 | |
| 1522 | dra = dratab[s->dimms[i].n_banks] |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1523 | [s->dimms[i].width] |
| 1524 | [s->dimms[i].cols-9] |
| 1525 | [s->dimms[i].rows-12]; |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 1526 | if (s->dimms[i].n_banks == N_BANKS_8) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1527 | dra |= 0x80; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1528 | if (ch == 0) { |
| 1529 | c0dra |= dra << (r*8); |
| 1530 | rankpop0 |= 1 << r; |
| 1531 | } else { |
| 1532 | c1dra |= dra << (r*8); |
| 1533 | rankpop1 |= 1 << r; |
| 1534 | } |
| 1535 | } |
| 1536 | MCHBAR32(0x208) = c0dra; |
| 1537 | MCHBAR32(0x608) = c1dra; |
| 1538 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1539 | MCHBAR8_AND_OR(0x262, ~0xf0, (rankpop0 << 4) & 0xf0); |
| 1540 | MCHBAR8_AND_OR(0x662, ~0xf0, (rankpop1 << 4) & 0xf0); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1541 | |
Arthur Heymans | b4a7804 | 2017-12-25 20:17:41 +0100 | [diff] [blame] | 1542 | if (s->spd_type == DDR3) { |
| 1543 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
| 1544 | /* ZQCAL enable */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1545 | MCHBAR32_OR(0x269 + 0x400 * ch, 1 << 26); |
Arthur Heymans | b4a7804 | 2017-12-25 20:17:41 +0100 | [diff] [blame] | 1546 | } |
| 1547 | } |
| 1548 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1549 | if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || |
| 1550 | ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1551 | MCHBAR8_OR(0x260, 1); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1552 | if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) || |
| 1553 | ONLY_DIMMB_IS_POPULATED(s->dimms, 1)) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1554 | MCHBAR8_OR(0x660, 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1555 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1556 | /* DRB */ |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1557 | lastrank_ch1 = 0; |
Arthur Heymans | dfce932 | 2017-12-16 19:48:00 +0100 | [diff] [blame] | 1558 | FOR_EACH_RANK(ch, r) { |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1559 | if (ch == 0) { |
Arthur Heymans | dfce932 | 2017-12-16 19:48:00 +0100 | [diff] [blame] | 1560 | if (RANK_IS_POPULATED(s->dimms, ch, r)) { |
| 1561 | dra0 = (c0dra >> (8*r)) & 0x7f; |
| 1562 | c0drb = (u16)(c0drb + drbtab[dra0]); |
| 1563 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1564 | MCHBAR16(0x200 + 2*r) = c0drb; |
| 1565 | } else { |
Arthur Heymans | dfce932 | 2017-12-16 19:48:00 +0100 | [diff] [blame] | 1566 | if (RANK_IS_POPULATED(s->dimms, ch, r)) { |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1567 | lastrank_ch1 = r; |
Arthur Heymans | dfce932 | 2017-12-16 19:48:00 +0100 | [diff] [blame] | 1568 | dra1 = (c1dra >> (8*r)) & 0x7f; |
| 1569 | c1drb = (u16)(c1drb + drbtab[dra1]); |
| 1570 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1571 | MCHBAR16(0x600 + 2*r) = c1drb; |
| 1572 | } |
| 1573 | } |
| 1574 | |
| 1575 | s->channel_capacity[0] = c0drb << 6; |
| 1576 | s->channel_capacity[1] = c1drb << 6; |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1577 | |
| 1578 | /* |
| 1579 | * In stacked mode the last present rank on ch1 needs to have its |
| 1580 | * size doubled in c1drbx. All subsequent ranks need the same setting |
| 1581 | * according to: "Intel 4 Series Chipset Family Datasheet" |
| 1582 | */ |
| 1583 | if (s->stacked_mode) { |
| 1584 | for (r = lastrank_ch1; r < 4; r++) |
| 1585 | MCHBAR16(0x600 + 2*r) = 2 * c1drb; |
| 1586 | } |
| 1587 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1588 | totalmemorymb = s->channel_capacity[0] + s->channel_capacity[1]; |
| 1589 | printk(BIOS_DEBUG, "Total memory: %d + %d = %dMiB\n", |
| 1590 | s->channel_capacity[0], s->channel_capacity[1], totalmemorymb); |
| 1591 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1592 | /* Populated channel sizes in MiB */ |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1593 | size_ch0 = s->channel_capacity[0]; |
| 1594 | size_ch1 = s->channel_capacity[1]; |
| 1595 | size_me = ME_UMA_SIZEMB; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1596 | |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1597 | if (s->stacked_mode) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1598 | MCHBAR8_OR(0x111, STACKED_MEM); |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1599 | } else { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1600 | MCHBAR8_AND(0x111, ~STACKED_MEM); |
| 1601 | MCHBAR8_OR(0x111, 1 << 4); |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1602 | } |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1603 | |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1604 | if (s->stacked_mode) { |
| 1605 | dual_channel_size = 0; |
| 1606 | } else if (size_me == 0) { |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1607 | dual_channel_size = MIN(size_ch0, size_ch1) * 2; |
| 1608 | } else { |
| 1609 | if (size_ch0 == 0) { |
Elyes HAOUAS | ef90609 | 2020-02-20 19:41:17 +0100 | [diff] [blame] | 1610 | /* ME needs RAM on CH0 */ |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1611 | size_me = 0; |
| 1612 | /* TOTEST: bailout? */ |
| 1613 | } else { |
| 1614 | /* Set ME UMA size in MiB */ |
| 1615 | MCHBAR16(0x100) = size_me; |
| 1616 | /* Set ME UMA Present bit */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1617 | MCHBAR32_OR(0x111, 1); |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1618 | } |
| 1619 | dual_channel_size = MIN(size_ch0 - size_me, size_ch1) * 2; |
| 1620 | } |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1621 | |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1622 | MCHBAR16(0x104) = dual_channel_size; |
| 1623 | single_channel_size = size_ch0 + size_ch1 - dual_channel_size; |
| 1624 | MCHBAR16(0x102) = single_channel_size; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1625 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1626 | map = 0; |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1627 | if (size_ch0 == 0) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1628 | map = 0; |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1629 | else if (size_ch1 == 0) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1630 | map |= 0x20; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1631 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1632 | map |= 0x40; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1633 | |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1634 | if (dual_channel_size == 0) |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1635 | map |= 0x18; |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1636 | /* Enable flex mode, we hardcode this everywhere */ |
| 1637 | if (size_me == 0) { |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1638 | if (!(s->stacked_mode && size_ch0 != 0 && size_ch1 != 0)) { |
| 1639 | map |= 0x04; |
| 1640 | if (size_ch0 <= size_ch1) |
| 1641 | map |= 0x01; |
| 1642 | } |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1643 | } else { |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1644 | if (s->stacked_mode == 0 && size_ch0 - size_me < size_ch1) |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1645 | map |= 0x04; |
| 1646 | } |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1647 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1648 | MCHBAR8(0x110) = map; |
| 1649 | MCHBAR16(0x10e) = 0; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1650 | |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1651 | /* |
| 1652 | * "108h[15:0] Single Channel Offset for Ch0" |
| 1653 | * This is the 'limit' of the part on CH0 that cannot be matched |
| 1654 | * with memory on CH1. MCHBAR16(0x10a) is where the dual channel |
| 1655 | * memory on ch0s end and MCHBAR16(0x108) is the limit of the single |
| 1656 | * channel size on ch0. |
| 1657 | */ |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1658 | if (s->stacked_mode && size_ch1 != 0) { |
| 1659 | single_channel_offset = 0; |
| 1660 | } else if (size_me == 0) { |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1661 | if (size_ch0 > size_ch1) |
| 1662 | single_channel_offset = dual_channel_size / 2 |
| 1663 | + single_channel_size; |
| 1664 | else |
| 1665 | single_channel_offset = dual_channel_size / 2; |
| 1666 | } else { |
| 1667 | if ((size_ch0 > size_ch1) && ((map & 0x7) == 4)) |
| 1668 | single_channel_offset = dual_channel_size / 2 |
| 1669 | + single_channel_size; |
| 1670 | else |
| 1671 | single_channel_offset = dual_channel_size / 2 |
| 1672 | + size_me; |
| 1673 | } |
| 1674 | |
| 1675 | MCHBAR16(0x108) = single_channel_offset; |
| 1676 | MCHBAR16(0x10a) = dual_channel_size / 2; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1677 | } |
| 1678 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1679 | static void configure_mmap(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1680 | { |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1681 | bool reclaim; |
| 1682 | u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud; |
| 1683 | u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit; |
Arthur Heymans | 16a70a4 | 2017-09-22 12:22:24 +0200 | [diff] [blame] | 1684 | u32 mmiostart, umasizem; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1685 | u16 ggc; |
Arthur Heymans | 27f94ee | 2016-06-18 21:08:58 +0200 | [diff] [blame] | 1686 | u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, |
| 1687 | 160, 224, 352 }; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1688 | u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; |
| 1689 | |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1690 | ggc = pci_read_config16(HOST_BRIDGE, 0x52); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1691 | gfxsize = ggc2uma[(ggc & 0xf0) >> 4]; |
| 1692 | gttsize = ggc2gtt[(ggc & 0xf00) >> 8]; |
Arthur Heymans | d522db0 | 2018-08-06 15:50:54 +0200 | [diff] [blame] | 1693 | /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, |
| 1694 | which requires to have TSEG_BASE aligned to TSEG_SIZE. */ |
| 1695 | tsegsize = 2; |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1696 | mmiosize = 0x800; /* 2GB MMIO */ |
Arthur Heymans | 16a70a4 | 2017-09-22 12:22:24 +0200 | [diff] [blame] | 1697 | umasizem = gfxsize + gttsize + tsegsize; |
| 1698 | mmiostart = 0x1000 - mmiosize + umasizem; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1699 | tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB; |
Arthur Heymans | 16a70a4 | 2017-09-22 12:22:24 +0200 | [diff] [blame] | 1700 | tolud = MIN(mmiostart, tom); |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1701 | |
| 1702 | reclaim = false; |
| 1703 | if ((tom - tolud) > 0x40) |
| 1704 | reclaim = true; |
| 1705 | |
| 1706 | if (reclaim) { |
| 1707 | tolud = tolud & ~0x3f; |
| 1708 | tom = tom & ~0x3f; |
| 1709 | reclaimbase = MAX(0x1000, tom); |
| 1710 | reclaimlimit = reclaimbase + (MIN(0x1000, tom) - tolud) - 0x40; |
| 1711 | } |
| 1712 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1713 | touud = tom; |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1714 | if (reclaim) |
| 1715 | touud = reclaimlimit + 0x40; |
| 1716 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1717 | gfxbase = tolud - gfxsize; |
| 1718 | gttbase = gfxbase - gttsize; |
| 1719 | tsegbase = gttbase - tsegsize; |
| 1720 | |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1721 | pci_write_config16(HOST_BRIDGE, 0xb0, tolud << 4); |
| 1722 | pci_write_config16(HOST_BRIDGE, 0xa0, tom >> 6); |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1723 | if (reclaim) { |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1724 | pci_write_config16(HOST_BRIDGE, 0x98, |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1725 | (u16)(reclaimbase >> 6)); |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1726 | pci_write_config16(HOST_BRIDGE, 0x9a, |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1727 | (u16)(reclaimlimit >> 6)); |
| 1728 | } |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1729 | pci_write_config16(HOST_BRIDGE, 0xa2, touud); |
| 1730 | pci_write_config32(HOST_BRIDGE, 0xa4, gfxbase << 20); |
| 1731 | pci_write_config32(HOST_BRIDGE, 0xa8, gttbase << 20); |
Angel Pons | 4a9569a | 2020-06-08 01:39:25 +0200 | [diff] [blame] | 1732 | /* Enable and set TSEG size to 2M */ |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1733 | pci_update_config8(HOST_BRIDGE, D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); |
| 1734 | pci_write_config32(HOST_BRIDGE, 0xac, tsegbase << 20); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1735 | } |
| 1736 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1737 | static void set_enhanced_mode(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1738 | { |
| 1739 | u8 ch, reg8; |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1740 | u32 reg32; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1741 | |
| 1742 | MCHBAR32(0xfb0) = 0x1000d024; |
| 1743 | MCHBAR32(0xfb4) = 0xc842; |
| 1744 | MCHBAR32(0xfbc) = 0xf; |
| 1745 | MCHBAR32(0xfc4) = 0xfe22244; |
| 1746 | MCHBAR8(0x12f) = 0x5c; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1747 | MCHBAR8_OR(0xfb0, 1); |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 1748 | if (s->selected_timings.mem_clk <= MEM_CLOCK_800MHz) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1749 | MCHBAR8_OR(0x12f, 0x2); |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 1750 | else |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1751 | MCHBAR8_AND(0x12f, ~0x2); |
| 1752 | MCHBAR8_AND_OR(0x6c0, ~0xf0, 0xa0); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1753 | MCHBAR32(0xfa8) = 0x30d400; |
| 1754 | |
| 1755 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1756 | MCHBAR8_OR(0x400*ch + 0x26c, 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1757 | MCHBAR32(0x400*ch + 0x278) = 0x88141881; |
| 1758 | MCHBAR16(0x400*ch + 0x27c) = 0x0041; |
| 1759 | MCHBAR8(0x400*ch + 0x292) = 0xf2; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1760 | MCHBAR16_OR(0x400*ch + 0x272, 0x100); |
| 1761 | MCHBAR8_AND_OR(0x400*ch + 0x243, ~0x2, 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1762 | MCHBAR32(0x400*ch + 0x288) = 0x8040200; |
| 1763 | MCHBAR32(0x400*ch + 0x28c) = 0xff402010; |
| 1764 | MCHBAR32(0x400*ch + 0x290) = 0x4f2091c; |
| 1765 | } |
| 1766 | |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1767 | reg8 = pci_read_config8(HOST_BRIDGE, 0xf0); |
| 1768 | pci_write_config8(HOST_BRIDGE, 0xf0, reg8 | 1); |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 1769 | MCHBAR32_AND_OR(0xfa0, ~0x20002, 0x2 | (s->selected_timings.fsb_clk == |
| 1770 | FSB_CLOCK_1333MHz ? 0x20000 : 0)); |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1771 | reg32 = 0x219100c2; |
| 1772 | if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) { |
| 1773 | reg32 |= 1; |
| 1774 | if (s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) |
| 1775 | reg32 &= ~0x10000; |
| 1776 | } else if (s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz) { |
| 1777 | reg32 &= ~0x10000; |
| 1778 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1779 | MCHBAR32_AND_OR(0xfa4, ~0x219100c3, reg32); |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1780 | reg32 = 0x44a00; |
| 1781 | switch (s->selected_timings.fsb_clk) { |
| 1782 | case FSB_CLOCK_1333MHz: |
| 1783 | reg32 |= 0x62; |
| 1784 | break; |
| 1785 | case FSB_CLOCK_1066MHz: |
| 1786 | reg32 |= 0x5a; |
| 1787 | break; |
| 1788 | default: |
| 1789 | case FSB_CLOCK_800MHz: |
| 1790 | reg32 |= 0x53; |
| 1791 | break; |
| 1792 | } |
| 1793 | |
| 1794 | MCHBAR32(0x2c) = reg32; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1795 | MCHBAR32(0x30) = 0x1f5a86; |
| 1796 | MCHBAR32(0x34) = 0x1902810; |
| 1797 | MCHBAR32(0x38) = 0xf7000000; |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1798 | reg32 = 0x23014410; |
| 1799 | if (s->selected_timings.fsb_clk > FSB_CLOCK_800MHz) |
| 1800 | reg32 = (reg32 & ~0x2000000) | 0x44000000; |
| 1801 | MCHBAR32(0x3c) = reg32; |
| 1802 | reg32 = 0x8f038000; |
| 1803 | if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) |
| 1804 | reg32 &= ~0x4000000; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1805 | MCHBAR32_AND_OR(0x40, ~0x8f038000, reg32); |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1806 | reg32 = 0x00013001; |
| 1807 | if (s->selected_timings.fsb_clk < FSB_CLOCK_1333MHz) |
| 1808 | reg32 |= 0x20000; |
| 1809 | MCHBAR32(0x20) = reg32; |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1810 | pci_write_config8(HOST_BRIDGE, 0xf0, reg8 & ~1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1811 | } |
| 1812 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1813 | static void power_settings(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1814 | { |
| 1815 | u32 reg1, reg2, reg3, reg4, clkgate, x592; |
| 1816 | u8 lane, ch; |
| 1817 | u8 twl = 0; |
| 1818 | u16 x264, x23c; |
| 1819 | |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 1820 | if (s->spd_type == DDR2) { |
| 1821 | twl = s->selected_timings.CAS - 1; |
| 1822 | x264 = 0x78; |
| 1823 | |
| 1824 | switch (s->selected_timings.mem_clk) { |
| 1825 | default: |
| 1826 | case MEM_CLOCK_667MHz: |
| 1827 | reg1 = 0x99; |
| 1828 | reg2 = 0x1048a9; |
| 1829 | clkgate = 0x230000; |
| 1830 | x23c = 0x7a89; |
| 1831 | break; |
| 1832 | case MEM_CLOCK_800MHz: |
| 1833 | if (s->selected_timings.CAS == 5) { |
| 1834 | reg1 = 0x19a; |
| 1835 | reg2 = 0x1048aa; |
| 1836 | } else { |
| 1837 | reg1 = 0x9a; |
| 1838 | reg2 = 0x2158aa; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1839 | x264 = 0x89; |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 1840 | } |
| 1841 | clkgate = 0x280000; |
| 1842 | x23c = 0x7b89; |
| 1843 | break; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1844 | } |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 1845 | reg3 = 0x232; |
| 1846 | reg4 = 0x2864; |
| 1847 | } else { /* DDR3 */ |
| 1848 | int ddr3_idx = s->selected_timings.mem_clk - MEM_CLOCK_800MHz; |
| 1849 | int cas_idx = s->selected_timings.CAS - 5; |
| 1850 | |
| 1851 | twl = s->selected_timings.mem_clk - MEM_CLOCK_800MHz + 5; |
| 1852 | reg1 = ddr3_c2_tab[s->nmode - 1][ddr3_idx][cas_idx][0]; |
| 1853 | reg2 = ddr3_c2_tab[s->nmode - 1][ddr3_idx][cas_idx][1]; |
| 1854 | reg3 = 0x764; |
| 1855 | reg4 = 0x78c8; |
| 1856 | x264 = ddr3_c2_x264[ddr3_idx][cas_idx]; |
| 1857 | x23c = ddr3_c2_x23c[ddr3_idx][cas_idx]; |
| 1858 | switch (s->selected_timings.mem_clk) { |
| 1859 | case MEM_CLOCK_800MHz: |
| 1860 | default: |
| 1861 | clkgate = 0x280000; |
| 1862 | break; |
| 1863 | case MEM_CLOCK_1066MHz: |
| 1864 | clkgate = 0x350000; |
| 1865 | break; |
| 1866 | case MEM_CLOCK_1333MHz: |
| 1867 | clkgate = 0xff0000; |
| 1868 | break; |
| 1869 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1870 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1871 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1872 | if (CHANNEL_IS_POPULATED(s->dimms, 0) && CHANNEL_IS_POPULATED(s->dimms, 1)) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1873 | MCHBAR32(0x14) = 0x0010461f; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1874 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1875 | MCHBAR32(0x14) = 0x0010691f; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1876 | MCHBAR32(0x18) = 0xdf6437f7; |
| 1877 | MCHBAR32(0x1c) = 0x0; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1878 | MCHBAR32_AND_OR(0x24, ~0xe0000000, 0x60000000); |
| 1879 | MCHBAR32_AND_OR(0x44, ~0x1fef0000, 0x6b0000); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1880 | MCHBAR16(0x115) = (u16) reg1; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1881 | MCHBAR32_AND_OR(0x117, ~0xffffff, reg2); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1882 | MCHBAR8(0x124) = 0x7; |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1883 | /* not sure if dummy reads are needed */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1884 | MCHBAR16_AND_OR(0x12a, 0, 0x80); |
| 1885 | MCHBAR8_AND_OR(0x12c, 0, 0xa0); |
| 1886 | MCHBAR16_AND(0x174, ~(1 << 15)); |
| 1887 | MCHBAR16_AND_OR(0x188, ~0x1f00, 0x1f00); |
| 1888 | MCHBAR8_AND(0x18c, ~0x8); |
| 1889 | MCHBAR8_OR(0x192, 1); |
| 1890 | MCHBAR8_OR(0x193, 0xf); |
| 1891 | MCHBAR16_AND_OR(0x1b4, ~0x480, 0x80); |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1892 | MCHBAR16_AND_OR(0x210, ~0x1fff, 0x3f); /* clockgating iii */ |
| 1893 | /* non-aligned access: possible bug? */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1894 | MCHBAR32_AND_OR(0x6d1, ~0xff03ff, 0x100 | clkgate); |
| 1895 | MCHBAR8_AND_OR(0x212, ~0x7f, 0x7f); |
| 1896 | MCHBAR32_AND_OR(0x2c0, ~0xffff0, 0xcc5f0); |
| 1897 | MCHBAR8_AND_OR(0x2c4, ~0x70, 0x70); |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1898 | /* non-aligned access: possible bug? */ |
| 1899 | MCHBAR32_AND_OR(0x2d1, ~0xffffff, 0xff2831); /* clockgating i */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1900 | MCHBAR32(0x2d4) = 0x40453600; |
| 1901 | MCHBAR32(0x300) = 0xc0b0a08; |
| 1902 | MCHBAR32(0x304) = 0x6040201; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1903 | MCHBAR32_AND_OR(0x30c, ~0x43c0f, 0x41405); |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1904 | MCHBAR16(0x610) = reg3; |
| 1905 | MCHBAR16(0x612) = reg4; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1906 | MCHBAR32_AND_OR(0x62c, ~0xc000000, 0x4000000); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1907 | MCHBAR32(0xae4) = 0; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1908 | MCHBAR32_AND_OR(0xc00, ~0xf0000, 0x10000); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1909 | MCHBAR32(0xf00) = 0x393a3b3c; |
| 1910 | MCHBAR32(0xf04) = 0x3d3e3f40; |
| 1911 | MCHBAR32(0xf08) = 0x393a3b3c; |
| 1912 | MCHBAR32(0xf0c) = 0x3d3e3f40; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1913 | MCHBAR32_AND(0xf18, ~0xfff00001); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1914 | MCHBAR32(0xf48) = 0xfff0ffe0; |
| 1915 | MCHBAR32(0xf4c) = 0xffc0ff00; |
| 1916 | MCHBAR32(0xf50) = 0xfc00f000; |
| 1917 | MCHBAR32(0xf54) = 0xc0008000; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1918 | MCHBAR32_AND_OR(0xf6c, ~0xffff0000, 0xffff0000); |
| 1919 | MCHBAR32_AND(0xfac, ~0x80000000); |
| 1920 | MCHBAR32_AND(0xfb8, ~0xff000000); |
| 1921 | MCHBAR32_AND_OR(0xfbc, ~0x7f800, 0xf000); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1922 | MCHBAR32(0x1104) = 0x3003232; |
| 1923 | MCHBAR32(0x1108) = 0x74; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1924 | if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1925 | MCHBAR32(0x110c) = 0xaa; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1926 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1927 | MCHBAR32(0x110c) = 0x100; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1928 | MCHBAR32(0x1110) = 0x10810350 & ~0x78; |
| 1929 | MCHBAR32(0x1114) = 0; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1930 | x592 = 0xff; |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 1931 | if (pci_read_config8(HOST_BRIDGE, 0x8) < 3) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1932 | x592 = ~0x4; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1933 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1934 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
| 1935 | MCHBAR8(0x400*ch + 0x239) = twl + 15; |
| 1936 | MCHBAR16(0x400*ch + 0x23c) = x23c; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1937 | MCHBAR32_AND_OR(0x400*ch + 0x248, ~0x706033, 0x406033); |
| 1938 | MCHBAR32_AND_OR(0x400*ch + 0x260, ~(1 << 16), 1 << 16); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1939 | MCHBAR8(0x400*ch + 0x264) = x264; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1940 | MCHBAR8_AND_OR(0x400*ch + 0x592, ~0x3f, 0x3c & x592); |
| 1941 | MCHBAR8_AND_OR(0x400*ch + 0x593, ~0x1f, 0x1e); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1942 | } |
| 1943 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1944 | for (lane = 0; lane < 8; lane++) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1945 | MCHBAR8_AND(0x561 + (lane << 2), ~(1 << 3)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1946 | } |
| 1947 | |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 1948 | static void software_ddr3_reset(struct sysinfo *s) |
| 1949 | { |
| 1950 | printk(BIOS_DEBUG, "Software initiated DDR3 reset.\n"); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1951 | MCHBAR8_OR(0x1a8, 0x02); |
| 1952 | MCHBAR8_AND(0x5da, ~0x80); |
| 1953 | MCHBAR8_AND(0x1a8, ~0x02); |
| 1954 | MCHBAR8_AND_OR(0x5da, ~0x03, 1); |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 1955 | udelay(200); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1956 | MCHBAR8_AND(0x1a8, ~0x02); |
| 1957 | MCHBAR8_OR(0x5da, 0x80); |
| 1958 | MCHBAR8_AND(0x5da, ~0x80); |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 1959 | udelay(500); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1960 | MCHBAR8_OR(0x5da, 0x03); |
| 1961 | MCHBAR8_AND(0x5da, ~0x03); |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 1962 | /* After write leveling the dram needs to be reset and reinitialised */ |
| 1963 | jedec_ddr3(s); |
| 1964 | } |
| 1965 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1966 | void do_raminit(struct sysinfo *s, int fast_boot) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1967 | { |
| 1968 | u8 ch; |
| 1969 | u8 r, bank; |
| 1970 | u32 reg32; |
| 1971 | |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1972 | if (s->boot_path != BOOT_PATH_WARM_RESET) { |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1973 | /* Clear self refresh */ |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1974 | MCHBAR32(PMSTS_MCHBAR) = MCHBAR32(PMSTS_MCHBAR) |
| 1975 | | PMSTS_BOTH_SELFREFRESH; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1976 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1977 | /* Clear host clk gate reg */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1978 | MCHBAR32_OR(0x1c, 0xffffffff); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1979 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1980 | /* Select type */ |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 1981 | if (s->spd_type == DDR2) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1982 | MCHBAR8_AND(0x1a8, ~0x4); |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 1983 | else |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1984 | MCHBAR8_OR(0x1a8, 0x4); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1985 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1986 | /* Set frequency */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1987 | MCHBAR32_AND_OR(0xc00, ~0x70, |
| 1988 | (s->selected_timings.mem_clk << 4) | (1 << 10)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1989 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1990 | /* Overwrite value if chipset rejects it */ |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1991 | s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4; |
| 1992 | if (s->selected_timings.mem_clk > (s->max_fsb + 3)) |
| 1993 | die("Error: DDR is faster than FSB, halt\n"); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1994 | } |
| 1995 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 1996 | /* Program clock crossing */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1997 | program_crossclock(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1998 | printk(BIOS_DEBUG, "Done clk crossing\n"); |
| 1999 | |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2000 | if (s->boot_path != BOOT_PATH_WARM_RESET) { |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2001 | setioclk_dram(s); |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2002 | printk(BIOS_DEBUG, "Done I/O clk\n"); |
| 2003 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2004 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2005 | /* Grant to launch */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2006 | launch_dram(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2007 | printk(BIOS_DEBUG, "Done launch\n"); |
| 2008 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2009 | /* Program DRAM timings */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2010 | program_timings(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2011 | printk(BIOS_DEBUG, "Done timings\n"); |
| 2012 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2013 | /* Program DLL */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2014 | program_dll(s); |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 2015 | if (!fast_boot) |
| 2016 | select_default_dq_dqs_settings(s); |
| 2017 | set_all_dq_dqs_dll_settings(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2018 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2019 | /* RCOMP */ |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2020 | if (s->boot_path != BOOT_PATH_WARM_RESET) { |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2021 | prog_rcomp(s); |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2022 | printk(BIOS_DEBUG, "RCOMP\n"); |
| 2023 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2024 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2025 | /* ODT */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2026 | program_odt(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2027 | printk(BIOS_DEBUG, "Done ODT\n"); |
| 2028 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2029 | /* RCOMP update */ |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2030 | if (s->boot_path != BOOT_PATH_WARM_RESET) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2031 | while (MCHBAR8(0x130) & 1) |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2032 | ; |
| 2033 | printk(BIOS_DEBUG, "Done RCOMP update\n"); |
| 2034 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2035 | |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 2036 | pre_jedec_memory_map(); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2037 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2038 | /* IOBUFACT */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2039 | if (CHANNEL_IS_POPULATED(s->dimms, 0)) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2040 | MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f); |
| 2041 | MCHBAR8_OR(0x5d8, 0x7); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2042 | } |
| 2043 | if (CHANNEL_IS_POPULATED(s->dimms, 1)) { |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 2044 | if (pci_read_config8(HOST_BRIDGE, 0x8) < 2) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2045 | MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f); |
| 2046 | MCHBAR8_OR(0x5d8, 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2047 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2048 | MCHBAR8_OR(0x9dd, 0x3f); |
| 2049 | MCHBAR8_OR(0x9d8, 0x7); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2050 | } |
| 2051 | |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 2052 | /* DDR3 reset */ |
| 2053 | if ((s->spd_type == DDR3) && (s->boot_path != BOOT_PATH_RESUME)) { |
| 2054 | printk(BIOS_DEBUG, "DDR3 Reset.\n"); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2055 | MCHBAR8_AND(0x1a8, ~0x2); |
| 2056 | MCHBAR8_OR(0x5da, 0x80); |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 2057 | udelay(500); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2058 | MCHBAR8_AND(0x1a8, ~0x2); |
| 2059 | MCHBAR8_AND(0x5da, ~0x80); |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 2060 | udelay(500); |
| 2061 | } |
| 2062 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2063 | /* Pre jedec */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2064 | MCHBAR8_OR(0x40, 0x2); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2065 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2066 | MCHBAR32_OR(0x400*ch + 0x260, 1 << 27); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2067 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2068 | MCHBAR16_OR(0x212, 0xf000); |
| 2069 | MCHBAR16_OR(0x212, 0xf00); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2070 | printk(BIOS_DEBUG, "Done pre-jedec\n"); |
| 2071 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2072 | /* JEDEC reset */ |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 2073 | if (s->boot_path != BOOT_PATH_RESUME) { |
| 2074 | if (s->spd_type == DDR2) |
| 2075 | jedec_ddr2(s); |
| 2076 | else /* DDR3 */ |
| 2077 | jedec_ddr3(s); |
| 2078 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2079 | |
| 2080 | printk(BIOS_DEBUG, "Done jedec steps\n"); |
| 2081 | |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 2082 | if (s->spd_type == DDR3) { |
| 2083 | if (!fast_boot) |
| 2084 | search_write_leveling(s); |
| 2085 | if (s->boot_path == BOOT_PATH_NORMAL) |
| 2086 | software_ddr3_reset(s); |
| 2087 | } |
| 2088 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2089 | /* After JEDEC reset */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2090 | MCHBAR8_AND(0x40, ~0x2); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2091 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Arthur Heymans | 0d28495 | 2017-05-25 19:55:52 +0200 | [diff] [blame] | 2092 | reg32 = (2 << 18); |
| 2093 | reg32 |= post_jedec_tab[s->selected_timings.fsb_clk] |
| 2094 | [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][0] |
| 2095 | << 13; |
| 2096 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz && |
| 2097 | s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz && |
| 2098 | ch == 1) { |
| 2099 | reg32 |= (post_jedec_tab[s->selected_timings.fsb_clk] |
| 2100 | [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] |
| 2101 | - 1) << 8; |
| 2102 | } else { |
| 2103 | reg32 |= post_jedec_tab[s->selected_timings.fsb_clk] |
| 2104 | [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] |
| 2105 | << 8; |
| 2106 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2107 | MCHBAR32_AND_OR(0x400*ch + 0x274, ~0xfff00, reg32); |
| 2108 | MCHBAR8_AND(0x400*ch + 0x274, ~0x80); |
| 2109 | MCHBAR8_OR(0x400*ch + 0x26c, 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2110 | MCHBAR32(0x400*ch + 0x278) = 0x88141881; |
| 2111 | MCHBAR16(0x400*ch + 0x27c) = 0x41; |
| 2112 | MCHBAR8(0x400*ch + 0x292) = 0xf2; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2113 | MCHBAR8_OR(0x400*ch + 0x271, 0xe); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2114 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2115 | MCHBAR8_OR(0x2c4, 0x8); |
| 2116 | MCHBAR8_OR(0x2c3, 0x40); |
| 2117 | MCHBAR8_OR(0x2c4, 0x4); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2118 | |
| 2119 | printk(BIOS_DEBUG, "Done post-jedec\n"); |
| 2120 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2121 | /* Set DDR init complete */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2122 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2123 | MCHBAR32_OR(0x400*ch + 0x268, 0xc0000000); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2124 | } |
| 2125 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2126 | /* Dummy reads */ |
Arthur Heymans | 8bb2bac | 2019-08-10 20:34:17 +0200 | [diff] [blame] | 2127 | if (s->boot_path == BOOT_PATH_NORMAL) { |
| 2128 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
| 2129 | for (bank = 0; bank < 4; bank++) |
| 2130 | read32((u32 *)(test_address(ch, r) | 0x800000 | (bank << 12))); |
| 2131 | } |
| 2132 | } |
| 2133 | printk(BIOS_DEBUG, "Done dummy reads\n"); |
| 2134 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2135 | /* Receive enable */ |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 2136 | sdram_program_receive_enable(s, fast_boot); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2137 | printk(BIOS_DEBUG, "Done rcven\n"); |
| 2138 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2139 | /* Finish rcven */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2140 | FOR_EACH_CHANNEL(ch) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2141 | MCHBAR8_AND(0x400*ch + 0x5d8, ~0xe); |
| 2142 | MCHBAR8_OR(0x400*ch + 0x5d8, 0x2); |
| 2143 | MCHBAR8_OR(0x400*ch + 0x5d8, 0x4); |
| 2144 | MCHBAR8_OR(0x400*ch + 0x5d8, 0x8); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2145 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2146 | MCHBAR8_OR(0x5dc, 0x80); |
| 2147 | MCHBAR8_AND(0x5dc, ~0x80); |
| 2148 | MCHBAR8_OR(0x5dc, 0x80); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2149 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2150 | /* XXX tRD */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2151 | |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 2152 | if (!fast_boot) { |
| 2153 | if (s->selected_timings.mem_clk > MEM_CLOCK_667MHz) { |
Elyes HAOUAS | 5ba154a | 2020-08-04 13:27:52 +0200 | [diff] [blame] | 2154 | if (do_write_training(s)) |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 2155 | die("DQ write training failed!"); |
| 2156 | } |
| 2157 | if (do_read_training(s)) |
| 2158 | die("DQS read training failed!"); |
| 2159 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2160 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2161 | /* DRADRB */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2162 | set_dradrb(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2163 | printk(BIOS_DEBUG, "Done DRADRB\n"); |
| 2164 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2165 | /* Memory map */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2166 | configure_mmap(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2167 | printk(BIOS_DEBUG, "Done memory map\n"); |
| 2168 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2169 | /* Enhanced mode */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2170 | set_enhanced_mode(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2171 | printk(BIOS_DEBUG, "Done enhanced mode\n"); |
| 2172 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2173 | /* Periodic RCOMP */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2174 | MCHBAR16_AND_OR(0x160, ~0xfff, 0x999); |
| 2175 | MCHBAR16_OR(0x1b4, 0x3000); |
| 2176 | MCHBAR8_OR(0x130, 0x82); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2177 | printk(BIOS_DEBUG, "Done PRCOMP\n"); |
| 2178 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2179 | /* Power settings */ |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2180 | power_settings(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2181 | printk(BIOS_DEBUG, "Done power settings\n"); |
| 2182 | |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 2183 | /* ME related */ |
Arthur Heymans | ddc8828 | 2017-02-27 16:27:21 +0100 | [diff] [blame] | 2184 | /* |
| 2185 | * FIXME: This locks some registers like bit1 of GGC |
| 2186 | * and is only needed in case of ME being used. |
| 2187 | */ |
| 2188 | if (ME_UMA_SIZEMB != 0) { |
| 2189 | if (RANK_IS_POPULATED(s->dimms, 0, 0) |
| 2190 | || RANK_IS_POPULATED(s->dimms, 1, 0)) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2191 | MCHBAR8_OR(0xa2f, 1 << 0); |
Arthur Heymans | ddc8828 | 2017-02-27 16:27:21 +0100 | [diff] [blame] | 2192 | if (RANK_IS_POPULATED(s->dimms, 0, 1) |
| 2193 | || RANK_IS_POPULATED(s->dimms, 1, 1)) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2194 | MCHBAR8_OR(0xa2f, 1 << 1); |
| 2195 | MCHBAR32_OR(0xa30, 1 << 26); |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 2196 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2197 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2198 | printk(BIOS_DEBUG, "Done raminit\n"); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2199 | } |