Patrick Georgi | c49d7a3 | 2020-05-08 22:50:46 +0200 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 2 | |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 3 | mainmenu "coreboot configuration" |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 4 | |
Uwe Hermann | c04be93 | 2009-10-05 13:55:28 +0000 | [diff] [blame] | 5 | menu "General setup" |
| 6 | |
Lee Leahy | bb70c40 | 2017-04-03 07:38:20 -0700 | [diff] [blame] | 7 | config COREBOOT_BUILD |
| 8 | bool |
| 9 | default y |
| 10 | |
Uwe Hermann | c04be93 | 2009-10-05 13:55:28 +0000 | [diff] [blame] | 11 | config LOCALVERSION |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 12 | string "Local version string" |
Uwe Hermann | c04be93 | 2009-10-05 13:55:28 +0000 | [diff] [blame] | 13 | help |
| 14 | Append an extra string to the end of the coreboot version. |
| 15 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 16 | This can be useful if, for instance, you want to append the |
| 17 | respective board's hostname or some other identifying string to |
| 18 | the coreboot version number, so that you can easily distinguish |
| 19 | boot logs of different boards from each other. |
| 20 | |
Arthur Heymans | 6f75154 | 2019-06-08 11:28:52 +0200 | [diff] [blame] | 21 | config CONFIGURABLE_CBFS_PREFIX |
| 22 | bool |
| 23 | help |
| 24 | Select this to prompt to use to configure the prefix for cbfs files. |
| 25 | |
Arthur Heymans | 6010eb2 | 2019-10-06 13:34:20 +0200 | [diff] [blame] | 26 | choice |
| 27 | prompt "CBFS prefix to use" |
| 28 | depends on CONFIGURABLE_CBFS_PREFIX |
| 29 | default CBFS_PREFIX_FALLBACK |
| 30 | |
| 31 | config CBFS_PREFIX_FALLBACK |
| 32 | bool "fallback" |
| 33 | |
| 34 | config CBFS_PREFIX_NORMAL |
| 35 | bool "normal" |
| 36 | |
| 37 | config CBFS_PREFIX_DIY |
| 38 | bool "Define your own cbfs prefix" |
| 39 | |
| 40 | endchoice |
| 41 | |
Patrick Georgi | 4b8a241 | 2010-02-09 19:35:16 +0000 | [diff] [blame] | 42 | config CBFS_PREFIX |
Arthur Heymans | 6010eb2 | 2019-10-06 13:34:20 +0200 | [diff] [blame] | 43 | string "CBFS prefix to use" if CBFS_PREFIX_DIY |
| 44 | default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK |
| 45 | default "normal" if CBFS_PREFIX_NORMAL |
Patrick Georgi | 4b8a241 | 2010-02-09 19:35:16 +0000 | [diff] [blame] | 46 | help |
| 47 | Select the prefix to all files put into the image. It's "fallback" |
| 48 | by default, "normal" is a common alternative. |
| 49 | |
Patrick Georgi | 23d89cc | 2010-03-16 01:17:19 +0000 | [diff] [blame] | 50 | choice |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 51 | prompt "Compiler to use" |
Patrick Georgi | 23d89cc | 2010-03-16 01:17:19 +0000 | [diff] [blame] | 52 | default COMPILER_GCC |
| 53 | help |
| 54 | This option allows you to select the compiler used for building |
| 55 | coreboot. |
Martin Roth | a5a628e8 | 2016-01-19 12:01:09 -0700 | [diff] [blame] | 56 | You must build the coreboot crosscompiler for the board that you |
| 57 | have selected. |
| 58 | |
| 59 | To build all the GCC crosscompilers (takes a LONG time), run: |
| 60 | make crossgcc |
| 61 | |
| 62 | For help on individual architectures, run the command: |
| 63 | make help_toolchain |
Patrick Georgi | 23d89cc | 2010-03-16 01:17:19 +0000 | [diff] [blame] | 64 | |
| 65 | config COMPILER_GCC |
| 66 | bool "GCC" |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 67 | help |
| 68 | Use the GNU Compiler Collection (GCC) to build coreboot. |
| 69 | |
| 70 | For details see http://gcc.gnu.org. |
| 71 | |
Patrick Georgi | 23d89cc | 2010-03-16 01:17:19 +0000 | [diff] [blame] | 72 | config COMPILER_LLVM_CLANG |
Martin Roth | a5a628e8 | 2016-01-19 12:01:09 -0700 | [diff] [blame] | 73 | bool "LLVM/clang (TESTING ONLY - Not currently working)" |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 74 | help |
Martin Roth | a5a628e8 | 2016-01-19 12:01:09 -0700 | [diff] [blame] | 75 | Use LLVM/clang to build coreboot. To use this, you must build the |
| 76 | coreboot version of the clang compiler. Run the command |
| 77 | make clang |
| 78 | Note that this option is not currently working correctly and should |
| 79 | really only be selected if you're trying to work on getting clang |
| 80 | operational. |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 81 | |
| 82 | For details see http://clang.llvm.org. |
| 83 | |
Patrick Georgi | 23d89cc | 2010-03-16 01:17:19 +0000 | [diff] [blame] | 84 | endchoice |
| 85 | |
Patrick Georgi | 9b0de71 | 2013-12-29 18:45:23 +0100 | [diff] [blame] | 86 | config ANY_TOOLCHAIN |
| 87 | bool "Allow building with any toolchain" |
| 88 | default n |
Patrick Georgi | 9b0de71 | 2013-12-29 18:45:23 +0100 | [diff] [blame] | 89 | help |
| 90 | Many toolchains break when building coreboot since it uses quite |
| 91 | unusual linker features. Unless developers explicitely request it, |
| 92 | we'll have to assume that they use their distro compiler by mistake. |
| 93 | Make sure that using patched compilers is a conscious decision. |
| 94 | |
Patrick Georgi | 516a2a7 | 2010-03-25 21:45:25 +0000 | [diff] [blame] | 95 | config CCACHE |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 96 | bool "Use ccache to speed up (re)compilation" |
Patrick Georgi | 516a2a7 | 2010-03-25 21:45:25 +0000 | [diff] [blame] | 97 | default n |
| 98 | help |
| 99 | Enables the use of ccache for faster builds. |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 100 | |
| 101 | Requires the ccache utility in your system $PATH. |
| 102 | |
| 103 | For details see https://ccache.samba.org. |
Patrick Georgi | 516a2a7 | 2010-03-25 21:45:25 +0000 | [diff] [blame] | 104 | |
Sol Boucher | 69b88bf | 2015-02-26 11:47:19 -0800 | [diff] [blame] | 105 | config FMD_GENPARSER |
| 106 | bool "Generate flashmap descriptor parser using flex and bison" |
| 107 | default n |
Sol Boucher | 69b88bf | 2015-02-26 11:47:19 -0800 | [diff] [blame] | 108 | help |
| 109 | Enable this option if you are working on the flashmap descriptor |
| 110 | parser and made changes to fmd_scanner.l or fmd_parser.y. |
| 111 | |
| 112 | Otherwise, say N to use the provided pregenerated scanner/parser. |
| 113 | |
Martin Roth | f411b70 | 2017-04-09 19:12:42 -0600 | [diff] [blame] | 114 | config UTIL_GENPARSER |
Denis 'GNUtoo' Carikli | 780e931 | 2018-01-10 14:35:55 +0100 | [diff] [blame] | 115 | bool "Generate SCONFIG & BINCFG parser using flex and bison" |
Stefan Reinauer | 9bf7810 | 2010-08-09 13:28:18 +0000 | [diff] [blame] | 116 | default n |
Stefan Reinauer | 9bf7810 | 2010-08-09 13:28:18 +0000 | [diff] [blame] | 117 | help |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 118 | Enable this option if you are working on the sconfig device tree |
Denis 'GNUtoo' Carikli | 780e931 | 2018-01-10 14:35:55 +0100 | [diff] [blame] | 119 | parser or bincfg and made changes to the .l or .y files. |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 120 | |
Sol Boucher | 69b88bf | 2015-02-26 11:47:19 -0800 | [diff] [blame] | 121 | Otherwise, say N to use the provided pregenerated scanner/parser. |
Stefan Reinauer | 9bf7810 | 2010-08-09 13:28:18 +0000 | [diff] [blame] | 122 | |
Joe Korty | 6d77252 | 2010-05-19 18:41:15 +0000 | [diff] [blame] | 123 | config USE_OPTION_TABLE |
| 124 | bool "Use CMOS for configuration values" |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 125 | depends on HAVE_OPTION_TABLE |
Joe Korty | 6d77252 | 2010-05-19 18:41:15 +0000 | [diff] [blame] | 126 | help |
| 127 | Enable this option if coreboot shall read options from the "CMOS" |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 128 | NVRAM instead of using hard-coded values. |
Joe Korty | 6d77252 | 2010-05-19 18:41:15 +0000 | [diff] [blame] | 129 | |
Timothy Pearson | f20c6e8 | 2015-02-14 16:15:31 -0600 | [diff] [blame] | 130 | config STATIC_OPTION_TABLE |
| 131 | bool "Load default configuration values into CMOS on each boot" |
Timothy Pearson | f20c6e8 | 2015-02-14 16:15:31 -0600 | [diff] [blame] | 132 | depends on USE_OPTION_TABLE |
| 133 | help |
| 134 | Enable this option to reset "CMOS" NVRAM values to default on |
| 135 | every boot. Use this if you want the NVRAM configuration to |
| 136 | never be modified from its default values. |
| 137 | |
Sven Schnelle | 8eee19d | 2011-05-02 19:53:04 +0000 | [diff] [blame] | 138 | config COMPRESS_RAMSTAGE |
| 139 | bool "Compress ramstage with LZMA" |
Subrata Banik | b5962a9 | 2019-06-08 12:29:02 +0530 | [diff] [blame] | 140 | depends on HAVE_RAMSTAGE |
Martin Roth | 75e5cb7 | 2016-12-15 15:05:37 -0700 | [diff] [blame] | 141 | # Default value set at the end of the file |
Sven Schnelle | 8eee19d | 2011-05-02 19:53:04 +0000 | [diff] [blame] | 142 | help |
Arthur Heymans | 7f22933 | 2019-11-08 11:59:25 +0100 | [diff] [blame] | 143 | Compress ramstage to save memory in the flash image. |
Sven Schnelle | 8eee19d | 2011-05-02 19:53:04 +0000 | [diff] [blame] | 144 | |
Julius Werner | 09f2921 | 2015-09-29 13:51:35 -0700 | [diff] [blame] | 145 | config COMPRESS_PRERAM_STAGES |
| 146 | bool "Compress romstage and verstage with LZ4" |
Subrata Banik | b5962a9 | 2019-06-08 12:29:02 +0530 | [diff] [blame] | 147 | depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE) |
Martin Roth | 75e5cb7 | 2016-12-15 15:05:37 -0700 | [diff] [blame] | 148 | # Default value set at the end of the file |
Julius Werner | 09f2921 | 2015-09-29 13:51:35 -0700 | [diff] [blame] | 149 | help |
| 150 | Compress romstage and (if it exists) verstage with LZ4 to save flash |
| 151 | space and speed up boot, since the time for reading the image from SPI |
| 152 | (and in the vboot case verifying it) is usually much greater than the |
| 153 | time spent decompressing. Doesn't work for XIP stages (assume all |
| 154 | ARCH_X86 for now) for obvious reasons. |
| 155 | |
Julius Werner | 99f4683 | 2018-05-16 14:14:04 -0700 | [diff] [blame] | 156 | config COMPRESS_BOOTBLOCK |
| 157 | bool |
Subrata Banik | b5962a9 | 2019-06-08 12:29:02 +0530 | [diff] [blame] | 158 | depends on HAVE_BOOTBLOCK |
Julius Werner | 99f4683 | 2018-05-16 14:14:04 -0700 | [diff] [blame] | 159 | help |
| 160 | This option can be used to compress the bootblock with LZ4 and attach |
| 161 | a small self-decompression stub to its front. This can drastically |
| 162 | reduce boot time on platforms where the bootblock is loaded over a |
| 163 | very slow connection and bootblock size trumps all other factors for |
Jonathan Neuschäfer | 2930a72 | 2018-09-29 17:42:52 +0200 | [diff] [blame] | 164 | speed. Since using this option usually requires changes to the |
Julius Werner | 99f4683 | 2018-05-16 14:14:04 -0700 | [diff] [blame] | 165 | SoC memlayout and possibly extra support code, it should not be |
| 166 | user-selectable. (There's no real point in offering this to the user |
| 167 | anyway... if it works and saves boot time, you would always want it.) |
| 168 | |
Cristian Măgherușan-Stanciu | d367b00 | 2011-06-19 03:03:28 +0200 | [diff] [blame] | 169 | config INCLUDE_CONFIG_FILE |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 170 | bool "Include the coreboot .config file into the ROM image" |
Martin Roth | 75e5cb7 | 2016-12-15 15:05:37 -0700 | [diff] [blame] | 171 | # Default value set at the end of the file |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 172 | help |
| 173 | Include the .config file that was used to compile coreboot |
| 174 | in the (CBFS) ROM image. This is useful if you want to know which |
| 175 | options were used to build a specific coreboot.rom image. |
| 176 | |
Daniele Forsi | 53847a2 | 2014-07-22 18:00:56 +0200 | [diff] [blame] | 177 | Saying Y here will increase the image size by 2-3KB. |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 178 | |
| 179 | You can use the following command to easily list the options: |
| 180 | |
| 181 | grep -a CONFIG_ coreboot.rom |
| 182 | |
| 183 | Alternatively, you can also use cbfstool to print the image |
| 184 | contents (including the raw 'config' item we're looking for). |
| 185 | |
| 186 | Example: |
| 187 | |
| 188 | $ cbfstool coreboot.rom print |
| 189 | coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, |
| 190 | offset 0x0 |
| 191 | Alignment: 64 bytes |
Steve Goodrich | f026912 | 2012-05-18 11:18:47 -0600 | [diff] [blame] | 192 | |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 193 | Name Offset Type Size |
Elyes HAOUAS | 2119d0b | 2020-02-16 10:01:33 +0100 | [diff] [blame] | 194 | cmos_layout.bin 0x0 CMOS layout 1159 |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 195 | fallback/romstage 0x4c0 stage 339756 |
Daniele Forsi | 53847a2 | 2014-07-22 18:00:56 +0200 | [diff] [blame] | 196 | fallback/ramstage 0x53440 stage 186664 |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 197 | fallback/payload 0x80dc0 payload 51526 |
| 198 | config 0x8d740 raw 3324 |
| 199 | (empty) 0x8e480 null 3610440 |
Cristian Măgherușan-Stanciu | d367b00 | 2011-06-19 03:03:28 +0200 | [diff] [blame] | 200 | |
Vadim Bendebury | 9202473d | 2011-09-21 14:46:43 -0700 | [diff] [blame] | 201 | config COLLECT_TIMESTAMPS |
| 202 | bool "Create a table of timestamps collected during boot" |
Paul Menzel | 4e4a763 | 2015-10-11 11:57:44 +0200 | [diff] [blame] | 203 | default y if ARCH_X86 |
Vadim Bendebury | 9202473d | 2011-09-21 14:46:43 -0700 | [diff] [blame] | 204 | help |
Uwe Hermann | ad8c95f | 2012-04-12 22:00:03 +0200 | [diff] [blame] | 205 | Make coreboot create a table of timer-ID/timer-value pairs to |
| 206 | allow measuring time spent at different phases of the boot process. |
| 207 | |
Martin Roth | b22bbe2 | 2018-03-07 15:32:16 -0700 | [diff] [blame] | 208 | config TIMESTAMPS_ON_CONSOLE |
| 209 | bool "Print the timestamp values on the console" |
| 210 | default n |
| 211 | depends on COLLECT_TIMESTAMPS |
| 212 | help |
Kyösti Mälkki | 8b93cb7 | 2020-01-09 08:41:46 +0200 | [diff] [blame] | 213 | Print the timestamps to the debug console if enabled at level info. |
Martin Roth | b22bbe2 | 2018-03-07 15:32:16 -0700 | [diff] [blame] | 214 | |
Patrick Georgi | 7e9b9d8 | 2012-04-30 21:06:10 +0200 | [diff] [blame] | 215 | config USE_BLOBS |
| 216 | bool "Allow use of binary-only repository" |
Felix Held | a6b887e | 2019-12-28 19:10:12 +0100 | [diff] [blame] | 217 | default y |
Patrick Georgi | 7e9b9d8 | 2012-04-30 21:06:10 +0200 | [diff] [blame] | 218 | help |
| 219 | This draws in the blobs repository, which contains binary files that |
| 220 | might be required for some chipsets or boards. |
| 221 | This flag ensures that a "Free" option remains available for users. |
| 222 | |
Marshall Dawson | 20ce400 | 2019-10-28 15:55:03 -0600 | [diff] [blame] | 223 | config USE_AMD_BLOBS |
| 224 | bool "Allow AMD blobs repository (with license agreement)" |
| 225 | depends on USE_BLOBS |
| 226 | help |
| 227 | This draws in the amd_blobs repository, which contains binary files |
| 228 | distributed by AMD, including VBIOS, PSP bootloaders, SMU firmwares, |
| 229 | etc. Selecting this item to download or clone the repo implies your |
| 230 | agreement to the AMD license agreement. A copy of the license text |
| 231 | may be reviewed by reading Documentation/soc/amd/amdblobs_license.md, |
| 232 | and your copy of the license is present in the repo once downloaded. |
| 233 | |
| 234 | Note that for some products, omitting PSP, SMU images, or other items |
| 235 | may result in a nonbooting coreboot.rom. |
| 236 | |
Julius Werner | bc1cb38 | 2020-06-18 15:03:22 -0700 | [diff] [blame] | 237 | config USE_QC_BLOBS |
Benjamin Doron | 999d29e | 2020-07-01 01:47:22 +0000 | [diff] [blame] | 238 | bool "Allow QC blobs repository (selecting this agrees to the license!)" |
Julius Werner | bc1cb38 | 2020-06-18 15:03:22 -0700 | [diff] [blame] | 239 | depends on USE_BLOBS |
| 240 | help |
| 241 | This draws in the qc_blobs repository, which contains binary files |
| 242 | distributed by Qualcomm that are required to build firmware for |
| 243 | certain Qualcomm SoCs (including QcLib, QC-SEC, qtiseclib and QUP |
| 244 | firmware). If you say Y here you are implicitly agreeing to the |
| 245 | Qualcomm license agreement which can be found at: |
| 246 | https://review.coreboot.org/cgit/qc_blobs.git/tree/LICENSE |
| 247 | |
| 248 | ***************************************************** |
| 249 | PLEASE MAKE SURE YOU READ AND AGREE TO ALL TERMS IN |
| 250 | ABOVE LICENSE AGREEMENT BEFORE SELECTING THIS OPTION! |
| 251 | ***************************************************** |
| 252 | |
| 253 | Not selecting this option means certain Qualcomm SoCs and related |
| 254 | mainboards cannot be built and will be hidden from the "Mainboards" |
| 255 | section. |
| 256 | |
Stefan Reinauer | d37ab45 | 2012-12-18 16:23:28 -0800 | [diff] [blame] | 257 | config COVERAGE |
| 258 | bool "Code coverage support" |
| 259 | depends on COMPILER_GCC |
Stefan Reinauer | d37ab45 | 2012-12-18 16:23:28 -0800 | [diff] [blame] | 260 | help |
| 261 | Add code coverage support for coreboot. This will store code |
| 262 | coverage information in CBMEM for extraction from user space. |
| 263 | If unsure, say N. |
| 264 | |
Ryan Salsamendi | ab37e9a | 2017-06-11 21:07:31 -0700 | [diff] [blame] | 265 | config UBSAN |
| 266 | bool "Undefined behavior sanitizer support" |
| 267 | default n |
| 268 | help |
| 269 | Instrument the code with checks for undefined behavior. If unsure, |
| 270 | say N because it adds a small performance penalty and may abort |
| 271 | on code that happens to work in spite of the UB. |
| 272 | |
Harshit Sharma | 0b1ec5a | 2020-08-05 21:16:31 -0700 | [diff] [blame] | 273 | config HAVE_ASAN_IN_ROMSTAGE |
| 274 | bool |
Harshit Sharma | 2bcaba0 | 2020-06-09 20:25:16 -0700 | [diff] [blame] | 275 | default n |
Harshit Sharma | 0b1ec5a | 2020-08-05 21:16:31 -0700 | [diff] [blame] | 276 | |
| 277 | config ASAN_IN_ROMSTAGE |
| 278 | bool |
| 279 | default n |
| 280 | help |
| 281 | Enable address sanitizer in romstage for platform. |
| 282 | |
| 283 | config HAVE_ASAN_IN_RAMSTAGE |
| 284 | bool |
| 285 | default n |
| 286 | |
| 287 | config ASAN_IN_RAMSTAGE |
| 288 | bool |
| 289 | default n |
| 290 | help |
| 291 | Enable address sanitizer in ramstage for platform. |
| 292 | |
| 293 | config ASAN |
| 294 | bool "Address sanitizer support" |
| 295 | default n |
| 296 | select ASAN_IN_ROMSTAGE if HAVE_ASAN_IN_ROMSTAGE |
| 297 | select ASAN_IN_RAMSTAGE if HAVE_ASAN_IN_RAMSTAGE |
Harshit Sharma | 2bcaba0 | 2020-06-09 20:25:16 -0700 | [diff] [blame] | 298 | help |
| 299 | Enable address sanitizer - runtime memory debugger, |
| 300 | designed to find out-of-bounds accesses and use-after-scope bugs. |
| 301 | |
| 302 | This feature consumes up to 1/8 of available memory and brings about |
| 303 | ~1.5x performance slowdown. |
| 304 | |
| 305 | If unsure, say N. |
| 306 | |
Harshit Sharma | 0b1ec5a | 2020-08-05 21:16:31 -0700 | [diff] [blame] | 307 | if ASAN |
Harshit Sharma | 3b9cc85 | 2020-07-06 23:38:31 -0700 | [diff] [blame] | 308 | comment "Before using this feature, make sure that " |
| 309 | comment "asan_shadow_offset_callback patch is applied to GCC." |
| 310 | endif |
| 311 | |
Kyösti Mälkki | 6766f4f | 2019-12-18 00:19:06 +0200 | [diff] [blame] | 312 | choice |
| 313 | prompt "Stage Cache for ACPI S3 resume" |
Kyösti Mälkki | 18a8ba4 | 2020-07-02 21:48:38 +0300 | [diff] [blame] | 314 | default NO_STAGE_CACHE if !HAVE_ACPI_RESUME |
Kyösti Mälkki | 6766f4f | 2019-12-18 00:19:06 +0200 | [diff] [blame] | 315 | default TSEG_STAGE_CACHE if SMM_TSEG |
| 316 | |
| 317 | config NO_STAGE_CACHE |
| 318 | bool "Disabled" |
| 319 | help |
| 320 | Do not save any component in stage cache for resume path. On resume, |
| 321 | all components would be read back from CBFS again. |
| 322 | |
Kyösti Mälkki | 0a4457f | 2019-08-01 20:29:14 +0300 | [diff] [blame] | 323 | config TSEG_STAGE_CACHE |
Kyösti Mälkki | 6766f4f | 2019-12-18 00:19:06 +0200 | [diff] [blame] | 324 | bool "TSEG" |
| 325 | depends on SMM_TSEG |
Stefan Reinauer | 58470e3 | 2014-10-17 13:08:36 +0200 | [diff] [blame] | 326 | help |
Kyösti Mälkki | 0a4457f | 2019-08-01 20:29:14 +0300 | [diff] [blame] | 327 | The option enables stage cache support for platform. Platform |
| 328 | can stash copies of postcar, ramstage and raw runtime data |
| 329 | inside SMM TSEG, to be restored on S3 resume path. |
| 330 | |
| 331 | config CBMEM_STAGE_CACHE |
Kyösti Mälkki | 6766f4f | 2019-12-18 00:19:06 +0200 | [diff] [blame] | 332 | bool "CBMEM" |
| 333 | depends on !SMM_TSEG |
Kyösti Mälkki | 0a4457f | 2019-08-01 20:29:14 +0300 | [diff] [blame] | 334 | help |
| 335 | The option enables stage cache support for platform. Platform |
| 336 | can stash copies of postcar, ramstage and raw runtime data |
| 337 | inside CBMEM. |
| 338 | |
| 339 | While the approach is faster than reloading stages from boot media |
| 340 | it is also a possible attack scenario via which OS can possibly |
| 341 | circumvent SMM locks and SPI write protections. |
| 342 | |
| 343 | If unsure, select 'N' |
Stefan Reinauer | 58470e3 | 2014-10-17 13:08:36 +0200 | [diff] [blame] | 344 | |
Kyösti Mälkki | 6766f4f | 2019-12-18 00:19:06 +0200 | [diff] [blame] | 345 | endchoice |
| 346 | |
Stefan Reinauer | 58470e3 | 2014-10-17 13:08:36 +0200 | [diff] [blame] | 347 | config UPDATE_IMAGE |
| 348 | bool "Update existing coreboot.rom image" |
Stefan Reinauer | 58470e3 | 2014-10-17 13:08:36 +0200 | [diff] [blame] | 349 | help |
| 350 | If this option is enabled, no new coreboot.rom file |
| 351 | is created. Instead it is expected that there already |
| 352 | is a suitable file for further processing. |
| 353 | The bootblock will not be modified. |
| 354 | |
Martin Roth | 5942e06 | 2016-01-20 14:59:21 -0700 | [diff] [blame] | 355 | If unsure, select 'N' |
| 356 | |
Konstantin Aladyshev | 6544cb3 | 2015-01-24 18:52:10 +0400 | [diff] [blame] | 357 | config BOOTSPLASH_IMAGE |
| 358 | bool "Add a bootsplash image" |
| 359 | help |
| 360 | Select this option if you have a bootsplash image that you would |
| 361 | like to add to your ROM. |
| 362 | |
| 363 | This will only add the image to the ROM. To actually run it check |
| 364 | options under 'Display' section. |
| 365 | |
| 366 | config BOOTSPLASH_FILE |
| 367 | string "Bootsplash path and filename" |
| 368 | depends on BOOTSPLASH_IMAGE |
Martin Roth | 75e5cb7 | 2016-12-15 15:05:37 -0700 | [diff] [blame] | 369 | # Default value set at the end of the file |
Konstantin Aladyshev | 6544cb3 | 2015-01-24 18:52:10 +0400 | [diff] [blame] | 370 | help |
| 371 | The path and filename of the file to use as graphical bootsplash |
| 372 | screen. The file format has to be jpg. |
| 373 | |
Duncan Laurie | 36e6c6f | 2020-05-09 19:20:10 -0700 | [diff] [blame] | 374 | config FW_CONFIG |
| 375 | bool "Firmware Configuration Probing" |
| 376 | default n |
| 377 | help |
| 378 | Enable support for probing devices with fw_config. This is a simple |
| 379 | bitmask broken into fields and options for probing. |
| 380 | |
| 381 | config FW_CONFIG_SOURCE_CBFS |
| 382 | bool "Obtain Firmware Configuration value from CBFS" |
| 383 | depends on FW_CONFIG |
| 384 | default n |
| 385 | help |
| 386 | With this option enabled coreboot will look for the 32bit firmware |
| 387 | configuration value in CBFS at the selected prefix with the file name |
| 388 | "fw_config". This option will override other sources and allow the |
| 389 | local image to preempt the mainboard selected source. |
| 390 | |
| 391 | config FW_CONFIG_SOURCE_CHROMEEC_CBI |
| 392 | bool "Obtain Firmware Configuration value from Google Chrome EC CBI" |
| 393 | depends on FW_CONFIG && EC_GOOGLE_CHROMEEC |
| 394 | default n |
| 395 | help |
| 396 | This option tells coreboot to read the firmware configuration value |
| 397 | from the Google Chrome Embedded Controller CBI interface. This source |
| 398 | is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was |
| 399 | found in CBFS. |
| 400 | |
Nico Huber | 94cdec6 | 2019-06-06 19:36:02 +0200 | [diff] [blame] | 401 | config HAVE_RAMPAYLOAD |
| 402 | bool |
| 403 | |
Subrata Banik | 7e893a0 | 2019-05-06 14:17:41 +0530 | [diff] [blame] | 404 | config RAMPAYLOAD |
| 405 | bool "Enable coreboot flow without executing ramstage" |
Subrata Banik | 86dbe0f | 2019-06-28 18:18:37 +0530 | [diff] [blame] | 406 | default y if ARCH_X86 |
Nico Huber | 94cdec6 | 2019-06-06 19:36:02 +0200 | [diff] [blame] | 407 | depends on HAVE_RAMPAYLOAD |
Subrata Banik | 7e893a0 | 2019-05-06 14:17:41 +0530 | [diff] [blame] | 408 | help |
| 409 | If this option is enabled, coreboot flow will skip ramstage |
| 410 | loading and execution of ramstage to load payload. |
| 411 | |
| 412 | Instead it is expected to load payload from postcar stage itself. |
| 413 | |
| 414 | In this flow coreboot will perform basic x86 initialization |
| 415 | (DRAM resource allocation), MTRR programming, |
| 416 | Skip PCI enumeration logic and only allocate BAR for fixed devices |
| 417 | (bootable devices, TPM over GSPI). |
| 418 | |
Subrata Banik | 37bead6 | 2020-02-09 19:13:52 +0530 | [diff] [blame] | 419 | config HAVE_CONFIGURABLE_RAMSTAGE |
| 420 | bool |
| 421 | |
Ronald G. Minnich | 466ca2c | 2019-10-22 02:02:24 +0000 | [diff] [blame] | 422 | config CONFIGURABLE_RAMSTAGE |
| 423 | bool "Enable a configurable ramstage." |
| 424 | default y if ARCH_X86 |
Subrata Banik | 37bead6 | 2020-02-09 19:13:52 +0530 | [diff] [blame] | 425 | depends on HAVE_CONFIGURABLE_RAMSTAGE |
Ronald G. Minnich | 466ca2c | 2019-10-22 02:02:24 +0000 | [diff] [blame] | 426 | help |
| 427 | A configurable ramstage allows you to select which parts of the ramstage |
| 428 | to run. Currently, we can only select a minimal PCI scanning step. |
| 429 | The minimal PCI scanning will only check those parts that are enabled |
| 430 | in the devicetree.cb. By convention none of those devices should be bridges. |
| 431 | |
| 432 | config MINIMAL_PCI_SCANNING |
| 433 | bool "Enable minimal PCI scanning" |
Subrata Banik | 1cb26a6 | 2020-02-09 19:35:16 +0530 | [diff] [blame] | 434 | depends on CONFIGURABLE_RAMSTAGE && PCI |
Ronald G. Minnich | 466ca2c | 2019-10-22 02:02:24 +0000 | [diff] [blame] | 435 | help |
Subrata Banik | 1cb26a6 | 2020-02-09 19:35:16 +0530 | [diff] [blame] | 436 | If this option is enabled, coreboot will scan only PCI devices |
Ronald G. Minnich | 466ca2c | 2019-10-22 02:02:24 +0000 | [diff] [blame] | 437 | marked as mandatory in devicetree.cb |
Uwe Hermann | c04be93 | 2009-10-05 13:55:28 +0000 | [diff] [blame] | 438 | endmenu |
| 439 | |
Martin Roth | 026e4dc | 2015-06-19 23:17:15 -0600 | [diff] [blame] | 440 | menu "Mainboard" |
| 441 | |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 442 | source "src/mainboard/Kconfig" |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 443 | |
Marshall Dawson | e937513 | 2016-09-04 08:38:33 -0600 | [diff] [blame] | 444 | config DEVICETREE |
| 445 | string |
| 446 | default "devicetree.cb" |
| 447 | help |
| 448 | This symbol allows mainboards to select a different file under their |
| 449 | mainboard directory for the devicetree.cb file. This allows the board |
| 450 | variants that need different devicetrees to be in the same directory. |
| 451 | |
| 452 | Examples: "devicetree.variant.cb" |
| 453 | "variant/devicetree.cb" |
| 454 | |
Furquan Shaikh | f241998 | 2018-06-21 18:50:48 -0700 | [diff] [blame] | 455 | config OVERRIDE_DEVICETREE |
| 456 | string |
| 457 | default "" |
| 458 | help |
| 459 | This symbol allows variants to provide an override devicetree file to |
| 460 | override the registers and/or add new devices on top of the ones |
| 461 | provided by baseboard devicetree using CONFIG_DEVICETREE. |
| 462 | |
| 463 | Examples: "devicetree.variant-override.cb" |
| 464 | "variant/devicetree-override.cb" |
| 465 | |
Patrick Georgi | 8a3592e | 2015-09-16 18:10:52 +0200 | [diff] [blame] | 466 | config FMDFILE |
| 467 | string "fmap description file in fmd format" |
Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 468 | default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS |
Patrick Georgi | 8a3592e | 2015-09-16 18:10:52 +0200 | [diff] [blame] | 469 | default "" |
| 470 | help |
| 471 | The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE, |
| 472 | but in some cases more complex setups are required. |
| 473 | When an fmd is specified, it overrides the default format. |
| 474 | |
Arthur Heymans | 965881b | 2019-09-25 13:18:52 +0200 | [diff] [blame] | 475 | config CBFS_SIZE |
| 476 | hex "Size of CBFS filesystem in ROM" |
| 477 | depends on FMDFILE = "" |
| 478 | # Default value set at the end of the file |
| 479 | help |
| 480 | This is the part of the ROM actually managed by CBFS, located at the |
| 481 | end of the ROM (passed through cbfstool -o) on x86 and at at the start |
| 482 | of the ROM (passed through cbfstool -s) everywhere else. It defaults |
| 483 | to span the whole ROM on all but Intel systems that use an Intel Firmware |
| 484 | Descriptor. It can be overridden to make coreboot live alongside other |
| 485 | components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE |
| 486 | binaries. This symbol should only be used to generate a default FMAP and |
| 487 | is unused when a non-default fmd file is provided via CONFIG_FMDFILE. |
| 488 | |
Martin Roth | da1ca20 | 2015-12-26 16:51:16 -0700 | [diff] [blame] | 489 | endmenu |
| 490 | |
Martin Roth | b09a569 | 2016-01-24 19:38:33 -0700 | [diff] [blame] | 491 | # load site-local kconfig to allow user specific defaults and overrides |
| 492 | source "site-local/Kconfig" |
| 493 | |
Vladimir Serbinenko | a9db82f | 2014-10-16 13:21:47 +0200 | [diff] [blame] | 494 | config SYSTEM_TYPE_LAPTOP |
Martin Roth | 595e777 | 2015-04-26 18:53:26 -0600 | [diff] [blame] | 495 | default n |
| 496 | bool |
Vladimir Serbinenko | a9db82f | 2014-10-16 13:21:47 +0200 | [diff] [blame] | 497 | |
Duncan Laurie | 8312df4 | 2019-02-01 11:33:57 -0800 | [diff] [blame] | 498 | config SYSTEM_TYPE_TABLET |
| 499 | default n |
| 500 | bool |
| 501 | |
| 502 | config SYSTEM_TYPE_DETACHABLE |
| 503 | default n |
| 504 | bool |
| 505 | |
| 506 | config SYSTEM_TYPE_CONVERTIBLE |
| 507 | default n |
| 508 | bool |
| 509 | |
Werner Zeh | c0fb361 | 2016-01-14 15:08:36 +0100 | [diff] [blame] | 510 | config CBFS_AUTOGEN_ATTRIBUTES |
| 511 | default n |
| 512 | bool |
| 513 | help |
| 514 | If this option is selected, every file in cbfs which has a constraint |
| 515 | regarding position or alignment will get an additional file attribute |
| 516 | which describes this constraint. |
| 517 | |
Uwe Hermann | 63a8f2a | 2009-10-26 21:42:13 +0000 | [diff] [blame] | 518 | menu "Chipset" |
| 519 | |
Duncan Laurie | d211976 | 2015-06-08 18:11:56 -0700 | [diff] [blame] | 520 | comment "SoC" |
Chris Ching | aa8e5d3 | 2017-10-20 10:43:39 -0600 | [diff] [blame] | 521 | source "src/soc/*/Kconfig" |
Uwe Hermann | 63a8f2a | 2009-10-26 21:42:13 +0000 | [diff] [blame] | 522 | comment "CPU" |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 523 | source "src/cpu/Kconfig" |
Uwe Hermann | 63a8f2a | 2009-10-26 21:42:13 +0000 | [diff] [blame] | 524 | comment "Northbridge" |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 525 | source "src/northbridge/*/*/Kconfig" |
Angel Pons | f462b3d | 2021-01-20 00:36:31 +0100 | [diff] [blame] | 526 | source "src/northbridge/*/*/Kconfig.common" |
Uwe Hermann | 63a8f2a | 2009-10-26 21:42:13 +0000 | [diff] [blame] | 527 | comment "Southbridge" |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 528 | source "src/southbridge/*/*/Kconfig" |
Angel Pons | c027ece | 2021-02-16 16:13:35 +0100 | [diff] [blame] | 529 | source "src/southbridge/*/*/Kconfig.common" |
Uwe Hermann | 63a8f2a | 2009-10-26 21:42:13 +0000 | [diff] [blame] | 530 | comment "Super I/O" |
Omar Pakker | 57603e2 | 2016-07-29 23:31:45 +0200 | [diff] [blame] | 531 | source "src/superio/*/*/Kconfig" |
Sven Schnelle | 7592e8b | 2011-01-27 11:43:03 +0000 | [diff] [blame] | 532 | comment "Embedded Controllers" |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 533 | source "src/ec/acpi/Kconfig" |
| 534 | source "src/ec/*/*/Kconfig" |
Uwe Hermann | 63a8f2a | 2009-10-26 21:42:13 +0000 | [diff] [blame] | 535 | |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 536 | source "src/southbridge/intel/common/firmware/Kconfig" |
Martin Roth | e1523ec | 2015-06-19 22:30:43 -0600 | [diff] [blame] | 537 | source "src/vendorcode/*/Kconfig" |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 538 | |
Martin Roth | e1523ec | 2015-06-19 22:30:43 -0600 | [diff] [blame] | 539 | source "src/arch/*/Kconfig" |
| 540 | |
Duncan Laurie | e335c2e | 2020-07-29 16:28:43 -0700 | [diff] [blame] | 541 | config CHIPSET_DEVICETREE |
| 542 | string |
| 543 | default "" |
| 544 | help |
| 545 | This symbol allows a chipset to provide a set of default settings in |
| 546 | a devicetree which are common to all mainboards. This may include |
| 547 | devices (including alias names), chip drivers, register settings, |
| 548 | and others. This path is relative to the src/ directory. |
| 549 | |
| 550 | Example: "chipset.cb" |
| 551 | |
Uwe Hermann | 63a8f2a | 2009-10-26 21:42:13 +0000 | [diff] [blame] | 552 | endmenu |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 553 | |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 554 | source "src/device/Kconfig" |
Stefan Reinauer | 95a6396 | 2012-11-13 17:00:01 -0800 | [diff] [blame] | 555 | |
Rudolf Marek | d9c2549 | 2010-05-16 15:31:53 +0000 | [diff] [blame] | 556 | menu "Generic Drivers" |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 557 | source "src/drivers/*/Kconfig" |
Stefan Reinauer | 86ddd73 | 2016-03-11 20:22:28 -0800 | [diff] [blame] | 558 | source "src/drivers/*/*/Kconfig" |
Duncan Laurie | 2cc126b | 2020-08-28 19:46:35 +0000 | [diff] [blame] | 559 | source "src/drivers/*/*/*/Kconfig" |
Lee Leahy | 48dbc66 | 2017-05-08 16:56:03 -0700 | [diff] [blame] | 560 | source "src/commonlib/storage/Kconfig" |
Rudolf Marek | d9c2549 | 2010-05-16 15:31:53 +0000 | [diff] [blame] | 561 | endmenu |
| 562 | |
Philipp Deppenwiese | 1899fbe | 2017-10-16 17:09:33 +0200 | [diff] [blame] | 563 | menu "Security" |
| 564 | |
| 565 | source "src/security/Kconfig" |
Wim Vervoorn | e32d16f | 2019-11-14 14:10:28 +0100 | [diff] [blame] | 566 | source "src/vendorcode/eltan/security/Kconfig" |
Philipp Deppenwiese | 1899fbe | 2017-10-16 17:09:33 +0200 | [diff] [blame] | 567 | |
| 568 | endmenu |
| 569 | |
Martin Roth | 09210a1 | 2016-05-17 11:28:23 -0600 | [diff] [blame] | 570 | source "src/acpi/Kconfig" |
| 571 | |
Aaron Durbin | 4a36c4e | 2016-08-11 11:02:26 -0500 | [diff] [blame] | 572 | # This option is for the current boards/chipsets where SPI flash |
| 573 | # is not the boot device. Currently nearly all boards/chipsets assume |
| 574 | # SPI flash is the boot device. |
| 575 | config BOOT_DEVICE_NOT_SPI_FLASH |
| 576 | bool |
| 577 | default n |
| 578 | |
| 579 | config BOOT_DEVICE_SPI_FLASH |
| 580 | bool |
| 581 | default y if !BOOT_DEVICE_NOT_SPI_FLASH |
| 582 | default n |
| 583 | |
Aaron Durbin | 16c173f | 2016-08-11 14:04:10 -0500 | [diff] [blame] | 584 | config BOOT_DEVICE_MEMORY_MAPPED |
| 585 | bool |
| 586 | default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH |
| 587 | default n |
| 588 | help |
| 589 | Inform system if SPI is memory-mapped or not. |
| 590 | |
Aaron Durbin | e8e118d | 2016-08-12 15:00:10 -0500 | [diff] [blame] | 591 | config BOOT_DEVICE_SUPPORTS_WRITES |
| 592 | bool |
| 593 | default n |
| 594 | help |
| 595 | Indicate that the platform has writable boot device |
| 596 | support. |
| 597 | |
Patrick Georgi | 0770f25 | 2015-04-22 13:28:21 +0200 | [diff] [blame] | 598 | config RTC |
| 599 | bool |
| 600 | default n |
| 601 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 602 | config HEAP_SIZE |
| 603 | hex |
Marty E. Plummer | 0987e43 | 2019-04-22 20:46:27 -0500 | [diff] [blame] | 604 | default 0x100000 if FLATTENED_DEVICE_TREE |
Myles Watson | 04000f4 | 2009-10-16 19:12:49 +0000 | [diff] [blame] | 605 | default 0x4000 |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 606 | |
Julius Werner | c3e7c4e | 2014-09-19 13:18:16 -0700 | [diff] [blame] | 607 | config STACK_SIZE |
| 608 | hex |
Julius Werner | 66a476a | 2015-10-12 16:45:21 -0700 | [diff] [blame] | 609 | default 0x1000 if ARCH_X86 |
| 610 | default 0x0 |
Julius Werner | c3e7c4e | 2014-09-19 13:18:16 -0700 | [diff] [blame] | 611 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 612 | config MAX_CPUS |
| 613 | int |
| 614 | default 1 |
| 615 | |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 616 | source "src/console/Kconfig" |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 617 | |
| 618 | config HAVE_ACPI_RESUME |
| 619 | bool |
| 620 | default n |
| 621 | |
Wim Vervoorn | bccc7e7 | 2020-01-15 11:31:25 +0100 | [diff] [blame] | 622 | config DISABLE_ACPI_HIBERNATE |
| 623 | bool |
| 624 | default n |
| 625 | help |
| 626 | Removes S4 from the available sleepstates |
| 627 | |
Aaron Durbin | 87c9fae | 2016-01-22 15:26:04 -0600 | [diff] [blame] | 628 | config RESUME_PATH_SAME_AS_BOOT |
| 629 | bool |
| 630 | default y if ARCH_X86 |
| 631 | depends on HAVE_ACPI_RESUME |
| 632 | help |
| 633 | This option indicates that when a system resumes it takes the |
| 634 | same path as a regular boot. e.g. an x86 system runs from the |
| 635 | reset vector at 0xfffffff0 on both resume and warm/cold boot. |
| 636 | |
Kyösti Mälkki | 76c4386 | 2019-07-01 17:25:41 +0300 | [diff] [blame] | 637 | config NO_MONOTONIC_TIMER |
Aaron Durbin | a421791 | 2013-04-29 22:31:51 -0500 | [diff] [blame] | 638 | def_bool n |
Kyösti Mälkki | 76c4386 | 2019-07-01 17:25:41 +0300 | [diff] [blame] | 639 | |
| 640 | config HAVE_MONOTONIC_TIMER |
| 641 | bool |
| 642 | depends on !NO_MONOTONIC_TIMER |
Kyösti Mälkki | b28b6b5 | 2019-07-01 15:38:25 +0300 | [diff] [blame] | 643 | default y |
Aaron Durbin | a421791 | 2013-04-29 22:31:51 -0500 | [diff] [blame] | 644 | help |
| 645 | The board/chipset provides a monotonic timer. |
| 646 | |
Aaron Durbin | e5e3630 | 2014-09-25 10:05:15 -0500 | [diff] [blame] | 647 | config GENERIC_UDELAY |
Kyösti Mälkki | 76c4386 | 2019-07-01 17:25:41 +0300 | [diff] [blame] | 648 | bool |
Aaron Durbin | e5e3630 | 2014-09-25 10:05:15 -0500 | [diff] [blame] | 649 | depends on HAVE_MONOTONIC_TIMER |
Kyösti Mälkki | 76c4386 | 2019-07-01 17:25:41 +0300 | [diff] [blame] | 650 | default y if !ARCH_X86 |
Aaron Durbin | e5e3630 | 2014-09-25 10:05:15 -0500 | [diff] [blame] | 651 | help |
| 652 | The board/chipset uses a generic udelay function utilizing the |
| 653 | monotonic timer. |
| 654 | |
Aaron Durbin | 340ca91 | 2013-04-30 09:58:12 -0500 | [diff] [blame] | 655 | config TIMER_QUEUE |
| 656 | def_bool n |
| 657 | depends on HAVE_MONOTONIC_TIMER |
| 658 | help |
Kyösti Mälkki | ecd8424 | 2013-09-13 07:57:49 +0300 | [diff] [blame] | 659 | Provide a timer queue for performing time-based callbacks. |
Aaron Durbin | 340ca91 | 2013-04-30 09:58:12 -0500 | [diff] [blame] | 660 | |
Aaron Durbin | 4409a5e | 2013-05-06 12:20:52 -0500 | [diff] [blame] | 661 | config COOP_MULTITASKING |
| 662 | def_bool n |
Aaron Durbin | 38c326d | 2013-05-06 12:22:23 -0500 | [diff] [blame] | 663 | depends on TIMER_QUEUE && ARCH_X86 |
Aaron Durbin | 4409a5e | 2013-05-06 12:20:52 -0500 | [diff] [blame] | 664 | help |
| 665 | Cooperative multitasking allows callbacks to be multiplexed on the |
| 666 | main thread of ramstage. With this enabled it allows for multiple |
| 667 | execution paths to take place when they have udelay() calls within |
| 668 | their code. |
| 669 | |
| 670 | config NUM_THREADS |
| 671 | int |
| 672 | default 4 |
| 673 | depends on COOP_MULTITASKING |
| 674 | help |
| 675 | How many execution threads to cooperatively multitask with. |
| 676 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 677 | config HAVE_OPTION_TABLE |
| 678 | bool |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 679 | default n |
Uwe Hermann | 6ba13bb | 2009-10-15 17:49:07 +0000 | [diff] [blame] | 680 | help |
| 681 | This variable specifies whether a given board has a cmos.layout |
| 682 | file containing NVRAM/CMOS bit definitions. |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 683 | It defaults to 'n' but can be selected in mainboard/*/Kconfig. |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 684 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 685 | config PCI_IO_CFG_EXT |
| 686 | bool |
| 687 | default n |
| 688 | |
| 689 | config IOAPIC |
| 690 | bool |
| 691 | default n |
| 692 | |
Myles Watson | 45bb25f | 2009-09-22 18:49:08 +0000 | [diff] [blame] | 693 | config USE_WATCHDOG_ON_BOOT |
| 694 | bool |
| 695 | default n |
| 696 | |
Myles Watson | 45bb25f | 2009-09-22 18:49:08 +0000 | [diff] [blame] | 697 | config GFXUMA |
| 698 | bool |
Myles Watson | d73c1b5 | 2009-10-26 15:14:07 +0000 | [diff] [blame] | 699 | default n |
Myles Watson | 45bb25f | 2009-09-22 18:49:08 +0000 | [diff] [blame] | 700 | help |
| 701 | Enable Unified Memory Architecture for graphics. |
| 702 | |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame] | 703 | config HAVE_MP_TABLE |
| 704 | bool |
Uwe Hermann | 6ba13bb | 2009-10-15 17:49:07 +0000 | [diff] [blame] | 705 | help |
| 706 | This variable specifies whether a given board has MP table support. |
| 707 | It is usually set in mainboard/*/Kconfig. |
| 708 | Whether or not the MP table is actually generated by coreboot |
| 709 | is configurable by the user via GENERATE_MP_TABLE. |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame] | 710 | |
| 711 | config HAVE_PIRQ_TABLE |
| 712 | bool |
Uwe Hermann | 6ba13bb | 2009-10-15 17:49:07 +0000 | [diff] [blame] | 713 | help |
| 714 | This variable specifies whether a given board has PIRQ table support. |
| 715 | It is usually set in mainboard/*/Kconfig. |
| 716 | Whether or not the PIRQ table is actually generated by coreboot |
| 717 | is configurable by the user via GENERATE_PIRQ_TABLE. |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame] | 718 | |
Aaron Durbin | 9420a52 | 2015-11-17 16:31:00 -0600 | [diff] [blame] | 719 | config ACPI_NHLT |
| 720 | bool |
| 721 | default n |
| 722 | help |
| 723 | Build support for NHLT (non HD Audio) ACPI table generation. |
| 724 | |
Myles Watson | d73c1b5 | 2009-10-26 15:14:07 +0000 | [diff] [blame] | 725 | #These Options are here to avoid "undefined" warnings. |
| 726 | #The actual selection and help texts are in the following menu. |
| 727 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 728 | menu "System tables" |
Myles Watson | 45bb25f | 2009-09-22 18:49:08 +0000 | [diff] [blame] | 729 | |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame] | 730 | config GENERATE_MP_TABLE |
Stefan Reinauer | 56cd70b | 2012-11-13 17:33:08 -0800 | [diff] [blame] | 731 | prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC |
| 732 | bool |
| 733 | default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC |
Uwe Hermann | 6ba13bb | 2009-10-15 17:49:07 +0000 | [diff] [blame] | 734 | help |
| 735 | Generate an MP table (conforming to the Intel MultiProcessor |
| 736 | specification 1.4) for this board. |
| 737 | |
| 738 | If unsure, say Y. |
Myles Watson | 45bb25f | 2009-09-22 18:49:08 +0000 | [diff] [blame] | 739 | |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame] | 740 | config GENERATE_PIRQ_TABLE |
Stefan Reinauer | 56cd70b | 2012-11-13 17:33:08 -0800 | [diff] [blame] | 741 | prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE |
| 742 | bool |
| 743 | default HAVE_PIRQ_TABLE |
Uwe Hermann | 6ba13bb | 2009-10-15 17:49:07 +0000 | [diff] [blame] | 744 | help |
| 745 | Generate a PIRQ table for this board. |
| 746 | |
| 747 | If unsure, say Y. |
Myles Watson | 45bb25f | 2009-09-22 18:49:08 +0000 | [diff] [blame] | 748 | |
Sven Schnelle | 164bcfd | 2011-08-14 20:56:34 +0200 | [diff] [blame] | 749 | config GENERATE_SMBIOS_TABLES |
| 750 | depends on ARCH_X86 |
| 751 | bool "Generate SMBIOS tables" |
| 752 | default y |
| 753 | help |
| 754 | Generate SMBIOS tables for this board. |
| 755 | |
| 756 | If unsure, say Y. |
| 757 | |
Vladimir Serbinenko | 0afdec4 | 2015-05-30 23:08:26 +0200 | [diff] [blame] | 758 | config SMBIOS_PROVIDED_BY_MOBO |
| 759 | bool |
| 760 | default n |
| 761 | |
Stefan Reinauer | 6023ca4 | 2014-10-17 13:28:15 +0200 | [diff] [blame] | 762 | config MAINBOARD_SERIAL_NUMBER |
Nico Huber | ebd8a4f | 2017-11-01 09:49:16 +0100 | [diff] [blame] | 763 | prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO |
| 764 | string |
Stefan Reinauer | 6023ca4 | 2014-10-17 13:28:15 +0200 | [diff] [blame] | 765 | depends on GENERATE_SMBIOS_TABLES |
| 766 | default "123456789" |
Martin Roth | 595e777 | 2015-04-26 18:53:26 -0600 | [diff] [blame] | 767 | help |
Stefan Reinauer | 6023ca4 | 2014-10-17 13:28:15 +0200 | [diff] [blame] | 768 | The Serial Number to store in SMBIOS structures. |
| 769 | |
| 770 | config MAINBOARD_VERSION |
Nico Huber | ebd8a4f | 2017-11-01 09:49:16 +0100 | [diff] [blame] | 771 | prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO |
| 772 | string |
Stefan Reinauer | 6023ca4 | 2014-10-17 13:28:15 +0200 | [diff] [blame] | 773 | depends on GENERATE_SMBIOS_TABLES |
| 774 | default "1.0" |
| 775 | help |
| 776 | The Version Number to store in SMBIOS structures. |
| 777 | |
| 778 | config MAINBOARD_SMBIOS_MANUFACTURER |
Nico Huber | ebd8a4f | 2017-11-01 09:49:16 +0100 | [diff] [blame] | 779 | prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO |
| 780 | string |
Stefan Reinauer | 6023ca4 | 2014-10-17 13:28:15 +0200 | [diff] [blame] | 781 | depends on GENERATE_SMBIOS_TABLES |
| 782 | default MAINBOARD_VENDOR |
| 783 | help |
| 784 | Override the default Manufacturer stored in SMBIOS structures. |
| 785 | |
| 786 | config MAINBOARD_SMBIOS_PRODUCT_NAME |
Nico Huber | ebd8a4f | 2017-11-01 09:49:16 +0100 | [diff] [blame] | 787 | prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO |
| 788 | string |
Stefan Reinauer | 6023ca4 | 2014-10-17 13:28:15 +0200 | [diff] [blame] | 789 | depends on GENERATE_SMBIOS_TABLES |
| 790 | default MAINBOARD_PART_NUMBER |
| 791 | help |
| 792 | Override the default Product name stored in SMBIOS structures. |
| 793 | |
Johnny Lin | c746a74 | 2020-06-03 11:44:22 +0800 | [diff] [blame] | 794 | config VPD_SMBIOS_VERSION |
| 795 | bool "Populates SMBIOS type 0 version from the VPD_RO variable 'firmware_version'" |
| 796 | default n |
| 797 | depends on VPD && GENERATE_SMBIOS_TABLES |
| 798 | help |
| 799 | Selecting this option will read firmware_version from |
| 800 | VPD_RO and override SMBIOS type 0 version. One special |
| 801 | scenario of using this feature is to assign a BIOS version |
| 802 | to a coreboot image without the need to rebuild from source. |
| 803 | |
Myles Watson | 45bb25f | 2009-09-22 18:49:08 +0000 | [diff] [blame] | 804 | endmenu |
| 805 | |
Martin Roth | 21c0650 | 2016-02-04 19:52:27 -0700 | [diff] [blame] | 806 | source "payloads/Kconfig" |
Peter Stuge | a758ca2 | 2009-09-17 16:21:31 +0000 | [diff] [blame] | 807 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 808 | menu "Debugging" |
| 809 | |
Nico Huber | d67edca | 2018-11-13 19:28:07 +0100 | [diff] [blame] | 810 | comment "CPU Debug Settings" |
Arthur Heymans | aae8190 | 2019-11-04 21:50:21 +0100 | [diff] [blame] | 811 | source "src/cpu/*/Kconfig.debug_cpu" |
Nico Huber | d67edca | 2018-11-13 19:28:07 +0100 | [diff] [blame] | 812 | |
Arthur Heymans | 71bd7e4 | 2019-10-20 14:20:53 +0200 | [diff] [blame] | 813 | comment "BLOB Debug Settings" |
| 814 | source "src/drivers/intel/fsp*/Kconfig.debug_blob" |
| 815 | |
Nico Huber | d67edca | 2018-11-13 19:28:07 +0100 | [diff] [blame] | 816 | comment "General Debug Settings" |
| 817 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 818 | # TODO: Better help text and detailed instructions. |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 819 | config GDB_STUB |
Uwe Hermann | 5ec2c2b | 2009-08-25 00:53:22 +0000 | [diff] [blame] | 820 | bool "GDB debugging support" |
Rudolf Marek | 6588802 | 2012-03-25 20:51:16 +0200 | [diff] [blame] | 821 | default n |
Arthur Heymans | 8e98013 | 2019-11-04 09:33:04 +0100 | [diff] [blame] | 822 | depends on DRIVERS_UART |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 823 | help |
Uwe Hermann | 5ec2c2b | 2009-08-25 00:53:22 +0000 | [diff] [blame] | 824 | If enabled, you will be able to set breakpoints for gdb debugging. |
Stefan Reinauer | 8677a23 | 2010-12-11 20:33:41 +0000 | [diff] [blame] | 825 | See src/arch/x86/lib/c_start.S for details. |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 826 | |
Denis 'GNUtoo' Carikli | e4cece0 | 2012-06-22 15:56:37 +0200 | [diff] [blame] | 827 | config GDB_WAIT |
Denis 'GNUtoo' Carikli | 7d234f2 | 2015-12-10 21:58:52 +0100 | [diff] [blame] | 828 | bool "Wait for a GDB connection in the ramstage" |
Denis 'GNUtoo' Carikli | e4cece0 | 2012-06-22 15:56:37 +0200 | [diff] [blame] | 829 | default n |
| 830 | depends on GDB_STUB |
| 831 | help |
Denis 'GNUtoo' Carikli | 7d234f2 | 2015-12-10 21:58:52 +0100 | [diff] [blame] | 832 | If enabled, coreboot will wait for a GDB connection in the ramstage. |
| 833 | |
Denis 'GNUtoo' Carikli | e4cece0 | 2012-06-22 15:56:37 +0200 | [diff] [blame] | 834 | |
Julius Werner | d82e0cf | 2015-02-17 17:27:23 -0800 | [diff] [blame] | 835 | config FATAL_ASSERTS |
| 836 | bool "Halt when hitting a BUG() or assertion error" |
| 837 | default n |
| 838 | help |
| 839 | If enabled, coreboot will call hlt() on a BUG() or failed ASSERT(). |
| 840 | |
Nico Huber | 371a667 | 2018-11-13 22:06:40 +0100 | [diff] [blame] | 841 | config HAVE_DEBUG_GPIO |
| 842 | bool |
| 843 | |
| 844 | config DEBUG_GPIO |
| 845 | bool "Output verbose GPIO debug messages" |
| 846 | depends on HAVE_DEBUG_GPIO |
| 847 | |
Stefan Reinauer | fe42218 | 2012-05-02 16:33:18 -0700 | [diff] [blame] | 848 | config DEBUG_CBFS |
| 849 | bool "Output verbose CBFS debug messages" |
| 850 | default n |
Stefan Reinauer | fe42218 | 2012-05-02 16:33:18 -0700 | [diff] [blame] | 851 | help |
| 852 | This option enables additional CBFS related debug messages. |
| 853 | |
Jens Rottmann | 0d11f2d | 2010-08-26 12:46:02 +0000 | [diff] [blame] | 854 | config HAVE_DEBUG_RAM_SETUP |
| 855 | def_bool n |
| 856 | |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 857 | config DEBUG_RAM_SETUP |
| 858 | bool "Output verbose RAM init debug messages" |
| 859 | default n |
Jens Rottmann | 0d11f2d | 2010-08-26 12:46:02 +0000 | [diff] [blame] | 860 | depends on HAVE_DEBUG_RAM_SETUP |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 861 | help |
| 862 | This option enables additional RAM init related debug messages. |
| 863 | It is recommended to enable this when debugging issues on your |
| 864 | board which might be RAM init related. |
| 865 | |
| 866 | Note: This option will increase the size of the coreboot image. |
| 867 | |
| 868 | If unsure, say N. |
| 869 | |
Myles Watson | 80e914ff | 2010-06-01 19:25:31 +0000 | [diff] [blame] | 870 | config DEBUG_PIRQ |
| 871 | bool "Check PIRQ table consistency" |
| 872 | default n |
| 873 | depends on GENERATE_PIRQ_TABLE |
| 874 | help |
| 875 | If unsure, say N. |
| 876 | |
Jens Rottmann | 0d11f2d | 2010-08-26 12:46:02 +0000 | [diff] [blame] | 877 | config HAVE_DEBUG_SMBUS |
| 878 | def_bool n |
| 879 | |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 880 | config DEBUG_SMBUS |
| 881 | bool "Output verbose SMBus debug messages" |
| 882 | default n |
Jens Rottmann | 0d11f2d | 2010-08-26 12:46:02 +0000 | [diff] [blame] | 883 | depends on HAVE_DEBUG_SMBUS |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 884 | help |
| 885 | This option enables additional SMBus (and SPD) debug messages. |
| 886 | |
| 887 | Note: This option will increase the size of the coreboot image. |
| 888 | |
| 889 | If unsure, say N. |
| 890 | |
| 891 | config DEBUG_SMI |
| 892 | bool "Output verbose SMI debug messages" |
| 893 | default n |
| 894 | depends on HAVE_SMI_HANDLER |
Angel Pons | 12d48cd | 2020-10-03 12:22:04 +0200 | [diff] [blame] | 895 | select SPI_FLASH_SMM if EM100PRO_SPI_CONSOLE || CONSOLE_SPI_FLASH |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 896 | help |
| 897 | This option enables additional SMI related debug messages. |
| 898 | |
| 899 | Note: This option will increase the size of the coreboot image. |
| 900 | |
| 901 | If unsure, say N. |
| 902 | |
Kyösti Mälkki | 9446447 | 2020-06-13 13:45:42 +0300 | [diff] [blame] | 903 | config DEBUG_PERIODIC_SMI |
| 904 | bool "Trigger SMI periodically" |
| 905 | depends on DEBUG_SMI |
| 906 | |
Uwe Hermann | a953f37 | 2010-11-10 00:14:32 +0000 | [diff] [blame] | 907 | # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional |
| 908 | # printk(BIOS_DEBUG, ...) calls. |
| 909 | config DEBUG_MALLOC |
Marc Jones | cf3dcd6 | 2020-12-02 11:34:17 -0700 | [diff] [blame] | 910 | prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL |
Stefan Reinauer | 95a6396 | 2012-11-13 17:00:01 -0800 | [diff] [blame] | 911 | bool |
Uwe Hermann | a953f37 | 2010-11-10 00:14:32 +0000 | [diff] [blame] | 912 | default n |
Uwe Hermann | a953f37 | 2010-11-10 00:14:32 +0000 | [diff] [blame] | 913 | help |
| 914 | This option enables additional malloc related debug messages. |
| 915 | |
| 916 | Note: This option will increase the size of the coreboot image. |
| 917 | |
| 918 | If unsure, say N. |
Cristian Măgherușan-Stanciu | 9f52ea4 | 2011-07-02 00:44:39 +0300 | [diff] [blame] | 919 | |
Marc Jones | 5b5c52e | 2020-10-12 11:44:46 -0600 | [diff] [blame] | 920 | # Only visible if DEBUG_SPEW (8) is set. |
| 921 | config DEBUG_RESOURCES |
Marc Jones | cf3dcd6 | 2020-12-02 11:34:17 -0700 | [diff] [blame] | 922 | bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL |
Marc Jones | 5b5c52e | 2020-10-12 11:44:46 -0600 | [diff] [blame] | 923 | default n |
| 924 | help |
| 925 | This option enables additional PCI memory and IO debug messages. |
| 926 | Note: This option will increase the size of the coreboot image. |
| 927 | If unsure, say N. |
| 928 | |
Kyösti Mälkki | 6627795 | 2018-12-31 15:22:34 +0200 | [diff] [blame] | 929 | config DEBUG_CONSOLE_INIT |
| 930 | bool "Debug console initialisation code" |
| 931 | default n |
| 932 | help |
| 933 | With this option printk()'s are attempted before console hardware |
| 934 | initialisation has been completed. Your mileage may vary. |
| 935 | |
| 936 | Typically you will need to modify source in console_hw_init() such |
| 937 | that a working console appears before the one you want to debug. |
| 938 | |
| 939 | If unsure, say N. |
| 940 | |
Uwe Hermann | a953f37 | 2010-11-10 00:14:32 +0000 | [diff] [blame] | 941 | # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional |
| 942 | # printk(BIOS_DEBUG, ...) calls. |
Myles Watson | 6c9bc01 | 2010-09-07 22:30:15 +0000 | [diff] [blame] | 943 | config REALMODE_DEBUG |
Marc Jones | cf3dcd6 | 2020-12-02 11:34:17 -0700 | [diff] [blame] | 944 | prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL |
Stefan Reinauer | 95a6396 | 2012-11-13 17:00:01 -0800 | [diff] [blame] | 945 | bool |
Myles Watson | 6c9bc01 | 2010-09-07 22:30:15 +0000 | [diff] [blame] | 946 | default n |
Peter Stuge | 5015f79 | 2010-11-10 02:00:32 +0000 | [diff] [blame] | 947 | depends on PCI_OPTION_ROM_RUN_REALMODE |
Myles Watson | 6c9bc01 | 2010-09-07 22:30:15 +0000 | [diff] [blame] | 948 | help |
| 949 | This option enables additional x86emu related debug messages. |
| 950 | |
| 951 | Note: This option will increase the time to emulate a ROM. |
| 952 | |
| 953 | If unsure, say N. |
| 954 | |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 955 | config X86EMU_DEBUG |
| 956 | bool "Output verbose x86emu debug messages" |
| 957 | default n |
| 958 | depends on PCI_OPTION_ROM_RUN_YABEL |
| 959 | help |
| 960 | This option enables additional x86emu related debug messages. |
| 961 | |
| 962 | Note: This option will increase the size of the coreboot image. |
| 963 | |
| 964 | If unsure, say N. |
| 965 | |
| 966 | config X86EMU_DEBUG_JMP |
| 967 | bool "Trace JMP/RETF" |
| 968 | default n |
| 969 | depends on X86EMU_DEBUG |
| 970 | help |
| 971 | Print information about JMP and RETF opcodes from x86emu. |
| 972 | |
| 973 | Note: This option will increase the size of the coreboot image. |
| 974 | |
| 975 | If unsure, say N. |
| 976 | |
| 977 | config X86EMU_DEBUG_TRACE |
| 978 | bool "Trace all opcodes" |
| 979 | default n |
| 980 | depends on X86EMU_DEBUG |
| 981 | help |
| 982 | Print _all_ opcodes that are executed by x86emu. |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 983 | |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 984 | WARNING: This will produce a LOT of output and take a long time. |
| 985 | |
| 986 | Note: This option will increase the size of the coreboot image. |
| 987 | |
| 988 | If unsure, say N. |
| 989 | |
| 990 | config X86EMU_DEBUG_PNP |
| 991 | bool "Log Plug&Play accesses" |
| 992 | default n |
| 993 | depends on X86EMU_DEBUG |
| 994 | help |
| 995 | Print Plug And Play accesses made by option ROMs. |
| 996 | |
| 997 | Note: This option will increase the size of the coreboot image. |
| 998 | |
| 999 | If unsure, say N. |
| 1000 | |
| 1001 | config X86EMU_DEBUG_DISK |
| 1002 | bool "Log Disk I/O" |
| 1003 | default n |
| 1004 | depends on X86EMU_DEBUG |
| 1005 | help |
| 1006 | Print Disk I/O related messages. |
| 1007 | |
| 1008 | Note: This option will increase the size of the coreboot image. |
| 1009 | |
| 1010 | If unsure, say N. |
| 1011 | |
| 1012 | config X86EMU_DEBUG_PMM |
| 1013 | bool "Log PMM" |
| 1014 | default n |
| 1015 | depends on X86EMU_DEBUG |
| 1016 | help |
| 1017 | Print messages related to POST Memory Manager (PMM). |
| 1018 | |
| 1019 | Note: This option will increase the size of the coreboot image. |
| 1020 | |
| 1021 | If unsure, say N. |
| 1022 | |
| 1023 | |
| 1024 | config X86EMU_DEBUG_VBE |
| 1025 | bool "Debug VESA BIOS Extensions" |
| 1026 | default n |
| 1027 | depends on X86EMU_DEBUG |
| 1028 | help |
| 1029 | Print messages related to VESA BIOS Extension (VBE) functions. |
| 1030 | |
| 1031 | Note: This option will increase the size of the coreboot image. |
| 1032 | |
| 1033 | If unsure, say N. |
| 1034 | |
| 1035 | config X86EMU_DEBUG_INT10 |
| 1036 | bool "Redirect INT10 output to console" |
| 1037 | default n |
| 1038 | depends on X86EMU_DEBUG |
| 1039 | help |
| 1040 | Let INT10 (i.e. character output) calls print messages to debug output. |
| 1041 | |
| 1042 | Note: This option will increase the size of the coreboot image. |
| 1043 | |
| 1044 | If unsure, say N. |
| 1045 | |
| 1046 | config X86EMU_DEBUG_INTERRUPTS |
| 1047 | bool "Log intXX calls" |
| 1048 | default n |
| 1049 | depends on X86EMU_DEBUG |
| 1050 | help |
| 1051 | Print messages related to interrupt handling. |
| 1052 | |
| 1053 | Note: This option will increase the size of the coreboot image. |
| 1054 | |
| 1055 | If unsure, say N. |
| 1056 | |
| 1057 | config X86EMU_DEBUG_CHECK_VMEM_ACCESS |
| 1058 | bool "Log special memory accesses" |
| 1059 | default n |
| 1060 | depends on X86EMU_DEBUG |
| 1061 | help |
| 1062 | Print messages related to accesses to certain areas of the virtual |
| 1063 | memory (e.g. BDA (BIOS Data Area) or interrupt vectors) |
| 1064 | |
| 1065 | Note: This option will increase the size of the coreboot image. |
| 1066 | |
| 1067 | If unsure, say N. |
| 1068 | |
| 1069 | config X86EMU_DEBUG_MEM |
| 1070 | bool "Log all memory accesses" |
| 1071 | default n |
| 1072 | depends on X86EMU_DEBUG |
| 1073 | help |
| 1074 | Print memory accesses made by option ROM. |
| 1075 | Note: This also includes accesses to fetch instructions. |
| 1076 | |
| 1077 | Note: This option will increase the size of the coreboot image. |
| 1078 | |
| 1079 | If unsure, say N. |
| 1080 | |
| 1081 | config X86EMU_DEBUG_IO |
| 1082 | bool "Log IO accesses" |
| 1083 | default n |
| 1084 | depends on X86EMU_DEBUG |
| 1085 | help |
| 1086 | Print I/O accesses made by option ROM. |
| 1087 | |
| 1088 | Note: This option will increase the size of the coreboot image. |
| 1089 | |
| 1090 | If unsure, say N. |
| 1091 | |
Denis 'GNUtoo' Carikli | 4cdc5d6 | 2013-05-15 00:19:49 +0200 | [diff] [blame] | 1092 | config X86EMU_DEBUG_TIMINGS |
| 1093 | bool "Output timing information" |
| 1094 | default n |
Kyösti Mälkki | 91945fb | 2019-07-10 15:10:22 +0300 | [diff] [blame] | 1095 | depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER |
Denis 'GNUtoo' Carikli | 4cdc5d6 | 2013-05-15 00:19:49 +0200 | [diff] [blame] | 1096 | help |
| 1097 | Print timing information needed by i915tool. |
| 1098 | |
| 1099 | If unsure, say N. |
| 1100 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 1101 | config DEBUG_SPI_FLASH |
| 1102 | bool "Output verbose SPI flash debug messages" |
| 1103 | default n |
| 1104 | depends on SPI_FLASH |
| 1105 | help |
| 1106 | This option enables additional SPI flash related debug messages. |
| 1107 | |
Marc Jones | dc12daf | 2021-04-16 14:26:08 -0600 | [diff] [blame] | 1108 | config DEBUG_IPMI |
| 1109 | bool "Output verbose IPMI debug messages" |
| 1110 | default n |
| 1111 | depends on IPMI_KCS |
| 1112 | help |
| 1113 | This option enables additional IPMI related debug messages. |
| 1114 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1115 | if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8 |
| 1116 | # Only visible with the right southbridge and loglevel. |
| 1117 | config DEBUG_INTEL_ME |
| 1118 | bool "Verbose logging for Intel Management Engine" |
| 1119 | default n |
| 1120 | help |
| 1121 | Enable verbose logging for Intel Management Engine driver that |
| 1122 | is present on Intel 6-series chipsets. |
| 1123 | endif |
| 1124 | |
Marc Jones | 8b522db | 2020-10-12 11:58:46 -0600 | [diff] [blame] | 1125 | config DEBUG_FUNC |
| 1126 | bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 |
| 1127 | default n |
| 1128 | help |
| 1129 | This option enables additional function entry and exit debug messages |
Kyösti Mälkki | 8c99c27 | 2020-07-24 15:54:31 +0300 | [diff] [blame] | 1130 | for select functions. |
Marc Jones | 8b522db | 2020-10-12 11:58:46 -0600 | [diff] [blame] | 1131 | Note: This option will increase the size of the coreboot image. |
| 1132 | If unsure, say N. |
| 1133 | |
Stefan Reinauer | d37ab45 | 2012-12-18 16:23:28 -0800 | [diff] [blame] | 1134 | config DEBUG_COVERAGE |
| 1135 | bool "Debug code coverage" |
| 1136 | default n |
| 1137 | depends on COVERAGE |
| 1138 | help |
| 1139 | If enabled, the code coverage hooks in coreboot will output some |
| 1140 | information about the coverage data that is dumped. |
| 1141 | |
Jonathan Neuschäfer | fc04f9b | 2016-06-29 21:59:32 +0200 | [diff] [blame] | 1142 | config DEBUG_BOOT_STATE |
| 1143 | bool "Debug boot state machine" |
| 1144 | default n |
| 1145 | help |
| 1146 | Control debugging of the boot state machine. When selected displays |
| 1147 | the state boundaries in ramstage. |
| 1148 | |
Nico Huber | e84e625 | 2016-10-05 17:43:56 +0200 | [diff] [blame] | 1149 | config DEBUG_ADA_CODE |
| 1150 | bool "Compile debug code in Ada sources" |
| 1151 | default n |
| 1152 | help |
| 1153 | Add the compiler switch `-gnata` to compile code guarded by |
| 1154 | `pragma Debug`. |
| 1155 | |
Simon Glass | 46255f7 | 2018-07-12 15:26:07 -0600 | [diff] [blame] | 1156 | config HAVE_EM100_SUPPORT |
| 1157 | bool "Platform can support the Dediprog EM100 SPI emulator" |
| 1158 | help |
| 1159 | This is enabled by platforms which can support using the EM100. |
| 1160 | |
| 1161 | config EM100 |
| 1162 | bool "Configure image for EM100 usage" |
| 1163 | depends on HAVE_EM100_SUPPORT |
| 1164 | help |
| 1165 | The Dediprog EM100 SPI emulator allows fast loading of new SPI images |
| 1166 | over USB. However it only supports a maximum SPI clock of 20MHz and |
| 1167 | single data output. Enable this option to use a 20MHz SPI clock and |
| 1168 | disable "Dual Output Fast Read" Support. |
| 1169 | |
| 1170 | On AMD platforms this changes the SPI speed at run-time if the |
| 1171 | mainboard code supports this. On supported Intel platforms this works |
| 1172 | by changing the settings in the descriptor.bin file. |
| 1173 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 1174 | endmenu |
| 1175 | |
Martin Roth | 8e4aafb | 2016-12-15 15:25:15 -0700 | [diff] [blame] | 1176 | ############################################################################### |
| 1177 | # Set variables with no prompt - these can be set anywhere, and putting at |
| 1178 | # the end of this file gives the most flexibility. |
Nico Huber | 3db7653 | 2017-05-18 18:07:34 +0200 | [diff] [blame] | 1179 | |
| 1180 | source "src/lib/Kconfig" |
| 1181 | |
Myles Watson | 2e67273 | 2009-11-12 16:38:03 +0000 | [diff] [blame] | 1182 | config WARNINGS_ARE_ERRORS |
| 1183 | bool |
Edward O'Callaghan | 63f6dc7 | 2014-11-18 03:17:54 +1100 | [diff] [blame] | 1184 | default y |
Patrick Georgi | 436f99b | 2009-11-27 16:55:13 +0000 | [diff] [blame] | 1185 | |
Peter Stuge | 51eafde | 2010-10-13 06:23:02 +0000 | [diff] [blame] | 1186 | # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, |
| 1187 | # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are |
| 1188 | # mutually exclusive. One of these options must be selected in the |
| 1189 | # mainboard Kconfig if the chipset supports enabling and disabling of |
| 1190 | # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set |
| 1191 | # in mainboard/Kconfig to know if the button should be enabled or not. |
| 1192 | |
| 1193 | config POWER_BUTTON_DEFAULT_ENABLE |
| 1194 | def_bool n |
| 1195 | help |
| 1196 | Select when the board has a power button which can optionally be |
| 1197 | disabled by the user. |
| 1198 | |
| 1199 | config POWER_BUTTON_DEFAULT_DISABLE |
| 1200 | def_bool n |
| 1201 | help |
| 1202 | Select when the board has a power button which can optionally be |
| 1203 | enabled by the user, e.g. when the board ships with a jumper over |
| 1204 | the power switch contacts. |
| 1205 | |
| 1206 | config POWER_BUTTON_FORCE_ENABLE |
| 1207 | def_bool n |
| 1208 | help |
| 1209 | Select when the board requires that the power button is always |
| 1210 | enabled. |
| 1211 | |
| 1212 | config POWER_BUTTON_FORCE_DISABLE |
| 1213 | def_bool n |
| 1214 | help |
| 1215 | Select when the board requires that the power button is always |
| 1216 | disabled, e.g. when it has been hardwired to ground. |
| 1217 | |
| 1218 | config POWER_BUTTON_IS_OPTIONAL |
| 1219 | bool |
| 1220 | default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE |
| 1221 | default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE) |
| 1222 | help |
| 1223 | Internal option that controls ENABLE_POWER_BUTTON visibility. |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 1224 | |
| 1225 | config REG_SCRIPT |
| 1226 | bool |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 1227 | default n |
| 1228 | help |
| 1229 | Internal option that controls whether we compile in register scripts. |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 1230 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 1231 | config MAX_REBOOT_CNT |
| 1232 | int |
| 1233 | default 3 |
Timothy Pearson | 17ada2e | 2015-03-18 01:31:34 -0500 | [diff] [blame] | 1234 | help |
| 1235 | Internal option that sets the maximum number of bootblock executions allowed |
| 1236 | with the normal image enabled before assuming the normal image is defective |
Vadim Bendebury | 9c9c336 | 2014-07-23 09:40:02 -0700 | [diff] [blame] | 1237 | and switching to the fallback image. |
Martin Roth | 59ff340 | 2016-02-09 09:06:46 -0700 | [diff] [blame] | 1238 | |
Martin Roth | 8e4aafb | 2016-12-15 15:25:15 -0700 | [diff] [blame] | 1239 | config UNCOMPRESSED_RAMSTAGE |
| 1240 | bool |
| 1241 | |
| 1242 | config NO_XIP_EARLY_STAGES |
| 1243 | bool |
| 1244 | default n if ARCH_X86 |
| 1245 | default y |
| 1246 | help |
| 1247 | Identify if early stages are eXecute-In-Place(XIP). |
| 1248 | |
Martin Roth | 8e4aafb | 2016-12-15 15:25:15 -0700 | [diff] [blame] | 1249 | config EARLY_CBMEM_LIST |
| 1250 | bool |
| 1251 | default n |
| 1252 | help |
| 1253 | Enable display of CBMEM during romstage and postcar. |
| 1254 | |
| 1255 | config RELOCATABLE_MODULES |
| 1256 | bool |
| 1257 | help |
| 1258 | If RELOCATABLE_MODULES is selected then support is enabled for |
| 1259 | building relocatable modules in the RAM stage. Those modules can be |
| 1260 | loaded anywhere and all the relocations are handled automatically. |
| 1261 | |
Martin Roth | 8e4aafb | 2016-12-15 15:25:15 -0700 | [diff] [blame] | 1262 | config GENERIC_GPIO_LIB |
| 1263 | bool |
| 1264 | help |
| 1265 | If enabled, compile the generic GPIO library. A "generic" GPIO |
| 1266 | implies configurability usually found on SoCs, particularly the |
| 1267 | ability to control internal pull resistors. |
| 1268 | |
Martin Roth | 8e4aafb | 2016-12-15 15:25:15 -0700 | [diff] [blame] | 1269 | config BOOTBLOCK_CUSTOM |
| 1270 | # To be selected by arch, SoC or mainboard if it does not want use the normal |
| 1271 | # src/lib/bootblock.c#main() C entry point. |
| 1272 | bool |
| 1273 | |
Furquan Shaikh | 46514c2 | 2020-06-11 11:59:07 -0700 | [diff] [blame] | 1274 | config MEMLAYOUT_LD_FILE |
| 1275 | string |
Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 1276 | default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/memlayout.ld" |
Furquan Shaikh | 46514c2 | 2020-06-11 11:59:07 -0700 | [diff] [blame] | 1277 | help |
| 1278 | This variable allows SoC/mainboard to supply in a custom linker file |
| 1279 | if required. This determines the linker file used for all the stages |
| 1280 | (bootblock, romstage, verstage, ramstage, postcar) in |
| 1281 | src/arch/${ARCH}/Makefile.inc. |
| 1282 | |
Martin Roth | 75e5cb7 | 2016-12-15 15:05:37 -0700 | [diff] [blame] | 1283 | ############################################################################### |
| 1284 | # Set default values for symbols created before mainboards. This allows the |
| 1285 | # option to be displayed in the general menu, but the default to be loaded in |
| 1286 | # the mainboard if desired. |
| 1287 | config COMPRESS_RAMSTAGE |
| 1288 | default y if !UNCOMPRESSED_RAMSTAGE |
| 1289 | |
| 1290 | config COMPRESS_PRERAM_STAGES |
| 1291 | depends on !ARCH_X86 |
| 1292 | default y |
| 1293 | |
| 1294 | config INCLUDE_CONFIG_FILE |
| 1295 | default y |
| 1296 | |
Martin Roth | 75e5cb7 | 2016-12-15 15:05:37 -0700 | [diff] [blame] | 1297 | config BOOTSPLASH_FILE |
| 1298 | depends on BOOTSPLASH_IMAGE |
| 1299 | default "bootsplash.jpg" |
| 1300 | |
| 1301 | config CBFS_SIZE |
| 1302 | default ROM_SIZE |
Subrata Banik | b5962a9 | 2019-06-08 12:29:02 +0530 | [diff] [blame] | 1303 | |
| 1304 | config HAVE_BOOTBLOCK |
| 1305 | bool |
| 1306 | default y |
| 1307 | |
| 1308 | config HAVE_VERSTAGE |
| 1309 | bool |
| 1310 | depends on VBOOT_SEPARATE_VERSTAGE |
| 1311 | default y |
| 1312 | |
| 1313 | config HAVE_ROMSTAGE |
| 1314 | bool |
| 1315 | default y |
| 1316 | |
Subrata Banik | b5962a9 | 2019-06-08 12:29:02 +0530 | [diff] [blame] | 1317 | config HAVE_RAMSTAGE |
| 1318 | bool |
| 1319 | default n if RAMPAYLOAD |
| 1320 | default y |