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Subrata Banikb3ced6a2020-08-04 13:34:03 +05301config SOC_INTEL_ALDERLAKE
2 bool
3 help
Angel Ponsdb925aa2021-12-01 11:44:09 +01004 Intel Alderlake support. Mainboards should specify the PCH
5 type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead
6 of selecting this option directly.
Subrata Banikb3ced6a2020-08-04 13:34:03 +05307
Varshit Pandyab5df56f2021-01-18 09:44:35 +05308config SOC_INTEL_ALDERLAKE_PCH_M
9 bool
Angel Ponsdb925aa2021-12-01 11:44:09 +010010 select SOC_INTEL_ALDERLAKE
Varshit Pandyab5df56f2021-01-18 09:44:35 +053011 help
Angel Ponsdb925aa2021-12-01 11:44:09 +010012 Choose this option if your mainboard has a PCH-M chipset.
13
Usha P78c9b672021-11-30 11:27:38 +053014config SOC_INTEL_ALDERLAKE_PCH_N
15 bool
16 select SOC_INTEL_ALDERLAKE
17 help
18 Choose this option if your mainboard has a PCH-N chipset.
19
Angel Ponsdb925aa2021-12-01 11:44:09 +010020config SOC_INTEL_ALDERLAKE_PCH_P
21 bool
22 select SOC_INTEL_ALDERLAKE
23 help
24 Choose this option if your mainboard has a PCH-P chipset.
Varshit Pandyab5df56f2021-01-18 09:44:35 +053025
Subrata Banikb3ced6a2020-08-04 13:34:03 +053026if SOC_INTEL_ALDERLAKE
27
28config CPU_SPECIFIC_OPTIONS
29 def_bool y
Angel Ponsa25eaff2020-09-23 15:37:15 +020030 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Sugnan Prabhu Sdcf04592021-12-03 19:07:04 +053031 select ACPI_ADL_IPU_ES_SUPPORT
Angel Pons8e035e32021-06-22 12:58:20 +020032 select ARCH_X86
Subrata Banikb3ced6a2020-08-04 13:34:03 +053033 select BOOT_DEVICE_SUPPORTS_WRITES
Subrata Banik292afef2020-09-09 13:34:18 +053034 select CACHE_MRC_SETTINGS
35 select CPU_INTEL_COMMON
Subrata Banik2871e0e2020-09-27 11:30:58 +053036 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
Michael Niewöhner5307f122021-09-19 00:32:37 +020037 select CPU_SUPPORTS_INTEL_TME
Michael Niewöhnerfe6070f2020-10-04 15:16:04 +020038 select CPU_SUPPORTS_PM_TIMER_EMULATION
Eric Lai4ea47c32020-12-21 16:57:49 +080039 select DRIVERS_USB_ACPI
Subrata Banik2871e0e2020-09-27 11:30:58 +053040 select FSP_COMPRESS_FSP_S_LZ4
Subrata Banik683c95e2020-12-19 19:36:45 +053041 select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
Subrata Banik292afef2020-09-09 13:34:18 +053042 select FSP_M_XIP
Subrata Banik4ed9f9a2020-10-31 22:01:55 +053043 select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
Subrata Banik298b3592021-09-14 12:38:08 +053044 select FSPS_HAS_ARCH_UPD
Subrata Banik2871e0e2020-09-27 11:30:58 +053045 select GENERIC_GPIO_LIB
Subrata Banikb4a169a2021-12-29 18:36:23 +000046 select HAVE_DEBUG_RAM_SETUP
Subrata Banik2871e0e2020-09-27 11:30:58 +053047 select HAVE_FSP_GOP
Subrata Banikb3ced6a2020-08-04 13:34:03 +053048 select INTEL_DESCRIPTOR_MODE_CAPABLE
Subrata Banik2871e0e2020-09-27 11:30:58 +053049 select HAVE_SMI_HANDLER
Subrata Banikb3ced6a2020-08-04 13:34:03 +053050 select IDT_IN_EVERY_STAGE
Subrata Banik2871e0e2020-09-27 11:30:58 +053051 select INTEL_GMA_ACPI
52 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
Meera Ravindranath81d367f2021-07-08 09:39:11 +053053 select INTEL_GMA_OPREGION_2_1
Subrata Banik0aed4e52020-10-12 17:27:31 +053054 select INTEL_TME
Aamir Bohra30cca6c2021-02-04 20:57:51 +053055 select MP_SERVICES_PPI_V2
Subrata Banik292afef2020-09-09 13:34:18 +053056 select MRC_SETTINGS_PROTECT
Subrata Banik2871e0e2020-09-27 11:30:58 +053057 select PARALLEL_MP_AP_WORK
Subrata Banikb3ced6a2020-08-04 13:34:03 +053058 select MICROCODE_BLOB_UNDISCLOSED
Subrata Banikee735942020-09-07 17:52:23 +053059 select PLATFORM_USES_FSP2_2
Subrata Banik2871e0e2020-09-27 11:30:58 +053060 select PMC_GLOBAL_RESET_ENABLE_LOCK
Subrata Banikb3ced6a2020-08-04 13:34:03 +053061 select SOC_INTEL_COMMON
Subrata Banik08089922020-10-03 13:02:06 +053062 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
Subrata Banikb3ced6a2020-08-04 13:34:03 +053063 select SOC_INTEL_COMMON_BLOCK
Subrata Banik08089922020-10-03 13:02:06 +053064 select SOC_INTEL_COMMON_BLOCK_ACPI
ravindr174596572021-03-29 19:41:25 +053065 select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
Sridahr Siricilla73b90c62021-11-11 01:10:16 +053066 select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID
Angel Pons98f672a2021-02-19 19:42:10 +010067 select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
Tim Wawrzynczak5faee2e2021-07-01 08:24:18 -060068 select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
69 select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ
Subrata Banik21974ab2020-10-31 21:40:43 +053070 select SOC_INTEL_COMMON_BLOCK_CAR
Subrata Banik292afef2020-09-09 13:34:18 +053071 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
Subrata Banikb3ced6a2020-08-04 13:34:03 +053072 select SOC_INTEL_COMMON_BLOCK_CPU
Subrata Banik2871e0e2020-09-27 11:30:58 +053073 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
Angel Ponsa4cd9112021-02-19 19:23:38 +010074 select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
Subrata Banik2871e0e2020-09-27 11:30:58 +053075 select SOC_INTEL_COMMON_BLOCK_DTT
76 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
Subrata Banikaf2f8b92022-01-10 10:26:52 +000077 select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI
Subrata Banikb3ced6a2020-08-04 13:34:03 +053078 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
Krishna Prasad Bhat01e426d2022-01-16 22:37:21 +053079 select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N
Subrata Banik2871e0e2020-09-27 11:30:58 +053080 select SOC_INTEL_COMMON_BLOCK_HDA
Subrata Banik5a49f3a2022-01-28 23:49:31 +053081 select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT
Tim Wawrzynczak0c057c22021-03-04 10:56:28 -070082 select SOC_INTEL_COMMON_BLOCK_IPU
Tim Wawrzynczak43607e42021-05-18 09:04:42 -060083 select SOC_INTEL_COMMON_BLOCK_IRQ
Furquan Shaikha1c247b2020-12-31 22:50:14 -080084 select SOC_INTEL_COMMON_BLOCK_MEMINIT
Rizwan Qureshi307be992021-04-08 20:35:29 +053085 select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
Lean Sheng Tan75020002021-06-30 01:47:48 -070086 select SOC_INTEL_COMMON_BLOCK_PMC_EPOC
Sumeet R Pawnikar77298c62021-03-10 21:09:37 +053087 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
Subrata Banikb3ced6a2020-08-04 13:34:03 +053088 select SOC_INTEL_COMMON_BLOCK_SA
Subrata Banik2871e0e2020-09-27 11:30:58 +053089 select SOC_INTEL_COMMON_BLOCK_SMM
90 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
Subrata Banik8407c342021-09-08 20:15:36 +053091 select SOC_INTEL_COMMON_BLOCK_TCSS
John Zhao3c463712022-01-10 15:49:37 -080092 select SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR
Subrata Banikb2e8bd82021-11-17 15:35:05 +053093 select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC
Eric Lai4ea47c32020-12-21 16:57:49 +080094 select SOC_INTEL_COMMON_BLOCK_USB4
95 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
96 select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
Tim Wawrzynczak242da792020-11-10 10:13:54 -070097 select SOC_INTEL_COMMON_BLOCK_XHCI
98 select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
Subrata Banik4ed9f9a2020-10-31 22:01:55 +053099 select SOC_INTEL_COMMON_FSP_RESET
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530100 select SOC_INTEL_COMMON_PCH_BASE
101 select SOC_INTEL_COMMON_RESET
Tim Wawrzynczakc0e82e72021-06-17 12:42:35 -0600102 select SOC_INTEL_CSE_SET_EOP
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530103 select SSE2
104 select SUPPORT_CPU_UCODE_IN_CBFS
105 select TSC_MONOTONIC_TIMER
106 select UDELAY_TSC
Subrata Banikee735942020-09-07 17:52:23 +0530107 select UDK_202005_BINDING
Subrata Banik2871e0e2020-09-27 11:30:58 +0530108 select DISPLAY_FSP_VERSION_INFO
Subrata Banik2871e0e2020-09-27 11:30:58 +0530109
Angel Pons5e7f90b2022-01-08 13:16:38 +0100110config ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR
111 bool
112 help
113 Alder Lake stepping A0 needs a different value for a PMC setting in
114 the IFD. When this option is selected, coreboot will update the IFD
115 value at runtime, which allows using an IFD with the new value with
116 any CPU stepping. To apply this workaround, the IFD region needs to
117 be writable by the host.
118
Subrata Banik095e2a72021-07-05 20:56:15 +0530119config ALDERLAKE_CAR_ENHANCED_NEM
120 bool
121 default y if !INTEL_CAR_NEM
122 select INTEL_CAR_NEM_ENHANCED
123 select CAR_HAS_SF_MASKS
124 select COS_MAPPED_TO_MSB
125 select CAR_HAS_L3_PROTECTED_WAYS
126
Subrata Banik2871e0e2020-09-27 11:30:58 +0530127config MAX_CPUS
128 int
129 default 24
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530130
131config DCACHE_RAM_BASE
132 default 0xfef00000
133
134config DCACHE_RAM_SIZE
Subrata Banik191bd822020-11-21 19:30:57 +0530135 default 0xc0000
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530136 help
137 The size of the cache-as-ram region required during bootblock
138 and/or romstage.
139
140config DCACHE_BSP_STACK_SIZE
141 hex
Subrata Banik191bd822020-11-21 19:30:57 +0530142 default 0x80400
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530143 help
144 The amount of anticipated stack usage in CAR by bootblock and
145 other stages. In the case of FSP_USES_CB_STACK default value will be
Subrata Banik191bd822020-11-21 19:30:57 +0530146 sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530147 (~1KiB).
148
149config FSP_TEMP_RAM_SIZE
150 hex
151 default 0x20000
152 help
153 The amount of anticipated heap usage in CAR by FSP.
154 Refer to Platform FSP integration guide document to know
155 the exact FSP requirement for Heap setup.
156
Tim Wawrzynczak092813a2020-11-24 13:48:56 -0700157config CHIPSET_DEVICETREE
158 string
159 default "soc/intel/alderlake/chipset.cb"
160
Subrata Banik683c95e2020-12-19 19:36:45 +0530161config EXT_BIOS_WIN_BASE
162 default 0xf8000000
163
164config EXT_BIOS_WIN_SIZE
165 default 0x2000000
166
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530167config IFD_CHIPSET
168 string
169 default "adl"
170
171config IED_REGION_SIZE
172 hex
173 default 0x400000
174
175config HEAP_SIZE
176 hex
177 default 0x10000
178
Tim Wawrzynczak8d11cdc2021-03-12 12:46:02 -0700179# Intel recommends reserving the following resources per PCIe TBT root port,
180# from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5
181# - 42 buses
182# - 194 MiB Non-prefetchable memory
183# - 448 MiB Prefetchable memory
Furquan Shaikhd9f5d902021-08-24 13:53:43 -0700184if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
Tim Wawrzynczak8d11cdc2021-03-12 12:46:02 -0700185
186config PCIEXP_HOTPLUG_BUSES
187 int
188 default 42
189
190config PCIEXP_HOTPLUG_MEM
191 hex
192 default 0xc200000
193
194config PCIEXP_HOTPLUG_PREFETCH_MEM
195 hex
196 default 0x1c000000
197
Furquan Shaikhd9f5d902021-08-24 13:53:43 -0700198endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
Tim Wawrzynczak8d11cdc2021-03-12 12:46:02 -0700199
Subrata Banik85144d92021-01-09 16:17:45 +0530200config MAX_PCH_ROOT_PORTS
Subrata Banik2871e0e2020-09-27 11:30:58 +0530201 int
Varshit Pandyab5df56f2021-01-18 09:44:35 +0530202 default 10 if SOC_INTEL_ALDERLAKE_PCH_M
Usha P78c9b672021-11-30 11:27:38 +0530203 default 12 if SOC_INTEL_ALDERLAKE_PCH_N
Angel Ponsdb925aa2021-12-01 11:44:09 +0100204 default 12 if SOC_INTEL_ALDERLAKE_PCH_P
Subrata Banik2871e0e2020-09-27 11:30:58 +0530205
Subrata Banik85144d92021-01-09 16:17:45 +0530206config MAX_CPU_ROOT_PORTS
207 int
Varshit Pandyab5df56f2021-01-18 09:44:35 +0530208 default 1 if SOC_INTEL_ALDERLAKE_PCH_M
Usha P78c9b672021-11-30 11:27:38 +0530209 default 0 if SOC_INTEL_ALDERLAKE_PCH_N
Angel Ponsdb925aa2021-12-01 11:44:09 +0100210 default 3 if SOC_INTEL_ALDERLAKE_PCH_P
Subrata Banik85144d92021-01-09 16:17:45 +0530211
MAULIK V VAGHELA3e4f28f2022-01-21 14:17:53 +0530212config MAX_TBT_ROOT_PORTS
213 int
214 default 0 if SOC_INTEL_ALDERLAKE_PCH_N
215 default 2 if SOC_INTEL_ALDERLAKE_PCH_M
216 default 4 if SOC_INTEL_ALDERLAKE_PCH_P
217
Subrata Banik85144d92021-01-09 16:17:45 +0530218config MAX_ROOT_PORTS
219 int
220 default MAX_PCH_ROOT_PORTS
221
Subrata Banikcffc9382021-01-29 18:41:35 +0530222config MAX_PCIE_CLOCK_SRC
Subrata Banik2871e0e2020-09-27 11:30:58 +0530223 int
Subrata Banikcffc9382021-01-29 18:41:35 +0530224 default 6 if SOC_INTEL_ALDERLAKE_PCH_M
Usha P78c9b672021-11-30 11:27:38 +0530225 default 5 if SOC_INTEL_ALDERLAKE_PCH_N
Angel Ponsdb925aa2021-12-01 11:44:09 +0100226 default 7 if SOC_INTEL_ALDERLAKE_PCH_P
Subrata Banikcffc9382021-01-29 18:41:35 +0530227
228config MAX_PCIE_CLOCK_REQ
229 int
Angel Ponsdb925aa2021-12-01 11:44:09 +0100230 default 6 if SOC_INTEL_ALDERLAKE_PCH_M
Usha P78c9b672021-11-30 11:27:38 +0530231 default 5 if SOC_INTEL_ALDERLAKE_PCH_N
Angel Ponsdb925aa2021-12-01 11:44:09 +0100232 default 10 if SOC_INTEL_ALDERLAKE_PCH_P
Subrata Banik2871e0e2020-09-27 11:30:58 +0530233
234config SMM_TSEG_SIZE
235 hex
236 default 0x800000
237
238config SMM_RESERVED_SIZE
239 hex
240 default 0x200000
241
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530242config PCR_BASE_ADDRESS
243 hex
244 default 0xfd000000
245 help
246 This option allows you to select MMIO Base Address of sideband bus.
247
Shelley Chen4e9bb332021-10-20 15:43:45 -0700248config ECAM_MMCONF_BASE_ADDRESS
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530249 default 0xc0000000
250
251config CPU_BCLK_MHZ
252 int
253 default 100
254
255config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
256 int
257 default 120
258
Michael Niewöhnerdadcbfb2020-10-04 14:48:05 +0200259config CPU_XTAL_HZ
260 default 38400000
261
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530262config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
263 int
264 default 133
265
266config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
267 int
268 default 7
269
270config SOC_INTEL_I2C_DEV_MAX
271 int
Varshit B Pandya339f0e72021-07-14 11:08:23 +0530272 default 8
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530273
274config SOC_INTEL_UART_DEV_MAX
275 int
276 default 7
277
278config CONSOLE_UART_BASE_ADDRESS
279 hex
Bora Guvendik2a704192020-11-16 11:23:48 -0800280 default 0xfe03e000
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530281 depends on INTEL_LPSS_UART_FOR_CONSOLE
282
Maulik V Vaghela996bab42021-02-05 12:03:19 +0530283config VBT_DATA_SIZE_KB
284 int
285 default 9
286
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530287# Clock divider parameters for 115200 baud rate
288# Baudrate = (UART source clcok * M) /(N *16)
289# ADL UART source clock: 120MHz
290config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
291 hex
292 default 0x25a
293
294config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
295 hex
296 default 0x7fff
297
Subrata Banik292afef2020-09-09 13:34:18 +0530298config VBOOT
299 select VBOOT_SEPARATE_VERSTAGE
300 select VBOOT_MUST_REQUEST_DISPLAY
301 select VBOOT_STARTS_IN_BOOTBLOCK
302 select VBOOT_VBNV_CMOS
303 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
Subrata Banik34237862021-06-17 23:36:02 +0530304 select VBOOT_X86_SHA256_ACCELERATION
Subrata Banik292afef2020-09-09 13:34:18 +0530305
MAULIK V VAGHELA84532da2021-08-25 16:41:23 +0530306# Default hash block size is 1KiB. Increasing it to 4KiB to improve
307# hashing time as well as read time. This helps in improving
308# boot time for Alder Lake.
309config VBOOT_HASH_BLOCK_SIZE
310 hex
311 default 0x1000
312
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530313config CBFS_SIZE
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530314 default 0x200000
315
316config PRERAM_CBMEM_CONSOLE_SIZE
317 hex
Subrata Banikbf750552021-07-10 20:30:57 +0530318 default 0x2000
Subrata Banik2871e0e2020-09-27 11:30:58 +0530319
Subrata Banikee735942020-09-07 17:52:23 +0530320config FSP_HEADER_PATH
321 string "Location of FSP headers"
Ronak Kanabarecdc7142022-02-02 16:12:00 +0530322 default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N
Subrata Banikee735942020-09-07 17:52:23 +0530323 default "src/vendorcode/intel/fsp/fsp2_0/alderlake/"
324
325config FSP_FD_PATH
326 string
327 depends on FSP_USE_REPO
328 default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd"
Subrata Banik292afef2020-09-09 13:34:18 +0530329
330config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT
331 int "Debug Consent for ADL"
Subrata Banik0cd553b2021-12-29 08:09:37 +0000332 # USB DBC is more common for developers so make this default to 2 if
Subrata Banik292afef2020-09-09 13:34:18 +0530333 # SOC_INTEL_DEBUG_CONSENT=y
Kane Chen0e9a6162021-11-23 14:42:48 +0800334 default 2 if SOC_INTEL_DEBUG_CONSENT
Subrata Banik292afef2020-09-09 13:34:18 +0530335 default 0
336 help
337 This is to control debug interface on SOC.
338 Setting non-zero value will allow to use DBC or DCI to debug SOC.
339 PlatformDebugConsent in FspmUpd.h has the details.
340
341 Desired platform debug type are
Kane Chen0e9a6162021-11-23 14:42:48 +0800342 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power),
343 7:Manual
Furquan Shaikha1c247b2020-12-31 22:50:14 -0800344
345config DATA_BUS_WIDTH
346 int
347 default 128
348
349config DIMMS_PER_CHANNEL
350 int
351 default 2
352
353config MRC_CHANNEL_WIDTH
354 int
355 default 16
356
Sugnan Prabhu Sdcf04592021-12-03 19:07:04 +0530357config ACPI_ADL_IPU_ES_SUPPORT
358 def_bool n
359 help
360 Enables ACPI entry to provide silicon type information to IPU kernel driver.
361
Furquan Shaikhf888c682021-10-05 21:37:33 -0700362if STITCH_ME_BIN
363
364config CSE_BPDT_VERSION
365 default "1.7"
366
367endif
368
Subrata Banikb3ced6a2020-08-04 13:34:03 +0530369endif