Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 1 | config SOC_INTEL_ALDERLAKE |
| 2 | bool |
| 3 | help |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 4 | Intel Alderlake support. Mainboards should specify the PCH |
| 5 | type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead |
| 6 | of selecting this option directly. |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 7 | |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 8 | config SOC_INTEL_ALDERLAKE_PCH_M |
| 9 | bool |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 10 | select SOC_INTEL_ALDERLAKE |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 11 | help |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 12 | Choose this option if your mainboard has a PCH-M chipset. |
| 13 | |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 14 | config SOC_INTEL_ALDERLAKE_PCH_N |
| 15 | bool |
| 16 | select SOC_INTEL_ALDERLAKE |
| 17 | help |
| 18 | Choose this option if your mainboard has a PCH-N chipset. |
| 19 | |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 20 | config SOC_INTEL_ALDERLAKE_PCH_P |
| 21 | bool |
| 22 | select SOC_INTEL_ALDERLAKE |
| 23 | help |
| 24 | Choose this option if your mainboard has a PCH-P chipset. |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 25 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 26 | if SOC_INTEL_ALDERLAKE |
| 27 | |
| 28 | config CPU_SPECIFIC_OPTIONS |
| 29 | def_bool y |
Angel Pons | a25eaff | 2020-09-23 15:37:15 +0200 | [diff] [blame] | 30 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Sugnan Prabhu S | dcf0459 | 2021-12-03 19:07:04 +0530 | [diff] [blame] | 31 | select ACPI_ADL_IPU_ES_SUPPORT |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 32 | select ARCH_X86 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 33 | select BOOT_DEVICE_SUPPORTS_WRITES |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 34 | select CACHE_MRC_SETTINGS |
| 35 | select CPU_INTEL_COMMON |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 36 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | 5307f12 | 2021-09-19 00:32:37 +0200 | [diff] [blame] | 37 | select CPU_SUPPORTS_INTEL_TME |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 38 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Eric Lai | 4ea47c3 | 2020-12-21 16:57:49 +0800 | [diff] [blame] | 39 | select DRIVERS_USB_ACPI |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 40 | select FSP_COMPRESS_FSP_S_LZ4 |
Subrata Banik | 683c95e | 2020-12-19 19:36:45 +0530 | [diff] [blame] | 41 | select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 42 | select FSP_M_XIP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 43 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Subrata Banik | 298b359 | 2021-09-14 12:38:08 +0530 | [diff] [blame] | 44 | select FSPS_HAS_ARCH_UPD |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 45 | select GENERIC_GPIO_LIB |
Subrata Banik | b4a169a | 2021-12-29 18:36:23 +0000 | [diff] [blame] | 46 | select HAVE_DEBUG_RAM_SETUP |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 47 | select HAVE_FSP_GOP |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 48 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 49 | select HAVE_SMI_HANDLER |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 50 | select IDT_IN_EVERY_STAGE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 51 | select INTEL_GMA_ACPI |
| 52 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Meera Ravindranath | 81d367f | 2021-07-08 09:39:11 +0530 | [diff] [blame] | 53 | select INTEL_GMA_OPREGION_2_1 |
Subrata Banik | 0aed4e5 | 2020-10-12 17:27:31 +0530 | [diff] [blame] | 54 | select INTEL_TME |
Aamir Bohra | 30cca6c | 2021-02-04 20:57:51 +0530 | [diff] [blame] | 55 | select MP_SERVICES_PPI_V2 |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 56 | select MRC_SETTINGS_PROTECT |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 57 | select PARALLEL_MP_AP_WORK |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 58 | select MICROCODE_BLOB_UNDISCLOSED |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 59 | select PLATFORM_USES_FSP2_2 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 60 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 61 | select SOC_INTEL_COMMON |
Subrata Banik | 0808992 | 2020-10-03 13:02:06 +0530 | [diff] [blame] | 62 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_BLOCK |
Subrata Banik | 0808992 | 2020-10-03 13:02:06 +0530 | [diff] [blame] | 64 | select SOC_INTEL_COMMON_BLOCK_ACPI |
ravindr1 | 7459657 | 2021-03-29 19:41:25 +0530 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC |
Sridahr Siricilla | 73b90c6 | 2021-11-11 01:10:16 +0530 | [diff] [blame] | 66 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID |
Angel Pons | 98f672a | 2021-02-19 19:42:10 +0100 | [diff] [blame] | 67 | select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
Tim Wawrzynczak | 5faee2e | 2021-07-01 08:24:18 -0600 | [diff] [blame] | 68 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP |
| 69 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ |
Subrata Banik | 21974ab | 2020-10-31 21:40:43 +0530 | [diff] [blame] | 70 | select SOC_INTEL_COMMON_BLOCK_CAR |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 71 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 72 | select SOC_INTEL_COMMON_BLOCK_CPU |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 73 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Angel Pons | a4cd911 | 2021-02-19 19:23:38 +0100 | [diff] [blame] | 74 | select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 75 | select SOC_INTEL_COMMON_BLOCK_DTT |
| 76 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Subrata Banik | af2f8b9 | 2022-01-10 10:26:52 +0000 | [diff] [blame] | 77 | select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 78 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 79 | select SOC_INTEL_COMMON_BLOCK_HDA |
Tim Wawrzynczak | 0c057c2 | 2021-03-04 10:56:28 -0700 | [diff] [blame] | 80 | select SOC_INTEL_COMMON_BLOCK_IPU |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 81 | select SOC_INTEL_COMMON_BLOCK_IRQ |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 82 | select SOC_INTEL_COMMON_BLOCK_MEMINIT |
Rizwan Qureshi | 307be99 | 2021-04-08 20:35:29 +0530 | [diff] [blame] | 83 | select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 |
Lean Sheng Tan | 7502000 | 2021-06-30 01:47:48 -0700 | [diff] [blame] | 84 | select SOC_INTEL_COMMON_BLOCK_PMC_EPOC |
Sumeet R Pawnikar | 77298c6 | 2021-03-10 21:09:37 +0530 | [diff] [blame] | 85 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 86 | select SOC_INTEL_COMMON_BLOCK_SA |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 87 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 88 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | 8407c34 | 2021-09-08 20:15:36 +0530 | [diff] [blame] | 89 | select SOC_INTEL_COMMON_BLOCK_TCSS |
John Zhao | 3c46371 | 2022-01-10 15:49:37 -0800 | [diff] [blame^] | 90 | select SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR |
Subrata Banik | b2e8bd8 | 2021-11-17 15:35:05 +0530 | [diff] [blame] | 91 | select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC |
Eric Lai | 4ea47c3 | 2020-12-21 16:57:49 +0800 | [diff] [blame] | 92 | select SOC_INTEL_COMMON_BLOCK_USB4 |
| 93 | select SOC_INTEL_COMMON_BLOCK_USB4_PCIE |
| 94 | select SOC_INTEL_COMMON_BLOCK_USB4_XHCI |
Tim Wawrzynczak | 242da79 | 2020-11-10 10:13:54 -0700 | [diff] [blame] | 95 | select SOC_INTEL_COMMON_BLOCK_XHCI |
| 96 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 97 | select SOC_INTEL_COMMON_FSP_RESET |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 98 | select SOC_INTEL_COMMON_PCH_BASE |
| 99 | select SOC_INTEL_COMMON_RESET |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 100 | select SOC_INTEL_CSE_SET_EOP |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 101 | select SSE2 |
| 102 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 103 | select TSC_MONOTONIC_TIMER |
| 104 | select UDELAY_TSC |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 105 | select UDK_202005_BINDING |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 106 | select DISPLAY_FSP_VERSION_INFO |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 107 | |
Angel Pons | 5e7f90b | 2022-01-08 13:16:38 +0100 | [diff] [blame] | 108 | config ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR |
| 109 | bool |
| 110 | help |
| 111 | Alder Lake stepping A0 needs a different value for a PMC setting in |
| 112 | the IFD. When this option is selected, coreboot will update the IFD |
| 113 | value at runtime, which allows using an IFD with the new value with |
| 114 | any CPU stepping. To apply this workaround, the IFD region needs to |
| 115 | be writable by the host. |
| 116 | |
Subrata Banik | 095e2a7 | 2021-07-05 20:56:15 +0530 | [diff] [blame] | 117 | config ALDERLAKE_CAR_ENHANCED_NEM |
| 118 | bool |
| 119 | default y if !INTEL_CAR_NEM |
| 120 | select INTEL_CAR_NEM_ENHANCED |
| 121 | select CAR_HAS_SF_MASKS |
| 122 | select COS_MAPPED_TO_MSB |
| 123 | select CAR_HAS_L3_PROTECTED_WAYS |
| 124 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 125 | config MAX_CPUS |
| 126 | int |
| 127 | default 24 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 128 | |
| 129 | config DCACHE_RAM_BASE |
| 130 | default 0xfef00000 |
| 131 | |
| 132 | config DCACHE_RAM_SIZE |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 133 | default 0xc0000 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 134 | help |
| 135 | The size of the cache-as-ram region required during bootblock |
| 136 | and/or romstage. |
| 137 | |
| 138 | config DCACHE_BSP_STACK_SIZE |
| 139 | hex |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 140 | default 0x80400 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 141 | help |
| 142 | The amount of anticipated stack usage in CAR by bootblock and |
| 143 | other stages. In the case of FSP_USES_CB_STACK default value will be |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 144 | sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 145 | (~1KiB). |
| 146 | |
| 147 | config FSP_TEMP_RAM_SIZE |
| 148 | hex |
| 149 | default 0x20000 |
| 150 | help |
| 151 | The amount of anticipated heap usage in CAR by FSP. |
| 152 | Refer to Platform FSP integration guide document to know |
| 153 | the exact FSP requirement for Heap setup. |
| 154 | |
Tim Wawrzynczak | 092813a | 2020-11-24 13:48:56 -0700 | [diff] [blame] | 155 | config CHIPSET_DEVICETREE |
| 156 | string |
| 157 | default "soc/intel/alderlake/chipset.cb" |
| 158 | |
Subrata Banik | 683c95e | 2020-12-19 19:36:45 +0530 | [diff] [blame] | 159 | config EXT_BIOS_WIN_BASE |
| 160 | default 0xf8000000 |
| 161 | |
| 162 | config EXT_BIOS_WIN_SIZE |
| 163 | default 0x2000000 |
| 164 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 165 | config IFD_CHIPSET |
| 166 | string |
| 167 | default "adl" |
| 168 | |
| 169 | config IED_REGION_SIZE |
| 170 | hex |
| 171 | default 0x400000 |
| 172 | |
| 173 | config HEAP_SIZE |
| 174 | hex |
| 175 | default 0x10000 |
| 176 | |
Tim Wawrzynczak | 8d11cdc | 2021-03-12 12:46:02 -0700 | [diff] [blame] | 177 | # Intel recommends reserving the following resources per PCIe TBT root port, |
| 178 | # from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5 |
| 179 | # - 42 buses |
| 180 | # - 194 MiB Non-prefetchable memory |
| 181 | # - 448 MiB Prefetchable memory |
Furquan Shaikh | d9f5d90 | 2021-08-24 13:53:43 -0700 | [diff] [blame] | 182 | if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
Tim Wawrzynczak | 8d11cdc | 2021-03-12 12:46:02 -0700 | [diff] [blame] | 183 | |
| 184 | config PCIEXP_HOTPLUG_BUSES |
| 185 | int |
| 186 | default 42 |
| 187 | |
| 188 | config PCIEXP_HOTPLUG_MEM |
| 189 | hex |
| 190 | default 0xc200000 |
| 191 | |
| 192 | config PCIEXP_HOTPLUG_PREFETCH_MEM |
| 193 | hex |
| 194 | default 0x1c000000 |
| 195 | |
Furquan Shaikh | d9f5d90 | 2021-08-24 13:53:43 -0700 | [diff] [blame] | 196 | endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
Tim Wawrzynczak | 8d11cdc | 2021-03-12 12:46:02 -0700 | [diff] [blame] | 197 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 198 | config MAX_PCH_ROOT_PORTS |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 199 | int |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 200 | default 10 if SOC_INTEL_ALDERLAKE_PCH_M |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 201 | default 12 if SOC_INTEL_ALDERLAKE_PCH_N |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 202 | default 12 if SOC_INTEL_ALDERLAKE_PCH_P |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 203 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 204 | config MAX_CPU_ROOT_PORTS |
| 205 | int |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 206 | default 1 if SOC_INTEL_ALDERLAKE_PCH_M |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 207 | default 0 if SOC_INTEL_ALDERLAKE_PCH_N |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 208 | default 3 if SOC_INTEL_ALDERLAKE_PCH_P |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 209 | |
| 210 | config MAX_ROOT_PORTS |
| 211 | int |
| 212 | default MAX_PCH_ROOT_PORTS |
| 213 | |
Subrata Banik | cffc938 | 2021-01-29 18:41:35 +0530 | [diff] [blame] | 214 | config MAX_PCIE_CLOCK_SRC |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 215 | int |
Subrata Banik | cffc938 | 2021-01-29 18:41:35 +0530 | [diff] [blame] | 216 | default 6 if SOC_INTEL_ALDERLAKE_PCH_M |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 217 | default 5 if SOC_INTEL_ALDERLAKE_PCH_N |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 218 | default 7 if SOC_INTEL_ALDERLAKE_PCH_P |
Subrata Banik | cffc938 | 2021-01-29 18:41:35 +0530 | [diff] [blame] | 219 | |
| 220 | config MAX_PCIE_CLOCK_REQ |
| 221 | int |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 222 | default 6 if SOC_INTEL_ALDERLAKE_PCH_M |
Usha P | 78c9b67 | 2021-11-30 11:27:38 +0530 | [diff] [blame] | 223 | default 5 if SOC_INTEL_ALDERLAKE_PCH_N |
Angel Pons | db925aa | 2021-12-01 11:44:09 +0100 | [diff] [blame] | 224 | default 10 if SOC_INTEL_ALDERLAKE_PCH_P |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 225 | |
| 226 | config SMM_TSEG_SIZE |
| 227 | hex |
| 228 | default 0x800000 |
| 229 | |
| 230 | config SMM_RESERVED_SIZE |
| 231 | hex |
| 232 | default 0x200000 |
| 233 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 234 | config PCR_BASE_ADDRESS |
| 235 | hex |
| 236 | default 0xfd000000 |
| 237 | help |
| 238 | This option allows you to select MMIO Base Address of sideband bus. |
| 239 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 240 | config ECAM_MMCONF_BASE_ADDRESS |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 241 | default 0xc0000000 |
| 242 | |
| 243 | config CPU_BCLK_MHZ |
| 244 | int |
| 245 | default 100 |
| 246 | |
| 247 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 248 | int |
| 249 | default 120 |
| 250 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 251 | config CPU_XTAL_HZ |
| 252 | default 38400000 |
| 253 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 254 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 255 | int |
| 256 | default 133 |
| 257 | |
| 258 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 259 | int |
| 260 | default 7 |
| 261 | |
| 262 | config SOC_INTEL_I2C_DEV_MAX |
| 263 | int |
Varshit B Pandya | 339f0e7 | 2021-07-14 11:08:23 +0530 | [diff] [blame] | 264 | default 8 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 265 | |
| 266 | config SOC_INTEL_UART_DEV_MAX |
| 267 | int |
| 268 | default 7 |
| 269 | |
| 270 | config CONSOLE_UART_BASE_ADDRESS |
| 271 | hex |
Bora Guvendik | 2a70419 | 2020-11-16 11:23:48 -0800 | [diff] [blame] | 272 | default 0xfe03e000 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 273 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 274 | |
Maulik V Vaghela | 996bab4 | 2021-02-05 12:03:19 +0530 | [diff] [blame] | 275 | config VBT_DATA_SIZE_KB |
| 276 | int |
| 277 | default 9 |
| 278 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 279 | # Clock divider parameters for 115200 baud rate |
| 280 | # Baudrate = (UART source clcok * M) /(N *16) |
| 281 | # ADL UART source clock: 120MHz |
| 282 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 283 | hex |
| 284 | default 0x25a |
| 285 | |
| 286 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 287 | hex |
| 288 | default 0x7fff |
| 289 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 290 | config VBOOT |
| 291 | select VBOOT_SEPARATE_VERSTAGE |
| 292 | select VBOOT_MUST_REQUEST_DISPLAY |
| 293 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 294 | select VBOOT_VBNV_CMOS |
| 295 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Subrata Banik | 3423786 | 2021-06-17 23:36:02 +0530 | [diff] [blame] | 296 | select VBOOT_X86_SHA256_ACCELERATION |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 297 | |
MAULIK V VAGHELA | 84532da | 2021-08-25 16:41:23 +0530 | [diff] [blame] | 298 | # Default hash block size is 1KiB. Increasing it to 4KiB to improve |
| 299 | # hashing time as well as read time. This helps in improving |
| 300 | # boot time for Alder Lake. |
| 301 | config VBOOT_HASH_BLOCK_SIZE |
| 302 | hex |
| 303 | default 0x1000 |
| 304 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 305 | config CBFS_SIZE |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 306 | default 0x200000 |
| 307 | |
| 308 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 309 | hex |
Subrata Banik | bf75055 | 2021-07-10 20:30:57 +0530 | [diff] [blame] | 310 | default 0x2000 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 311 | |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 312 | config FSP_HEADER_PATH |
| 313 | string "Location of FSP headers" |
| 314 | default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" |
| 315 | |
| 316 | config FSP_FD_PATH |
| 317 | string |
| 318 | depends on FSP_USE_REPO |
| 319 | default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd" |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 320 | |
| 321 | config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT |
| 322 | int "Debug Consent for ADL" |
Subrata Banik | 0cd553b | 2021-12-29 08:09:37 +0000 | [diff] [blame] | 323 | # USB DBC is more common for developers so make this default to 2 if |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 324 | # SOC_INTEL_DEBUG_CONSENT=y |
Kane Chen | 0e9a616 | 2021-11-23 14:42:48 +0800 | [diff] [blame] | 325 | default 2 if SOC_INTEL_DEBUG_CONSENT |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 326 | default 0 |
| 327 | help |
| 328 | This is to control debug interface on SOC. |
| 329 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 330 | PlatformDebugConsent in FspmUpd.h has the details. |
| 331 | |
| 332 | Desired platform debug type are |
Kane Chen | 0e9a616 | 2021-11-23 14:42:48 +0800 | [diff] [blame] | 333 | 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), |
| 334 | 7:Manual |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 335 | |
| 336 | config DATA_BUS_WIDTH |
| 337 | int |
| 338 | default 128 |
| 339 | |
| 340 | config DIMMS_PER_CHANNEL |
| 341 | int |
| 342 | default 2 |
| 343 | |
| 344 | config MRC_CHANNEL_WIDTH |
| 345 | int |
| 346 | default 16 |
| 347 | |
Sugnan Prabhu S | dcf0459 | 2021-12-03 19:07:04 +0530 | [diff] [blame] | 348 | config ACPI_ADL_IPU_ES_SUPPORT |
| 349 | def_bool n |
| 350 | help |
| 351 | Enables ACPI entry to provide silicon type information to IPU kernel driver. |
| 352 | |
Furquan Shaikh | f888c68 | 2021-10-05 21:37:33 -0700 | [diff] [blame] | 353 | if STITCH_ME_BIN |
| 354 | |
| 355 | config CSE_BPDT_VERSION |
| 356 | default "1.7" |
| 357 | |
| 358 | endif |
| 359 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 360 | endif |