Felix Held | 4a8cd72 | 2020-04-18 22:26:39 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 2 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 3 | config SOC_AMD_PICASSO |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 4 | bool |
| 5 | help |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 6 | AMD Picasso support |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 7 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 8 | if SOC_AMD_PICASSO |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 9 | |
| 10 | config CPU_SPECIFIC_OPTIONS |
| 11 | def_bool y |
| 12 | select ARCH_BOOTBLOCK_X86_32 |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 13 | select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 14 | select ARCH_ROMSTAGE_X86_32 |
| 15 | select ARCH_RAMSTAGE_X86_32 |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 16 | select ARCH_X86 |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 17 | select RESET_VECTOR_IN_RAM |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 18 | select X86_AMD_FIXED_MTRRS |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 19 | select X86_AMD_INIT_SIPI |
Kyösti Mälkki | 3139c8d | 2020-06-28 16:33:33 +0300 | [diff] [blame] | 20 | select ACPI_SOC_NVS |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 21 | select DRIVERS_I2C_DESIGNWARE |
Raul E Rangel | 0357ab7 | 2020-07-09 12:08:58 -0600 | [diff] [blame] | 22 | select DRIVERS_USB_PCI_XHCI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 23 | select GENERIC_GPIO_LIB |
Furquan Shaikh | 8e91509 | 2020-06-17 23:15:35 -0700 | [diff] [blame] | 24 | select IDT_IN_EVERY_STAGE |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 25 | select IOAPIC |
Felix Held | e697fd9 | 2021-01-18 15:10:43 +0100 | [diff] [blame] | 26 | select HAVE_ACPI_TABLES |
Furquan Shaikh | 0eabe13 | 2020-04-28 21:57:07 -0700 | [diff] [blame] | 27 | select HAVE_EM100_SUPPORT |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 28 | select SOC_AMD_COMMON |
Karthikeyan Ramasubramanian | 4520aa2 | 2021-04-23 11:42:19 -0600 | [diff] [blame] | 29 | select SOC_AMD_COMMON_BLOCK_ACP |
Felix Held | 33c548b | 2021-01-27 20:34:24 +0100 | [diff] [blame] | 30 | select SOC_AMD_COMMON_BLOCK_ACPI |
| 31 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
Felix Held | 18b51e9 | 2021-05-08 01:30:30 +0200 | [diff] [blame] | 32 | select SOC_AMD_COMMON_BLOCK_ACPI_ALIB |
Eric Lai | 65b0afe | 2021-04-09 11:50:48 +0800 | [diff] [blame] | 33 | select SOC_AMD_COMMON_BLOCK_ACPI_GPIO |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 34 | select SOC_AMD_COMMON_BLOCK_ACPI_IVRS |
Felix Held | 33c548b | 2021-01-27 20:34:24 +0100 | [diff] [blame] | 35 | select SOC_AMD_COMMON_BLOCK_AOAC |
Felix Held | 21c46c0 | 2021-03-05 00:13:16 +0100 | [diff] [blame] | 36 | select SOC_AMD_COMMON_BLOCK_APOB |
Felix Held | 33c548b | 2021-01-27 20:34:24 +0100 | [diff] [blame] | 37 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
Felix Held | dba3fe7 | 2021-02-13 01:05:56 +0100 | [diff] [blame] | 38 | select SOC_AMD_COMMON_BLOCK_DATA_FABRIC |
Felix Held | 33c548b | 2021-01-27 20:34:24 +0100 | [diff] [blame] | 39 | select SOC_AMD_COMMON_BLOCK_GRAPHICS |
Furquan Shaikh | 702cf30 | 2020-05-09 18:30:51 -0700 | [diff] [blame] | 40 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 41 | select SOC_AMD_COMMON_BLOCK_HDA |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 42 | select SOC_AMD_COMMON_BLOCK_I2C |
Felix Held | 33c548b | 2021-01-27 20:34:24 +0100 | [diff] [blame] | 43 | select SOC_AMD_COMMON_BLOCK_IOMMU |
| 44 | select SOC_AMD_COMMON_BLOCK_LPC |
Felix Held | 1e1d490 | 2021-07-14 00:05:39 +0200 | [diff] [blame] | 45 | select SOC_AMD_COMMON_BLOCK_MCAX |
Felix Held | 33c548b | 2021-01-27 20:34:24 +0100 | [diff] [blame] | 46 | select SOC_AMD_COMMON_BLOCK_NONCAR |
| 47 | select SOC_AMD_COMMON_BLOCK_PCI |
Raul E Rangel | 4831411 | 2021-05-10 14:55:11 -0600 | [diff] [blame] | 48 | select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER |
Felix Held | 0d2c001 | 2021-04-12 23:44:14 +0200 | [diff] [blame] | 49 | select SOC_AMD_COMMON_BLOCK_PM |
| 50 | select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE |
Felix Held | 33c548b | 2021-01-27 20:34:24 +0100 | [diff] [blame] | 51 | select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 52 | select SOC_AMD_COMMON_BLOCK_SATA |
Aaron Durbin | 3d2e18a | 2020-01-28 11:20:05 -0700 | [diff] [blame] | 53 | select SOC_AMD_COMMON_BLOCK_SMBUS |
Felix Held | 161d809 | 2020-12-01 18:17:42 +0100 | [diff] [blame] | 54 | select SOC_AMD_COMMON_BLOCK_SMI |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 55 | select SOC_AMD_COMMON_BLOCK_SMM |
Felix Held | 60a4643 | 2020-11-12 00:14:16 +0100 | [diff] [blame] | 56 | select SOC_AMD_COMMON_BLOCK_SMU |
Felix Held | 33c548b | 2021-01-27 20:34:24 +0100 | [diff] [blame] | 57 | select SOC_AMD_COMMON_BLOCK_SPI |
Felix Held | 2f5c759 | 2020-12-04 17:31:10 +0100 | [diff] [blame] | 58 | select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H |
Felix Held | 6f8f9c9 | 2020-12-09 21:36:56 +0100 | [diff] [blame] | 59 | select SOC_AMD_COMMON_BLOCK_UART |
Raul E Rangel | 394c6b0 | 2021-02-12 14:37:43 -0700 | [diff] [blame] | 60 | select SOC_AMD_COMMON_BLOCK_UCODE |
Nikolai Vyssotski | a289cdd | 2021-04-28 18:09:29 -0500 | [diff] [blame] | 61 | select SOC_AMD_COMMON_FSP_DMI_TABLES |
Aaron Durbin | 1d0b99b | 2020-04-11 11:58:57 -0600 | [diff] [blame] | 62 | select PROVIDES_ROM_SHARING |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 63 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 64 | select PARALLEL_MP_AP_WORK |
| 65 | select HAVE_SMI_HANDLER |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 66 | select SSE2 |
| 67 | select RTC |
Marshall Dawson | 00a2208 | 2020-01-20 23:05:31 -0700 | [diff] [blame] | 68 | select PLATFORM_USES_FSP2_0 |
Furquan Shaikh | c3063c5 | 2020-05-28 11:58:20 -0700 | [diff] [blame] | 69 | select FSP_COMPRESS_FSP_M_LZMA |
| 70 | select FSP_COMPRESS_FSP_S_LZMA |
Marshall Dawson | 00a2208 | 2020-01-20 23:05:31 -0700 | [diff] [blame] | 71 | select UDK_2017_BINDING |
| 72 | select HAVE_CF9_RESET |
Raul E Rangel | 394c6b0 | 2021-02-12 14:37:43 -0700 | [diff] [blame] | 73 | |
Angel Pons | 6f5a658 | 2021-06-22 15:18:07 +0200 | [diff] [blame] | 74 | config ARCH_ALL_STAGES_X86 |
| 75 | default n |
| 76 | |
Raul E Rangel | 394c6b0 | 2021-02-12 14:37:43 -0700 | [diff] [blame] | 77 | config SOC_AMD_COMMON_BLOCK_UCODE_SIZE |
| 78 | default 3200 |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 79 | |
Felix Held | c4eb45f | 2021-02-13 02:36:02 +0100 | [diff] [blame] | 80 | config CHIPSET_DEVICETREE |
| 81 | string |
| 82 | default "soc/amd/picasso/chipset.cb" |
| 83 | |
Felix Held | 3cc3d81 | 2020-06-17 16:16:08 +0200 | [diff] [blame] | 84 | config FSP_M_FILE |
| 85 | string "FSP-M (memory init) binary path and filename" |
| 86 | depends on ADD_FSP_BINARIES |
| 87 | default "3rdparty/amd_blobs/picasso/PICASSO_M.fd" |
| 88 | help |
| 89 | The path and filename of the FSP-M binary for this platform. |
| 90 | |
| 91 | config FSP_S_FILE |
| 92 | string "FSP-S (silicon init) binary path and filename" |
| 93 | depends on ADD_FSP_BINARIES |
| 94 | default "3rdparty/amd_blobs/picasso/PICASSO_S.fd" |
| 95 | help |
| 96 | The path and filename of the FSP-S binary for this platform. |
| 97 | |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 98 | config EARLY_RESERVED_DRAM_BASE |
| 99 | hex |
| 100 | default 0x2000000 |
| 101 | help |
| 102 | This variable defines the base address of the DRAM which is reserved |
| 103 | for usage by coreboot in early stages (i.e. before ramstage is up). |
| 104 | This memory gets reserved in BIOS tables to ensure that the OS does |
| 105 | not use it, thus preventing corruption of OS memory in case of S3 |
| 106 | resume. |
| 107 | |
| 108 | config EARLYRAM_BSP_STACK_SIZE |
| 109 | hex |
| 110 | default 0x1000 |
| 111 | |
| 112 | config PSP_APOB_DRAM_ADDRESS |
| 113 | hex |
| 114 | default 0x2001000 |
| 115 | help |
| 116 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 117 | Block. |
| 118 | |
| 119 | config PSP_SHAREDMEM_BASE |
| 120 | hex |
| 121 | default 0x2011000 if VBOOT |
| 122 | default 0x0 |
| 123 | help |
| 124 | This variable defines the base address in DRAM memory where PSP copies |
Kangheui Won | 6b36c83 | 2021-04-21 14:48:14 +1000 | [diff] [blame] | 125 | the vboot workbuf. This is used in the linker script to have a static |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 126 | allocation for the buffer as well as for adding relevant entries in |
Kangheui Won | 6b36c83 | 2021-04-21 14:48:14 +1000 | [diff] [blame] | 127 | the BIOS directory table for the PSP. |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 128 | |
| 129 | config PSP_SHAREDMEM_SIZE |
| 130 | hex |
| 131 | default 0x8000 if VBOOT |
| 132 | default 0x0 |
| 133 | help |
| 134 | Sets the maximum size for the PSP to pass the vboot workbuf and |
| 135 | any logs or timestamps back to coreboot. This will be copied |
| 136 | into main memory by the PSP and will be available when the x86 is |
| 137 | started. The workbuf's base depends on the address of the reset |
| 138 | vector. |
| 139 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 140 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 141 | hex |
| 142 | default 0x1600 |
| 143 | help |
| 144 | Increase this value if preram cbmem console is getting truncated |
| 145 | |
Kangheui Won | 4020aa7 | 2021-05-20 09:56:39 +1000 | [diff] [blame] | 146 | config CBFS_MCACHE_SIZE |
| 147 | hex |
| 148 | default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 149 | |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 150 | config C_ENV_BOOTBLOCK_SIZE |
| 151 | hex |
| 152 | default 0x10000 |
| 153 | help |
| 154 | Sets the size of the bootblock stage that should be loaded in DRAM. |
| 155 | This variable controls the DRAM allocation size in linker script |
| 156 | for bootblock stage. |
| 157 | |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 158 | config ROMSTAGE_ADDR |
| 159 | hex |
| 160 | default 0x2040000 |
| 161 | help |
| 162 | Sets the address in DRAM where romstage should be loaded. |
| 163 | |
| 164 | config ROMSTAGE_SIZE |
| 165 | hex |
| 166 | default 0x80000 |
| 167 | help |
| 168 | Sets the size of DRAM allocation for romstage in linker script. |
| 169 | |
| 170 | config FSP_M_ADDR |
| 171 | hex |
| 172 | default 0x20C0000 |
| 173 | help |
| 174 | Sets the address in DRAM where FSP-M should be loaded. cbfstool |
| 175 | performs relocation of FSP-M to this address. |
| 176 | |
| 177 | config FSP_M_SIZE |
| 178 | hex |
| 179 | default 0x80000 |
| 180 | help |
| 181 | Sets the size of DRAM allocation for FSP-M in linker script. |
| 182 | |
| 183 | config VERSTAGE_ADDR |
| 184 | hex |
| 185 | depends on VBOOT_SEPARATE_VERSTAGE |
| 186 | default 0x2140000 |
| 187 | help |
| 188 | Sets the address in DRAM where verstage should be loaded if running |
| 189 | as a separate stage on x86. |
| 190 | |
| 191 | config VERSTAGE_SIZE |
| 192 | hex |
| 193 | depends on VBOOT_SEPARATE_VERSTAGE |
| 194 | default 0x80000 |
| 195 | help |
| 196 | Sets the size of DRAM allocation for verstage in linker script if |
| 197 | running as a separate stage on x86. |
| 198 | |
| 199 | config RAMBASE |
| 200 | hex |
| 201 | default 0x10000000 |
| 202 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 203 | config CPU_ADDR_BITS |
| 204 | int |
| 205 | default 48 |
| 206 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 207 | config MMCONF_BASE_ADDRESS |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 208 | default 0xF8000000 |
| 209 | |
| 210 | config MMCONF_BUS_NUMBER |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 211 | default 64 |
| 212 | |
Raul E Rangel | 5f52c0e | 2020-05-13 13:22:48 -0600 | [diff] [blame] | 213 | config VERSTAGE_ADDR |
| 214 | hex |
| 215 | default 0x4000000 |
| 216 | |
Felix Held | 1032d22 | 2020-11-04 16:19:35 +0100 | [diff] [blame] | 217 | config MAX_CPUS |
| 218 | int |
| 219 | default 8 |
Felix Held | b77387f | 2021-04-23 22:16:04 +0200 | [diff] [blame] | 220 | help |
| 221 | Maximum number of threads the platform can have. |
Felix Held | 1032d22 | 2020-11-04 16:19:35 +0100 | [diff] [blame] | 222 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 223 | config VGA_BIOS_ID |
| 224 | string |
Martin Roth | 86ba0d7 | 2020-02-05 16:46:30 -0700 | [diff] [blame] | 225 | default "1002,15d8,c1" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 226 | help |
| 227 | The default VGA BIOS PCI vendor/device ID should be set to the |
Martin Roth | 86ba0d7 | 2020-02-05 16:46:30 -0700 | [diff] [blame] | 228 | result of the map_oprom_vendev_rev() function in northbridge.c. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 229 | |
| 230 | config VGA_BIOS_FILE |
| 231 | string |
Raul E Rangel | f39dab1 | 2020-05-13 16:46:57 -0600 | [diff] [blame] | 232 | default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 233 | |
Martin Roth | 86ba0d7 | 2020-02-05 16:46:30 -0700 | [diff] [blame] | 234 | config VGA_BIOS_SECOND |
| 235 | def_bool y |
| 236 | |
| 237 | config VGA_BIOS_SECOND_ID |
| 238 | string |
| 239 | default "1002,15dd,c4" |
| 240 | help |
| 241 | Because Dali and Picasso need different video BIOSes, but have the |
| 242 | same vendor/device IDs, we need an alternate method to determine the |
| 243 | correct video BIOS. In map_oprom_vendev_rev(), we look at the cpuid |
| 244 | and decide which rom to load. |
| 245 | |
| 246 | Even though the hardware has the same vendor/device IDs, the vBIOS |
| 247 | contains a *different* device ID, confusing the situation even more. |
| 248 | |
| 249 | config VGA_BIOS_SECOND_FILE |
| 250 | string |
| 251 | default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin" |
| 252 | |
| 253 | config CHECK_REV_IN_OPROM_NAME |
| 254 | bool |
| 255 | default y |
| 256 | help |
| 257 | Select this in the platform BIOS or chipset if the option rom has a |
| 258 | revision that needs to be checked when searching CBFS. |
| 259 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 260 | config S3_VGA_ROM_RUN |
| 261 | bool |
| 262 | default n |
| 263 | |
| 264 | config HEAP_SIZE |
| 265 | hex |
| 266 | default 0xc0000 |
| 267 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 268 | config SERIRQ_CONTINUOUS_MODE |
| 269 | bool |
| 270 | default n |
| 271 | help |
| 272 | Set this option to y for serial IRQ in continuous mode. |
| 273 | Otherwise it is in quiet mode. |
| 274 | |
Felix Held | e738299 | 2021-01-12 23:05:56 +0100 | [diff] [blame] | 275 | config CONSOLE_UART_BASE_ADDRESS |
| 276 | depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART |
| 277 | hex |
| 278 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 279 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
Felix Held | d614e85 | 2021-06-15 21:06:38 +0200 | [diff] [blame] | 280 | default 0xfedce000 if UART_FOR_CONSOLE = 2 |
Felix Held | e738299 | 2021-01-12 23:05:56 +0100 | [diff] [blame] | 281 | default 0xfedcf000 if UART_FOR_CONSOLE = 3 |
| 282 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 283 | config SMM_TSEG_SIZE |
| 284 | hex |
Felix Held | e22eef7 | 2021-02-10 22:22:07 +0100 | [diff] [blame] | 285 | default 0x800000 if HAVE_SMI_HANDLER |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 286 | default 0x0 |
| 287 | |
| 288 | config SMM_RESERVED_SIZE |
| 289 | hex |
Marshall Dawson | 3e2fabf | 2020-06-12 10:28:04 -0600 | [diff] [blame] | 290 | default 0x180000 |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 291 | |
| 292 | config SMM_MODULE_STACK_SIZE |
| 293 | hex |
| 294 | default 0x800 |
| 295 | |
| 296 | config ACPI_CPU_STRING |
| 297 | string |
Jason Glenesk | f2a59a4 | 2020-08-10 00:58:37 -0700 | [diff] [blame] | 298 | default "\\_SB.C%03d" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 299 | |
| 300 | config ACPI_BERT |
| 301 | bool "Build ACPI BERT Table" |
| 302 | default y |
| 303 | depends on HAVE_ACPI_TABLES |
| 304 | help |
| 305 | Report Machine Check errors identified in POST to the OS in an |
Marshall Dawson | 03743b7 | 2020-06-18 10:23:48 -0600 | [diff] [blame] | 306 | ACPI Boot Error Record Table. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 307 | |
Marshall Dawson | 901cb9c | 2020-01-21 14:53:45 -0700 | [diff] [blame] | 308 | config ACPI_BERT_SIZE |
| 309 | hex |
Marshall Dawson | 03743b7 | 2020-06-18 10:23:48 -0600 | [diff] [blame] | 310 | default 0x4000 if ACPI_BERT |
| 311 | default 0x0 |
Marshall Dawson | 901cb9c | 2020-01-21 14:53:45 -0700 | [diff] [blame] | 312 | help |
| 313 | Specify the amount of DRAM reserved for gathering the data used to |
| 314 | generate the ACPI table. |
| 315 | |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 316 | config ACPI_SSDT_PSD_INDEPENDENT |
| 317 | bool "Allow core p-state independent transitions" |
| 318 | default y |
| 319 | help |
| 320 | AMD recommends the ACPI _PSD object to be configured to cause |
| 321 | cores to transition between p-states independently. A vendor may |
| 322 | choose to generate _PSD object to allow cores to transition together. |
| 323 | |
Furquan Shaikh | 40a3888 | 2020-05-01 10:43:48 -0700 | [diff] [blame] | 324 | config CHROMEOS |
Rob Barnes | 5ac928d | 2020-07-07 16:16:12 -0600 | [diff] [blame] | 325 | select ALWAYS_LOAD_OPROM |
| 326 | select ALWAYS_RUN_OPROM |
Furquan Shaikh | 40a3888 | 2020-05-01 10:43:48 -0700 | [diff] [blame] | 327 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 328 | config RO_REGION_ONLY |
| 329 | string |
| 330 | depends on CHROMEOS |
| 331 | default "apu/amdfw" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 332 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 333 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 334 | int |
Martin Roth | 4017de0 | 2019-12-16 23:21:05 -0700 | [diff] [blame] | 335 | default 150 |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 336 | |
Aaron Durbin | 1d0b99b | 2020-04-11 11:58:57 -0600 | [diff] [blame] | 337 | config DISABLE_SPI_FLASH_ROM_SHARING |
| 338 | def_bool n |
| 339 | help |
| 340 | Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin |
| 341 | which indicates a board level ROM transaction request. This |
| 342 | removes arbitration with board and assumes the chipset controls |
| 343 | the SPI flash bus entirely. |
| 344 | |
Felix Held | 27b295b | 2021-03-25 01:20:41 +0100 | [diff] [blame] | 345 | config DISABLE_KEYBOARD_RESET_PIN |
| 346 | bool |
| 347 | help |
| 348 | Instruct the SoC to not use the state of GPIO_129 as keyboard reset |
| 349 | signal. When this pin is used as GPIO and the keyboard reset |
| 350 | functionality isn't disabled, configuring it as an output and driving |
| 351 | it as 0 will cause a reset. |
| 352 | |
Marshall Dawson | 00a2208 | 2020-01-20 23:05:31 -0700 | [diff] [blame] | 353 | config FSP_TEMP_RAM_SIZE |
| 354 | hex |
Marshall Dawson | 00a2208 | 2020-01-20 23:05:31 -0700 | [diff] [blame] | 355 | default 0x40000 |
| 356 | help |
| 357 | The amount of coreboot-allocated heap and stack usage by the FSP. |
| 358 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 359 | menu "PSP Configuration Options" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 360 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 361 | config AMD_FWM_POSITION_INDEX |
| 362 | int "Firmware Directory Table location (0 to 5)" |
| 363 | range 0 5 |
| 364 | default 0 if BOARD_ROMSIZE_KB_512 |
| 365 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 366 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 367 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 368 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 369 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 370 | help |
| 371 | Typically this is calculated by the ROM size, but there may |
| 372 | be situations where you want to put the firmware directory |
| 373 | table in a different location. |
| 374 | 0: 512 KB - 0xFFFA0000 |
| 375 | 1: 1 MB - 0xFFF20000 |
| 376 | 2: 2 MB - 0xFFE20000 |
| 377 | 3: 4 MB - 0xFFC20000 |
| 378 | 4: 8 MB - 0xFF820000 |
| 379 | 5: 16 MB - 0xFF020000 |
| 380 | |
| 381 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 382 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 383 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 384 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 385 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 386 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 387 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 388 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 389 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 390 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 391 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 392 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 393 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 394 | config AMDFW_CONFIG_FILE |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 395 | string |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 396 | default "src/soc/amd/picasso/fw.cfg" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 397 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 398 | config PSP_LOAD_MP2_FW |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 399 | bool |
Furquan Shaikh | 47cdf43 | 2020-04-23 18:01:34 -0700 | [diff] [blame] | 400 | default n |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 401 | help |
| 402 | Include the MP2 firmwares and configuration into the PSP build. |
| 403 | |
Furquan Shaikh | 47cdf43 | 2020-04-23 18:01:34 -0700 | [diff] [blame] | 404 | If unsure, answer 'n' |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 405 | |
| 406 | config PSP_LOAD_S0I3_FW |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 407 | bool |
Furquan Shaikh | 30bc5b3 | 2020-04-23 18:02:53 -0700 | [diff] [blame] | 408 | default n |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 409 | help |
| 410 | Select this item to include the S0i3 file into the PSP build. |
| 411 | |
| 412 | config HAVE_PSP_WHITELIST_FILE |
| 413 | bool "Include a debug whitelist file in PSP build" |
| 414 | default n |
| 415 | help |
| 416 | Support secured unlock prior to reset using a whitelisted |
| 417 | number? This feature requires a signed whitelist image and |
| 418 | bootloader from AMD. |
| 419 | |
| 420 | If unsure, answer 'n' |
| 421 | |
| 422 | config PSP_WHITELIST_FILE |
Martin Roth | 49b09a0 | 2020-02-20 13:54:06 -0700 | [diff] [blame] | 423 | string "Debug whitelist file path" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 424 | depends on HAVE_PSP_WHITELIST_FILE |
Raul E Rangel | f39dab1 | 2020-05-13 16:46:57 -0600 | [diff] [blame] | 425 | default "3rdparty/amd_blobs/picasso/PSP/wtl-rvn.sbin" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 426 | |
Furquan Shaikh | 577db02 | 2020-04-24 15:52:04 -0700 | [diff] [blame] | 427 | config PSP_UNLOCK_SECURE_DEBUG |
| 428 | bool "Unlock secure debug" |
| 429 | default n |
| 430 | help |
| 431 | Select this item to enable secure debug options in PSP. |
| 432 | |
Martin Roth | de49833 | 2020-09-01 11:00:28 -0600 | [diff] [blame] | 433 | config PSP_VERSTAGE_FILE |
| 434 | string "Specify the PSP_verstage file path" |
| 435 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
Raul E Rangel | 21c70b1 | 2021-07-16 14:36:01 -0600 | [diff] [blame] | 436 | default "\$(obj)/psp_verstage.bin" |
Martin Roth | de49833 | 2020-09-01 11:00:28 -0600 | [diff] [blame] | 437 | help |
| 438 | Add psp_verstage file to the build & PSP Directory Table |
| 439 | |
Martin Roth | fe87d76 | 2020-09-01 11:04:21 -0600 | [diff] [blame] | 440 | config PSP_VERSTAGE_SIGNING_TOKEN |
| 441 | string "Specify the PSP_verstage Signature Token file path" |
| 442 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 443 | default "" |
| 444 | help |
| 445 | Add psp_verstage signature token to the build & PSP Directory Table |
| 446 | |
Martin Roth | fdad5ad | 2021-04-16 11:36:01 -0600 | [diff] [blame] | 447 | config PSP_SOFTFUSE_BITS |
| 448 | string "PSP Soft Fuse bits to enable" |
| 449 | default "28" |
| 450 | help |
| 451 | Space separated list of Soft Fuse bits to enable. |
| 452 | Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) |
| 453 | Bit 15: PSP post code destination: 0=LPC 1=eSPI |
| 454 | Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) |
| 455 | |
| 456 | See #55758 (NDA) for additional bit definitions. |
| 457 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 458 | endmenu |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 459 | |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 460 | config VBOOT |
| 461 | select VBOOT_VBNV_CMOS |
Martin Roth | e7e6c4e | 2020-07-15 11:54:14 -0600 | [diff] [blame] | 462 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 463 | |
| 464 | config VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 465 | def_bool n |
| 466 | depends on VBOOT |
| 467 | select ARCH_VERSTAGE_ARMV7 |
| 468 | help |
| 469 | Runs verstage on the PSP. Only available on |
| 470 | certain Chrome OS branded parts from AMD. |
| 471 | |
Martin Roth | 5632c6b | 2020-10-28 11:52:30 -0600 | [diff] [blame] | 472 | config VBOOT_HASH_BLOCK_SIZE |
| 473 | hex |
| 474 | default 0x9000 |
| 475 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 476 | help |
| 477 | Because the bulk of the time in psp_verstage to hash the RO cbfs is |
| 478 | spent in the overhead of doing svc calls, increasing the hash block |
| 479 | size significantly cuts the verstage hashing time as seen below. |
| 480 | |
| 481 | 4k takes 180ms |
| 482 | 16k takes 44ms |
| 483 | 32k takes 33.7ms |
| 484 | 36k takes 32.5ms |
| 485 | There's actually still room for an even bigger stack, but we've |
| 486 | reached a point of diminishing returns. |
| 487 | |
Martin Roth | 50cca76 | 2020-08-13 11:06:18 -0600 | [diff] [blame] | 488 | config CMOS_RECOVERY_BYTE |
| 489 | hex |
| 490 | default 0x51 |
| 491 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 492 | help |
| 493 | If the workbuf is not passed from the PSP to coreboot, set the |
| 494 | recovery flag and reboot. The PSP will read this byte, mark the |
| 495 | recovery request in VBNV, and reset the system into recovery mode. |
| 496 | |
| 497 | This is the byte before the default first byte used by VBNV |
| 498 | (0x26 + 0x0E - 1) |
| 499 | |
Martin Roth | 9aa8d11 | 2020-06-04 21:31:41 -0600 | [diff] [blame] | 500 | if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 501 | |
| 502 | config RWA_REGION_ONLY |
| 503 | string |
| 504 | default "apu/amdfw_a" |
| 505 | help |
| 506 | Add a space-delimited list of filenames that should only be in the |
| 507 | RW-A section. |
| 508 | |
| 509 | config RWB_REGION_ONLY |
| 510 | string |
| 511 | default "apu/amdfw_b" |
| 512 | help |
| 513 | Add a space-delimited list of filenames that should only be in the |
| 514 | RW-B section. |
| 515 | |
| 516 | config PICASSO_FW_A_POSITION |
| 517 | hex |
| 518 | help |
| 519 | Location of the AMD firmware in the RW_A region |
| 520 | |
| 521 | config PICASSO_FW_B_POSITION |
| 522 | hex |
| 523 | help |
| 524 | Location of the AMD firmware in the RW_B region |
| 525 | |
| 526 | endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 527 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 528 | endif # SOC_AMD_PICASSO |