Felix Held | 4a8cd72 | 2020-04-18 22:26:39 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 2 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 3 | config SOC_AMD_PICASSO |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 4 | bool |
| 5 | help |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 6 | AMD Picasso support |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 7 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 8 | if SOC_AMD_PICASSO |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 9 | |
| 10 | config CPU_SPECIFIC_OPTIONS |
| 11 | def_bool y |
| 12 | select ARCH_BOOTBLOCK_X86_32 |
| 13 | select ARCH_VERSTAGE_X86_32 |
| 14 | select ARCH_ROMSTAGE_X86_32 |
| 15 | select ARCH_RAMSTAGE_X86_32 |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 16 | select RESET_VECTOR_IN_RAM |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 17 | select X86_AMD_FIXED_MTRRS |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 18 | select X86_AMD_INIT_SIPI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 19 | select ACPI_AMD_HARDWARE_SLEEP_VALUES |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 20 | select DRIVERS_I2C_DESIGNWARE |
| 21 | select GENERIC_GPIO_LIB |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 22 | select IOAPIC |
Furquan Shaikh | 0eabe13 | 2020-04-28 21:57:07 -0700 | [diff] [blame] | 23 | select HAVE_EM100_SUPPORT |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 24 | select HAVE_USBDEBUG_OPTIONS |
Marshall Dawson | 80d0b01 | 2019-06-19 12:29:23 -0600 | [diff] [blame] | 25 | select TSC_MONOTONIC_TIMER |
Richard Spiegel | 65562cd65 | 2019-08-21 10:27:05 -0700 | [diff] [blame] | 26 | select SOC_AMD_COMMON_BLOCK_SPI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 27 | select TSC_SYNC_LFENCE |
Marshall Dawson | 80d0b01 | 2019-06-19 12:29:23 -0600 | [diff] [blame] | 28 | select UDELAY_TSC |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 29 | select SOC_AMD_COMMON |
| 30 | select SOC_AMD_COMMON_BLOCK |
Furquan Shaikh | 702cf30 | 2020-05-09 18:30:51 -0700 | [diff] [blame] | 31 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 32 | select SOC_AMD_COMMON_BLOCK_IOMMU |
| 33 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
| 34 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
| 35 | select SOC_AMD_COMMON_BLOCK_ACPI |
Furquan Shaikh | 9e1a49c | 2020-04-23 14:01:12 -0700 | [diff] [blame] | 36 | select SOC_AMD_COMMON_BLOCK_GRAPHICS |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 37 | select SOC_AMD_COMMON_BLOCK_LPC |
| 38 | select SOC_AMD_COMMON_BLOCK_PCI |
| 39 | select SOC_AMD_COMMON_BLOCK_HDA |
| 40 | select SOC_AMD_COMMON_BLOCK_SATA |
Aaron Durbin | 3d2e18a | 2020-01-28 11:20:05 -0700 | [diff] [blame] | 41 | select SOC_AMD_COMMON_BLOCK_SMBUS |
Marshall Dawson | 5a73fc3 | 2020-01-24 09:42:57 -0700 | [diff] [blame] | 42 | select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
Aaron Durbin | 1d0b99b | 2020-04-11 11:58:57 -0600 | [diff] [blame] | 43 | select PROVIDES_ROM_SHARING |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 44 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
| 45 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 46 | select PARALLEL_MP |
| 47 | select PARALLEL_MP_AP_WORK |
| 48 | select HAVE_SMI_HANDLER |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 49 | select SSE2 |
| 50 | select RTC |
Marshall Dawson | 00a2208 | 2020-01-20 23:05:31 -0700 | [diff] [blame] | 51 | select PLATFORM_USES_FSP2_0 |
| 52 | select FSP_USES_CB_STACK |
| 53 | select UDK_2017_BINDING |
| 54 | select HAVE_CF9_RESET |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 55 | |
Felix Held | 8cb5c30 | 2020-03-27 20:04:32 +0100 | [diff] [blame] | 56 | config AMD_FP5 |
| 57 | def_bool y if !AMD_FT5 |
| 58 | help |
| 59 | The FP5 package supports higher-wattage parts and dual channel DDR4 memory. |
| 60 | |
| 61 | config AMD_FT5 |
| 62 | def_bool n |
| 63 | help |
| 64 | The FT5 package supports low-power parts and single-channel DDR4 memory. |
| 65 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 66 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 67 | hex |
| 68 | default 0x1600 |
| 69 | help |
| 70 | Increase this value if preram cbmem console is getting truncated |
| 71 | |
| 72 | config CPU_ADDR_BITS |
| 73 | int |
| 74 | default 48 |
| 75 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 76 | config MMCONF_BASE_ADDRESS |
| 77 | hex |
| 78 | default 0xF8000000 |
| 79 | |
| 80 | config MMCONF_BUS_NUMBER |
| 81 | int |
| 82 | default 64 |
| 83 | |
Raul E Rangel | 5f52c0e | 2020-05-13 13:22:48 -0600 | [diff] [blame] | 84 | config VERSTAGE_ADDR |
| 85 | hex |
| 86 | default 0x4000000 |
| 87 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 88 | config VGA_BIOS_ID |
| 89 | string |
Marshall Dawson | 0d441da | 2019-07-09 18:19:05 -0500 | [diff] [blame] | 90 | default "1002,15d8" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 91 | help |
| 92 | The default VGA BIOS PCI vendor/device ID should be set to the |
| 93 | result of the map_oprom_vendev() function in northbridge.c. |
| 94 | |
| 95 | config VGA_BIOS_FILE |
| 96 | string |
Raul E Rangel | f39dab1 | 2020-05-13 16:46:57 -0600 | [diff] [blame^] | 97 | default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 98 | |
| 99 | config S3_VGA_ROM_RUN |
| 100 | bool |
| 101 | default n |
| 102 | |
| 103 | config HEAP_SIZE |
| 104 | hex |
| 105 | default 0xc0000 |
| 106 | |
| 107 | config EHCI_BAR |
| 108 | hex |
| 109 | default 0xfef00000 |
| 110 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 111 | config SERIRQ_CONTINUOUS_MODE |
| 112 | bool |
| 113 | default n |
| 114 | help |
| 115 | Set this option to y for serial IRQ in continuous mode. |
| 116 | Otherwise it is in quiet mode. |
| 117 | |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 118 | config PICASSO_ACPI_IO_BASE |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 119 | hex |
| 120 | default 0x400 |
| 121 | help |
| 122 | Base address for the ACPI registers. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 123 | |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 124 | config PICASSO_UART |
| 125 | bool "UART controller on Picasso" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 126 | default n |
| 127 | select DRIVERS_UART_8250MEM |
| 128 | select DRIVERS_UART_8250MEM_32 |
| 129 | select NO_UART_ON_SUPERIO |
| 130 | select UART_OVERRIDE_REFCLK |
| 131 | help |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 132 | There are four memory-mapped UARTs controllers in Picasso at: |
| 133 | 0: 0xfedc9000 |
| 134 | 1: 0xfedca000 |
| 135 | 2: 0xfedc3000 |
| 136 | 3: 0xfedcf000 |
| 137 | |
| 138 | choice PICASSO_UART_CLOCK_SOURCE |
| 139 | prompt "UART Frequency" |
| 140 | depends on PICASSO_UART |
| 141 | default PICASSO_UART_48MZ |
| 142 | |
| 143 | config PICASSO_UART_48MZ |
| 144 | bool "48 MHz clock" |
| 145 | help |
| 146 | Select this option for the most compatibility. |
| 147 | |
| 148 | config PICASSO_UART_1_8MZ |
| 149 | bool "1.8432 MHz clock" |
| 150 | help |
| 151 | Select this option if an old payload or Linux ttyS0 arguments |
| 152 | require it. |
| 153 | |
| 154 | endchoice |
| 155 | |
| 156 | config PICASSO_UART_LEGACY |
| 157 | bool "Decode legacy I/O range" |
| 158 | depends on PICASSO_UART |
| 159 | help |
| 160 | Assign I/O 3F8, 2F8, etc. to a Picasso UART. Only a single UART may |
| 161 | decode legacy addresses and this option enables the one used for the |
| 162 | console. A UART accessed with I/O does not allow all the features |
| 163 | of MMIO. The MMIO decode is still present when this option is used. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 164 | |
| 165 | config CONSOLE_UART_BASE_ADDRESS |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 166 | depends on CONSOLE_SERIAL && PICASSO_UART |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 167 | hex |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 168 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 169 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| 170 | default 0xfedc3000 if UART_FOR_CONSOLE = 2 |
| 171 | default 0xfedcf000 if UART_FOR_CONSOLE = 3 |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 172 | |
| 173 | config SMM_TSEG_SIZE |
| 174 | hex |
| 175 | default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER |
| 176 | default 0x0 |
| 177 | |
| 178 | config SMM_RESERVED_SIZE |
| 179 | hex |
| 180 | default 0x150000 |
| 181 | |
| 182 | config SMM_MODULE_STACK_SIZE |
| 183 | hex |
| 184 | default 0x800 |
| 185 | |
| 186 | config ACPI_CPU_STRING |
| 187 | string |
| 188 | default "\\_PR.P%03d" |
| 189 | |
| 190 | config ACPI_BERT |
| 191 | bool "Build ACPI BERT Table" |
| 192 | default y |
| 193 | depends on HAVE_ACPI_TABLES |
| 194 | help |
| 195 | Report Machine Check errors identified in POST to the OS in an |
| 196 | ACPI Boot Error Record Table. This option reserves an 8MB region |
| 197 | for building the error structures. |
| 198 | |
Marshall Dawson | 901cb9c | 2020-01-21 14:53:45 -0700 | [diff] [blame] | 199 | config ACPI_BERT_SIZE |
| 200 | hex |
| 201 | default 0x4000 |
| 202 | help |
| 203 | Specify the amount of DRAM reserved for gathering the data used to |
| 204 | generate the ACPI table. |
| 205 | |
Furquan Shaikh | 40a3888 | 2020-05-01 10:43:48 -0700 | [diff] [blame] | 206 | config CHROMEOS |
| 207 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 208 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 209 | config RO_REGION_ONLY |
| 210 | string |
| 211 | depends on CHROMEOS |
| 212 | default "apu/amdfw" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 213 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 214 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 215 | int |
Martin Roth | 4017de0 | 2019-12-16 23:21:05 -0700 | [diff] [blame] | 216 | default 150 |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 217 | |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 218 | config PICASSO_LPC_IOMUX |
| 219 | bool |
| 220 | help |
| 221 | Picasso's LPC bus signals are MUXed with some of the EMMC signals. |
| 222 | Select this option if LPC signals are required. |
| 223 | |
Aaron Durbin | 1d0b99b | 2020-04-11 11:58:57 -0600 | [diff] [blame] | 224 | config DISABLE_SPI_FLASH_ROM_SHARING |
| 225 | def_bool n |
| 226 | help |
| 227 | Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin |
| 228 | which indicates a board level ROM transaction request. This |
| 229 | removes arbitration with board and assumes the chipset controls |
| 230 | the SPI flash bus entirely. |
| 231 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 232 | config MAINBOARD_POWER_RESTORE |
| 233 | def_bool n |
| 234 | help |
| 235 | This option determines what state to go to once power is restored |
| 236 | after having been lost in S0. Select this option to automatically |
| 237 | return to S0. Otherwise the system will remain in S5 once power |
| 238 | is restored. |
| 239 | |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 240 | config X86_RESET_VECTOR |
| 241 | hex |
| 242 | default 0x807fff0 |
| 243 | |
| 244 | config EARLYRAM_BSP_STACK_SIZE |
| 245 | hex |
| 246 | default 0x800 |
| 247 | |
Marshall Dawson | 00a2208 | 2020-01-20 23:05:31 -0700 | [diff] [blame] | 248 | config FSP_TEMP_RAM_SIZE |
| 249 | hex |
| 250 | depends on FSP_USES_CB_STACK |
| 251 | default 0x40000 |
| 252 | help |
| 253 | The amount of coreboot-allocated heap and stack usage by the FSP. |
| 254 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 255 | menu "PSP Configuration Options" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 256 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 257 | config AMDFW_OUTSIDE_CBFS |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 258 | bool |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 259 | default n |
| 260 | help |
| 261 | The AMDFW (PSP) is typically locatable in cbfs. Select this |
| 262 | option to manually attach the generated amdfw.rom outside of |
| 263 | cbfs. The location is selected by the FWM position. |
| 264 | |
| 265 | config AMD_FWM_POSITION_INDEX |
| 266 | int "Firmware Directory Table location (0 to 5)" |
| 267 | range 0 5 |
| 268 | default 0 if BOARD_ROMSIZE_KB_512 |
| 269 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 270 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 271 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 272 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 273 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 274 | help |
| 275 | Typically this is calculated by the ROM size, but there may |
| 276 | be situations where you want to put the firmware directory |
| 277 | table in a different location. |
| 278 | 0: 512 KB - 0xFFFA0000 |
| 279 | 1: 1 MB - 0xFFF20000 |
| 280 | 2: 2 MB - 0xFFE20000 |
| 281 | 3: 4 MB - 0xFFC20000 |
| 282 | 4: 8 MB - 0xFF820000 |
| 283 | 5: 16 MB - 0xFF020000 |
| 284 | |
| 285 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 286 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 287 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 288 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 289 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 290 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 291 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 292 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 293 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 294 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 295 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 296 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 297 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 298 | config AMD_PUBKEY_FILE |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 299 | string |
Raul E Rangel | f39dab1 | 2020-05-13 16:46:57 -0600 | [diff] [blame^] | 300 | default "3rdparty/amd_blobs/picasso/PSP/AmdPubKeyRV.bin" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 301 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 302 | config PSP_APCB_FILE |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 303 | string |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 304 | help |
Marshall Dawson | 4357a82 | 2019-09-25 11:07:56 -0600 | [diff] [blame] | 305 | The name of the AGESA Parameter Customization Block. This image is |
| 306 | instance ID 0 in the PSP's BIOS Directory Table. |
| 307 | |
| 308 | config PSP_APCB1_FILE |
| 309 | string |
| 310 | help |
| 311 | If specified, this image is instance ID 1 in the PSP's BIOS |
| 312 | Directory Table. |
| 313 | |
| 314 | config PSP_APCB2_FILE |
| 315 | string |
| 316 | help |
| 317 | If specified, this image is instance ID 2 in the PSP's BIOS |
| 318 | Directory Table. |
| 319 | |
| 320 | config PSP_APCB3_FILE |
| 321 | string |
| 322 | help |
| 323 | If specified, this image is instance ID 3 in the PSP's BIOS |
| 324 | Directory Table. |
| 325 | |
| 326 | config PSP_APCB4_FILE |
| 327 | string |
| 328 | help |
| 329 | If specified, this image is instance ID 4 in the PSP's BIOS |
| 330 | Directory Table. |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 331 | |
| 332 | config PSP_APOB_DESTINATION |
| 333 | hex |
| 334 | default 0x9f00000 |
| 335 | help |
| 336 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 337 | Block. |
| 338 | |
| 339 | config PSP_APOB_NV_ADDRESS |
| 340 | hex "Base address of APOB NV" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 341 | help |
| 342 | Location in flash where the PSP can find the S3 restore information. |
| 343 | Place this on a boundary that the flash device can erase. |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 344 | |
| 345 | config PSP_APOB_NV_SIZE |
| 346 | hex "Size of APOB NV to be reserved" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 347 | help |
| 348 | Size of the S3 restore information. Make this a multiple of the |
| 349 | size the flash device can erase. |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 350 | |
| 351 | config USE_PSPSCUREOS |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 352 | bool |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 353 | default y |
| 354 | help |
| 355 | Include the PspSecureOs and PspTrustlet binaries in the PSP build. |
| 356 | |
| 357 | If unsure, answer 'y' |
| 358 | |
| 359 | config PSP_LOAD_MP2_FW |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 360 | bool |
Furquan Shaikh | 47cdf43 | 2020-04-23 18:01:34 -0700 | [diff] [blame] | 361 | default n |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 362 | help |
| 363 | Include the MP2 firmwares and configuration into the PSP build. |
| 364 | |
Furquan Shaikh | 47cdf43 | 2020-04-23 18:01:34 -0700 | [diff] [blame] | 365 | If unsure, answer 'n' |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 366 | |
| 367 | config PSP_LOAD_S0I3_FW |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 368 | bool |
Furquan Shaikh | 30bc5b3 | 2020-04-23 18:02:53 -0700 | [diff] [blame] | 369 | default n |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 370 | help |
| 371 | Select this item to include the S0i3 file into the PSP build. |
| 372 | |
| 373 | config HAVE_PSP_WHITELIST_FILE |
| 374 | bool "Include a debug whitelist file in PSP build" |
| 375 | default n |
| 376 | help |
| 377 | Support secured unlock prior to reset using a whitelisted |
| 378 | number? This feature requires a signed whitelist image and |
| 379 | bootloader from AMD. |
| 380 | |
| 381 | If unsure, answer 'n' |
| 382 | |
| 383 | config PSP_WHITELIST_FILE |
| 384 | string "Debug whitelist file name" |
| 385 | depends on HAVE_PSP_WHITELIST_FILE |
Raul E Rangel | f39dab1 | 2020-05-13 16:46:57 -0600 | [diff] [blame^] | 386 | default "3rdparty/amd_blobs/picasso/PSP/wtl-rvn.sbin" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 387 | |
Furquan Shaikh | 577db02 | 2020-04-24 15:52:04 -0700 | [diff] [blame] | 388 | config PSP_UNLOCK_SECURE_DEBUG |
| 389 | bool "Unlock secure debug" |
| 390 | default n |
| 391 | help |
| 392 | Select this item to enable secure debug options in PSP. |
| 393 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 394 | endmenu |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 395 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 396 | endif # SOC_AMD_PICASSO |