soc/amd/picasso: add psp_verstage
This is the main code for building coreboot's verstage as a userspace
application to run on the PSP. It does a minimal setup of hardware,
then runs verstage_main. It uses hardware hashing to increase the speed
and will directly reboot into recovery mode if there are any failures.
BUG=b:158124527
TEST=Build & boot trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index fd2a205..5872a6f 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -10,7 +10,7 @@
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_BOOTBLOCK_X86_32
- select ARCH_VERSTAGE_X86_32
+ select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select RESET_VECTOR_IN_RAM
@@ -473,6 +473,16 @@
Note that this option may conflict with the whitelist file if a
different PSP bootloader binary is specified.
+config PSP_SHAREDMEM_SIZE
+ hex "Maximum size of shared memory area"
+ default 0x3000 if VBOOT
+ default 0x0
+ help
+ Sets the maximum size for the PSP to pass the vboot workbuf and
+ any logs or timestamps back to coreboot. This will be copied
+ into main memory by the PSP and will be available when the x86 is
+ started.
+
config PSP_UNLOCK_SECURE_DEBUG
bool "Unlock secure debug"
default n
@@ -481,4 +491,17 @@
endmenu
+
+config VBOOT
+ select VBOOT_VBNV_CMOS
+ select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH if ! VBOOT_STARTS_BEFORE_BOOTBLOCK
+
+config VBOOT_STARTS_BEFORE_BOOTBLOCK
+ def_bool n
+ depends on VBOOT
+ select ARCH_VERSTAGE_ARMV7
+ help
+ Runs verstage on the PSP. Only available on
+ certain Chrome OS branded parts from AMD.
+
endif # SOC_AMD_PICASSO