soc/amd/picasso: Move BERT region to cbmem
Allocate storage for the BERT reserved memory in cbmem, and add it in
response to a romstage hook. Add a Kconfig option for adjusting the
size reserved. This is different from the Stoney Ridge implementation
where it was intentionally oversized to ease MTRR use and to keep TSEG
aligned.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4759154d394a8f5b35c0ef0a15994bbef25492e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38694
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 842ba0c..4759f01 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -199,6 +199,13 @@
ACPI Boot Error Record Table. This option reserves an 8MB region
for building the error structures.
+config ACPI_BERT_SIZE
+ hex
+ default 0x4000
+ help
+ Specify the amount of DRAM reserved for gathering the data used to
+ generate the ACPI table.
+
config RO_REGION_ONLY
string
depends on CHROMEOS