Felix Held | 4a8cd72 | 2020-04-18 22:26:39 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 2 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 3 | config SOC_AMD_PICASSO |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 4 | bool |
| 5 | help |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 6 | AMD Picasso support |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 7 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 8 | if SOC_AMD_PICASSO |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 9 | |
| 10 | config CPU_SPECIFIC_OPTIONS |
| 11 | def_bool y |
| 12 | select ARCH_BOOTBLOCK_X86_32 |
| 13 | select ARCH_VERSTAGE_X86_32 |
| 14 | select ARCH_ROMSTAGE_X86_32 |
| 15 | select ARCH_RAMSTAGE_X86_32 |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 16 | select RESET_VECTOR_IN_RAM |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 17 | select X86_AMD_FIXED_MTRRS |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 18 | select X86_AMD_INIT_SIPI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 19 | select ACPI_AMD_HARDWARE_SLEEP_VALUES |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 20 | select DRIVERS_I2C_DESIGNWARE |
| 21 | select GENERIC_GPIO_LIB |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 22 | select IOAPIC |
Furquan Shaikh | 0eabe13 | 2020-04-28 21:57:07 -0700 | [diff] [blame] | 23 | select HAVE_EM100_SUPPORT |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 24 | select HAVE_USBDEBUG_OPTIONS |
Marshall Dawson | 80d0b01 | 2019-06-19 12:29:23 -0600 | [diff] [blame] | 25 | select TSC_MONOTONIC_TIMER |
Richard Spiegel | 65562cd65 | 2019-08-21 10:27:05 -0700 | [diff] [blame] | 26 | select SOC_AMD_COMMON_BLOCK_SPI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 27 | select TSC_SYNC_LFENCE |
Marshall Dawson | 80d0b01 | 2019-06-19 12:29:23 -0600 | [diff] [blame] | 28 | select UDELAY_TSC |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 29 | select SOC_AMD_COMMON |
| 30 | select SOC_AMD_COMMON_BLOCK |
Furquan Shaikh | 702cf30 | 2020-05-09 18:30:51 -0700 | [diff] [blame] | 31 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 32 | select SOC_AMD_COMMON_BLOCK_IOMMU |
| 33 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
| 34 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
| 35 | select SOC_AMD_COMMON_BLOCK_ACPI |
Furquan Shaikh | 9e1a49c | 2020-04-23 14:01:12 -0700 | [diff] [blame] | 36 | select SOC_AMD_COMMON_BLOCK_GRAPHICS |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 37 | select SOC_AMD_COMMON_BLOCK_LPC |
| 38 | select SOC_AMD_COMMON_BLOCK_PCI |
| 39 | select SOC_AMD_COMMON_BLOCK_HDA |
| 40 | select SOC_AMD_COMMON_BLOCK_SATA |
Aaron Durbin | 3d2e18a | 2020-01-28 11:20:05 -0700 | [diff] [blame] | 41 | select SOC_AMD_COMMON_BLOCK_SMBUS |
Marshall Dawson | 5a73fc3 | 2020-01-24 09:42:57 -0700 | [diff] [blame] | 42 | select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
Aaron Durbin | 1d0b99b | 2020-04-11 11:58:57 -0600 | [diff] [blame] | 43 | select PROVIDES_ROM_SHARING |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 44 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
| 45 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 46 | select PARALLEL_MP |
| 47 | select PARALLEL_MP_AP_WORK |
| 48 | select HAVE_SMI_HANDLER |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 49 | select SSE2 |
| 50 | select RTC |
Marshall Dawson | 00a2208 | 2020-01-20 23:05:31 -0700 | [diff] [blame] | 51 | select PLATFORM_USES_FSP2_0 |
| 52 | select FSP_USES_CB_STACK |
| 53 | select UDK_2017_BINDING |
| 54 | select HAVE_CF9_RESET |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 55 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 56 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 57 | hex |
| 58 | default 0x1600 |
| 59 | help |
| 60 | Increase this value if preram cbmem console is getting truncated |
| 61 | |
| 62 | config CPU_ADDR_BITS |
| 63 | int |
| 64 | default 48 |
| 65 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 66 | config MMCONF_BASE_ADDRESS |
| 67 | hex |
| 68 | default 0xF8000000 |
| 69 | |
| 70 | config MMCONF_BUS_NUMBER |
| 71 | int |
| 72 | default 64 |
| 73 | |
Raul E Rangel | 5f52c0e | 2020-05-13 13:22:48 -0600 | [diff] [blame] | 74 | config VERSTAGE_ADDR |
| 75 | hex |
| 76 | default 0x4000000 |
| 77 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 78 | config VGA_BIOS_ID |
| 79 | string |
Marshall Dawson | 0d441da | 2019-07-09 18:19:05 -0500 | [diff] [blame] | 80 | default "1002,15d8" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 81 | help |
| 82 | The default VGA BIOS PCI vendor/device ID should be set to the |
| 83 | result of the map_oprom_vendev() function in northbridge.c. |
| 84 | |
| 85 | config VGA_BIOS_FILE |
| 86 | string |
Raul E Rangel | f39dab1 | 2020-05-13 16:46:57 -0600 | [diff] [blame] | 87 | default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 88 | |
| 89 | config S3_VGA_ROM_RUN |
| 90 | bool |
| 91 | default n |
| 92 | |
| 93 | config HEAP_SIZE |
| 94 | hex |
| 95 | default 0xc0000 |
| 96 | |
| 97 | config EHCI_BAR |
| 98 | hex |
| 99 | default 0xfef00000 |
| 100 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 101 | config SERIRQ_CONTINUOUS_MODE |
| 102 | bool |
| 103 | default n |
| 104 | help |
| 105 | Set this option to y for serial IRQ in continuous mode. |
| 106 | Otherwise it is in quiet mode. |
| 107 | |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 108 | config PICASSO_ACPI_IO_BASE |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 109 | hex |
| 110 | default 0x400 |
| 111 | help |
| 112 | Base address for the ACPI registers. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 113 | |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 114 | config PICASSO_UART |
| 115 | bool "UART controller on Picasso" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 116 | default n |
| 117 | select DRIVERS_UART_8250MEM |
| 118 | select DRIVERS_UART_8250MEM_32 |
| 119 | select NO_UART_ON_SUPERIO |
| 120 | select UART_OVERRIDE_REFCLK |
| 121 | help |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 122 | There are four memory-mapped UARTs controllers in Picasso at: |
| 123 | 0: 0xfedc9000 |
| 124 | 1: 0xfedca000 |
| 125 | 2: 0xfedc3000 |
| 126 | 3: 0xfedcf000 |
| 127 | |
| 128 | choice PICASSO_UART_CLOCK_SOURCE |
| 129 | prompt "UART Frequency" |
| 130 | depends on PICASSO_UART |
| 131 | default PICASSO_UART_48MZ |
| 132 | |
| 133 | config PICASSO_UART_48MZ |
| 134 | bool "48 MHz clock" |
| 135 | help |
| 136 | Select this option for the most compatibility. |
| 137 | |
| 138 | config PICASSO_UART_1_8MZ |
| 139 | bool "1.8432 MHz clock" |
| 140 | help |
| 141 | Select this option if an old payload or Linux ttyS0 arguments |
| 142 | require it. |
| 143 | |
| 144 | endchoice |
| 145 | |
| 146 | config PICASSO_UART_LEGACY |
| 147 | bool "Decode legacy I/O range" |
| 148 | depends on PICASSO_UART |
| 149 | help |
| 150 | Assign I/O 3F8, 2F8, etc. to a Picasso UART. Only a single UART may |
| 151 | decode legacy addresses and this option enables the one used for the |
| 152 | console. A UART accessed with I/O does not allow all the features |
| 153 | of MMIO. The MMIO decode is still present when this option is used. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 154 | |
| 155 | config CONSOLE_UART_BASE_ADDRESS |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 156 | depends on CONSOLE_SERIAL && PICASSO_UART |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 157 | hex |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 158 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 159 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| 160 | default 0xfedc3000 if UART_FOR_CONSOLE = 2 |
| 161 | default 0xfedcf000 if UART_FOR_CONSOLE = 3 |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 162 | |
| 163 | config SMM_TSEG_SIZE |
| 164 | hex |
| 165 | default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER |
| 166 | default 0x0 |
| 167 | |
| 168 | config SMM_RESERVED_SIZE |
| 169 | hex |
| 170 | default 0x150000 |
| 171 | |
| 172 | config SMM_MODULE_STACK_SIZE |
| 173 | hex |
| 174 | default 0x800 |
| 175 | |
| 176 | config ACPI_CPU_STRING |
| 177 | string |
| 178 | default "\\_PR.P%03d" |
| 179 | |
| 180 | config ACPI_BERT |
| 181 | bool "Build ACPI BERT Table" |
| 182 | default y |
| 183 | depends on HAVE_ACPI_TABLES |
| 184 | help |
| 185 | Report Machine Check errors identified in POST to the OS in an |
| 186 | ACPI Boot Error Record Table. This option reserves an 8MB region |
| 187 | for building the error structures. |
| 188 | |
Marshall Dawson | 901cb9c | 2020-01-21 14:53:45 -0700 | [diff] [blame] | 189 | config ACPI_BERT_SIZE |
| 190 | hex |
| 191 | default 0x4000 |
| 192 | help |
| 193 | Specify the amount of DRAM reserved for gathering the data used to |
| 194 | generate the ACPI table. |
| 195 | |
Furquan Shaikh | 40a3888 | 2020-05-01 10:43:48 -0700 | [diff] [blame] | 196 | config CHROMEOS |
| 197 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 198 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 199 | config RO_REGION_ONLY |
| 200 | string |
| 201 | depends on CHROMEOS |
| 202 | default "apu/amdfw" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 203 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 204 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 205 | int |
Martin Roth | 4017de0 | 2019-12-16 23:21:05 -0700 | [diff] [blame] | 206 | default 150 |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 207 | |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 208 | config PICASSO_LPC_IOMUX |
| 209 | bool |
| 210 | help |
| 211 | Picasso's LPC bus signals are MUXed with some of the EMMC signals. |
| 212 | Select this option if LPC signals are required. |
| 213 | |
Aaron Durbin | 1d0b99b | 2020-04-11 11:58:57 -0600 | [diff] [blame] | 214 | config DISABLE_SPI_FLASH_ROM_SHARING |
| 215 | def_bool n |
| 216 | help |
| 217 | Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin |
| 218 | which indicates a board level ROM transaction request. This |
| 219 | removes arbitration with board and assumes the chipset controls |
| 220 | the SPI flash bus entirely. |
| 221 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 222 | config MAINBOARD_POWER_RESTORE |
| 223 | def_bool n |
| 224 | help |
| 225 | This option determines what state to go to once power is restored |
| 226 | after having been lost in S0. Select this option to automatically |
| 227 | return to S0. Otherwise the system will remain in S5 once power |
| 228 | is restored. |
| 229 | |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 230 | config X86_RESET_VECTOR |
| 231 | hex |
| 232 | default 0x807fff0 |
| 233 | |
| 234 | config EARLYRAM_BSP_STACK_SIZE |
| 235 | hex |
| 236 | default 0x800 |
| 237 | |
Marshall Dawson | 00a2208 | 2020-01-20 23:05:31 -0700 | [diff] [blame] | 238 | config FSP_TEMP_RAM_SIZE |
| 239 | hex |
| 240 | depends on FSP_USES_CB_STACK |
| 241 | default 0x40000 |
| 242 | help |
| 243 | The amount of coreboot-allocated heap and stack usage by the FSP. |
| 244 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 245 | menu "PSP Configuration Options" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 246 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 247 | config AMDFW_OUTSIDE_CBFS |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 248 | bool |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 249 | default n |
| 250 | help |
| 251 | The AMDFW (PSP) is typically locatable in cbfs. Select this |
| 252 | option to manually attach the generated amdfw.rom outside of |
| 253 | cbfs. The location is selected by the FWM position. |
| 254 | |
| 255 | config AMD_FWM_POSITION_INDEX |
| 256 | int "Firmware Directory Table location (0 to 5)" |
| 257 | range 0 5 |
| 258 | default 0 if BOARD_ROMSIZE_KB_512 |
| 259 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 260 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 261 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 262 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 263 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 264 | help |
| 265 | Typically this is calculated by the ROM size, but there may |
| 266 | be situations where you want to put the firmware directory |
| 267 | table in a different location. |
| 268 | 0: 512 KB - 0xFFFA0000 |
| 269 | 1: 1 MB - 0xFFF20000 |
| 270 | 2: 2 MB - 0xFFE20000 |
| 271 | 3: 4 MB - 0xFFC20000 |
| 272 | 4: 8 MB - 0xFF820000 |
| 273 | 5: 16 MB - 0xFF020000 |
| 274 | |
| 275 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 276 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 277 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 278 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 279 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 280 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 281 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 282 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 283 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 284 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 285 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 286 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 287 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 288 | config AMD_PUBKEY_FILE |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 289 | string |
Raul E Rangel | f39dab1 | 2020-05-13 16:46:57 -0600 | [diff] [blame] | 290 | default "3rdparty/amd_blobs/picasso/PSP/AmdPubKeyRV.bin" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 291 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 292 | config PSP_APOB_DESTINATION |
| 293 | hex |
| 294 | default 0x9f00000 |
| 295 | help |
| 296 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 297 | Block. |
| 298 | |
| 299 | config PSP_APOB_NV_ADDRESS |
| 300 | hex "Base address of APOB NV" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 301 | help |
| 302 | Location in flash where the PSP can find the S3 restore information. |
| 303 | Place this on a boundary that the flash device can erase. |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 304 | |
| 305 | config PSP_APOB_NV_SIZE |
| 306 | hex "Size of APOB NV to be reserved" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 307 | help |
| 308 | Size of the S3 restore information. Make this a multiple of the |
| 309 | size the flash device can erase. |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 310 | |
| 311 | config USE_PSPSCUREOS |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 312 | bool |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 313 | default y |
| 314 | help |
| 315 | Include the PspSecureOs and PspTrustlet binaries in the PSP build. |
| 316 | |
| 317 | If unsure, answer 'y' |
| 318 | |
| 319 | config PSP_LOAD_MP2_FW |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 320 | bool |
Furquan Shaikh | 47cdf43 | 2020-04-23 18:01:34 -0700 | [diff] [blame] | 321 | default n |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 322 | help |
| 323 | Include the MP2 firmwares and configuration into the PSP build. |
| 324 | |
Furquan Shaikh | 47cdf43 | 2020-04-23 18:01:34 -0700 | [diff] [blame] | 325 | If unsure, answer 'n' |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 326 | |
| 327 | config PSP_LOAD_S0I3_FW |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 328 | bool |
Furquan Shaikh | 30bc5b3 | 2020-04-23 18:02:53 -0700 | [diff] [blame] | 329 | default n |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 330 | help |
| 331 | Select this item to include the S0i3 file into the PSP build. |
| 332 | |
| 333 | config HAVE_PSP_WHITELIST_FILE |
| 334 | bool "Include a debug whitelist file in PSP build" |
| 335 | default n |
| 336 | help |
| 337 | Support secured unlock prior to reset using a whitelisted |
| 338 | number? This feature requires a signed whitelist image and |
| 339 | bootloader from AMD. |
| 340 | |
| 341 | If unsure, answer 'n' |
| 342 | |
| 343 | config PSP_WHITELIST_FILE |
Martin Roth | 49b09a0 | 2020-02-20 13:54:06 -0700 | [diff] [blame^] | 344 | string "Debug whitelist file path" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 345 | depends on HAVE_PSP_WHITELIST_FILE |
Raul E Rangel | f39dab1 | 2020-05-13 16:46:57 -0600 | [diff] [blame] | 346 | default "3rdparty/amd_blobs/picasso/PSP/wtl-rvn.sbin" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 347 | |
Martin Roth | 49b09a0 | 2020-02-20 13:54:06 -0700 | [diff] [blame^] | 348 | config PSP_BOOTLOADER_FILE |
| 349 | string "Specify the PSP Bootloader file path" |
| 350 | default "3rdparty/amd_blobs/picasso/PSP/PspBootLoader_WL_RV.sbin" if HAVE_PSP_WHITELIST_FILE |
| 351 | default "3rdparty/amd_blobs/picasso/PSP/PspBootLoader_prod_RV.sbin" |
| 352 | help |
| 353 | Supply the name of the PSP bootloader file. |
| 354 | |
| 355 | Note that this option may conflict with the whitelist file if a |
| 356 | different PSP bootloader binary is specified. |
| 357 | |
Furquan Shaikh | 577db02 | 2020-04-24 15:52:04 -0700 | [diff] [blame] | 358 | config PSP_UNLOCK_SECURE_DEBUG |
| 359 | bool "Unlock secure debug" |
| 360 | default n |
| 361 | help |
| 362 | Select this item to enable secure debug options in PSP. |
| 363 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 364 | endmenu |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 365 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 366 | endif # SOC_AMD_PICASSO |