Felix Held | 4a8cd72 | 2020-04-18 22:26:39 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 2 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 3 | config SOC_AMD_PICASSO |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 4 | bool |
| 5 | help |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 6 | AMD Picasso support |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 7 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 8 | if SOC_AMD_PICASSO |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 9 | |
| 10 | config CPU_SPECIFIC_OPTIONS |
| 11 | def_bool y |
| 12 | select ARCH_BOOTBLOCK_X86_32 |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 13 | select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 14 | select ARCH_ROMSTAGE_X86_32 |
| 15 | select ARCH_RAMSTAGE_X86_32 |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 16 | select RESET_VECTOR_IN_RAM |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 17 | select X86_AMD_FIXED_MTRRS |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 18 | select X86_AMD_INIT_SIPI |
Kyösti Mälkki | 3139c8d | 2020-06-28 16:33:33 +0300 | [diff] [blame] | 19 | select ACPI_SOC_NVS |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 20 | select DRIVERS_I2C_DESIGNWARE |
Raul E Rangel | 0357ab7 | 2020-07-09 12:08:58 -0600 | [diff] [blame] | 21 | select DRIVERS_USB_PCI_XHCI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 22 | select GENERIC_GPIO_LIB |
Furquan Shaikh | 8e91509 | 2020-06-17 23:15:35 -0700 | [diff] [blame] | 23 | select IDT_IN_EVERY_STAGE |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 24 | select IOAPIC |
Felix Held | e697fd9 | 2021-01-18 15:10:43 +0100 | [diff] [blame] | 25 | select HAVE_ACPI_TABLES |
Furquan Shaikh | 0eabe13 | 2020-04-28 21:57:07 -0700 | [diff] [blame] | 26 | select HAVE_EM100_SUPPORT |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 27 | select SOC_AMD_COMMON |
Felix Held | 33c548b | 2021-01-27 20:34:24 +0100 | [diff] [blame] | 28 | select SOC_AMD_COMMON_BLOCK_ACPI |
| 29 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
| 30 | select SOC_AMD_COMMON_BLOCK_AOAC |
Felix Held | 21c46c0 | 2021-03-05 00:13:16 +0100 | [diff] [blame] | 31 | select SOC_AMD_COMMON_BLOCK_APOB |
Felix Held | 33c548b | 2021-01-27 20:34:24 +0100 | [diff] [blame] | 32 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
Felix Held | dba3fe7 | 2021-02-13 01:05:56 +0100 | [diff] [blame] | 33 | select SOC_AMD_COMMON_BLOCK_DATA_FABRIC |
Felix Held | 33c548b | 2021-01-27 20:34:24 +0100 | [diff] [blame] | 34 | select SOC_AMD_COMMON_BLOCK_GRAPHICS |
Furquan Shaikh | 702cf30 | 2020-05-09 18:30:51 -0700 | [diff] [blame] | 35 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 36 | select SOC_AMD_COMMON_BLOCK_HDA |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 37 | select SOC_AMD_COMMON_BLOCK_I2C |
Felix Held | 33c548b | 2021-01-27 20:34:24 +0100 | [diff] [blame] | 38 | select SOC_AMD_COMMON_BLOCK_IOMMU |
| 39 | select SOC_AMD_COMMON_BLOCK_LPC |
| 40 | select SOC_AMD_COMMON_BLOCK_NONCAR |
| 41 | select SOC_AMD_COMMON_BLOCK_PCI |
| 42 | select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 43 | select SOC_AMD_COMMON_BLOCK_SATA |
Aaron Durbin | 3d2e18a | 2020-01-28 11:20:05 -0700 | [diff] [blame] | 44 | select SOC_AMD_COMMON_BLOCK_SMBUS |
Felix Held | 161d809 | 2020-12-01 18:17:42 +0100 | [diff] [blame] | 45 | select SOC_AMD_COMMON_BLOCK_SMI |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 46 | select SOC_AMD_COMMON_BLOCK_SMM |
Felix Held | 60a4643 | 2020-11-12 00:14:16 +0100 | [diff] [blame] | 47 | select SOC_AMD_COMMON_BLOCK_SMU |
Felix Held | 33c548b | 2021-01-27 20:34:24 +0100 | [diff] [blame] | 48 | select SOC_AMD_COMMON_BLOCK_SPI |
Felix Held | 2f5c759 | 2020-12-04 17:31:10 +0100 | [diff] [blame] | 49 | select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H |
Felix Held | 6f8f9c9 | 2020-12-09 21:36:56 +0100 | [diff] [blame] | 50 | select SOC_AMD_COMMON_BLOCK_UART |
Raul E Rangel | 394c6b0 | 2021-02-12 14:37:43 -0700 | [diff] [blame] | 51 | select SOC_AMD_COMMON_BLOCK_UCODE |
Aaron Durbin | 1d0b99b | 2020-04-11 11:58:57 -0600 | [diff] [blame] | 52 | select PROVIDES_ROM_SHARING |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 53 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 54 | select PARALLEL_MP |
| 55 | select PARALLEL_MP_AP_WORK |
| 56 | select HAVE_SMI_HANDLER |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 57 | select SSE2 |
| 58 | select RTC |
Marshall Dawson | 00a2208 | 2020-01-20 23:05:31 -0700 | [diff] [blame] | 59 | select PLATFORM_USES_FSP2_0 |
Furquan Shaikh | c3063c5 | 2020-05-28 11:58:20 -0700 | [diff] [blame] | 60 | select FSP_COMPRESS_FSP_M_LZMA |
| 61 | select FSP_COMPRESS_FSP_S_LZMA |
Marshall Dawson | 00a2208 | 2020-01-20 23:05:31 -0700 | [diff] [blame] | 62 | select UDK_2017_BINDING |
| 63 | select HAVE_CF9_RESET |
Raul E Rangel | 394c6b0 | 2021-02-12 14:37:43 -0700 | [diff] [blame] | 64 | |
| 65 | config SOC_AMD_COMMON_BLOCK_UCODE_SIZE |
| 66 | default 3200 |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 67 | |
Felix Held | 3cc3d81 | 2020-06-17 16:16:08 +0200 | [diff] [blame] | 68 | config FSP_M_FILE |
| 69 | string "FSP-M (memory init) binary path and filename" |
| 70 | depends on ADD_FSP_BINARIES |
| 71 | default "3rdparty/amd_blobs/picasso/PICASSO_M.fd" |
| 72 | help |
| 73 | The path and filename of the FSP-M binary for this platform. |
| 74 | |
| 75 | config FSP_S_FILE |
| 76 | string "FSP-S (silicon init) binary path and filename" |
| 77 | depends on ADD_FSP_BINARIES |
| 78 | default "3rdparty/amd_blobs/picasso/PICASSO_S.fd" |
| 79 | help |
| 80 | The path and filename of the FSP-S binary for this platform. |
| 81 | |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 82 | config EARLY_RESERVED_DRAM_BASE |
| 83 | hex |
| 84 | default 0x2000000 |
| 85 | help |
| 86 | This variable defines the base address of the DRAM which is reserved |
| 87 | for usage by coreboot in early stages (i.e. before ramstage is up). |
| 88 | This memory gets reserved in BIOS tables to ensure that the OS does |
| 89 | not use it, thus preventing corruption of OS memory in case of S3 |
| 90 | resume. |
| 91 | |
| 92 | config EARLYRAM_BSP_STACK_SIZE |
| 93 | hex |
| 94 | default 0x1000 |
| 95 | |
| 96 | config PSP_APOB_DRAM_ADDRESS |
| 97 | hex |
| 98 | default 0x2001000 |
| 99 | help |
| 100 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 101 | Block. |
| 102 | |
| 103 | config PSP_SHAREDMEM_BASE |
| 104 | hex |
| 105 | default 0x2011000 if VBOOT |
| 106 | default 0x0 |
| 107 | help |
| 108 | This variable defines the base address in DRAM memory where PSP copies |
| 109 | vboot workbuf to. This is used in linker script to have a static |
| 110 | allocation for the buffer as well as for adding relevant entries in |
| 111 | BIOS directory table for the PSP. |
| 112 | |
| 113 | config PSP_SHAREDMEM_SIZE |
| 114 | hex |
| 115 | default 0x8000 if VBOOT |
| 116 | default 0x0 |
| 117 | help |
| 118 | Sets the maximum size for the PSP to pass the vboot workbuf and |
| 119 | any logs or timestamps back to coreboot. This will be copied |
| 120 | into main memory by the PSP and will be available when the x86 is |
| 121 | started. The workbuf's base depends on the address of the reset |
| 122 | vector. |
| 123 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 124 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 125 | hex |
| 126 | default 0x1600 |
| 127 | help |
| 128 | Increase this value if preram cbmem console is getting truncated |
| 129 | |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 130 | config C_ENV_BOOTBLOCK_SIZE |
| 131 | hex |
| 132 | default 0x10000 |
| 133 | help |
| 134 | Sets the size of the bootblock stage that should be loaded in DRAM. |
| 135 | This variable controls the DRAM allocation size in linker script |
| 136 | for bootblock stage. |
| 137 | |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 138 | config ROMSTAGE_ADDR |
| 139 | hex |
| 140 | default 0x2040000 |
| 141 | help |
| 142 | Sets the address in DRAM where romstage should be loaded. |
| 143 | |
| 144 | config ROMSTAGE_SIZE |
| 145 | hex |
| 146 | default 0x80000 |
| 147 | help |
| 148 | Sets the size of DRAM allocation for romstage in linker script. |
| 149 | |
| 150 | config FSP_M_ADDR |
| 151 | hex |
| 152 | default 0x20C0000 |
| 153 | help |
| 154 | Sets the address in DRAM where FSP-M should be loaded. cbfstool |
| 155 | performs relocation of FSP-M to this address. |
| 156 | |
| 157 | config FSP_M_SIZE |
| 158 | hex |
| 159 | default 0x80000 |
| 160 | help |
| 161 | Sets the size of DRAM allocation for FSP-M in linker script. |
| 162 | |
| 163 | config VERSTAGE_ADDR |
| 164 | hex |
| 165 | depends on VBOOT_SEPARATE_VERSTAGE |
| 166 | default 0x2140000 |
| 167 | help |
| 168 | Sets the address in DRAM where verstage should be loaded if running |
| 169 | as a separate stage on x86. |
| 170 | |
| 171 | config VERSTAGE_SIZE |
| 172 | hex |
| 173 | depends on VBOOT_SEPARATE_VERSTAGE |
| 174 | default 0x80000 |
| 175 | help |
| 176 | Sets the size of DRAM allocation for verstage in linker script if |
| 177 | running as a separate stage on x86. |
| 178 | |
| 179 | config RAMBASE |
| 180 | hex |
| 181 | default 0x10000000 |
| 182 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 183 | config CPU_ADDR_BITS |
| 184 | int |
| 185 | default 48 |
| 186 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 187 | config MMCONF_BASE_ADDRESS |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 188 | default 0xF8000000 |
| 189 | |
| 190 | config MMCONF_BUS_NUMBER |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 191 | default 64 |
| 192 | |
Raul E Rangel | 5f52c0e | 2020-05-13 13:22:48 -0600 | [diff] [blame] | 193 | config VERSTAGE_ADDR |
| 194 | hex |
| 195 | default 0x4000000 |
| 196 | |
Felix Held | 1032d22 | 2020-11-04 16:19:35 +0100 | [diff] [blame] | 197 | config MAX_CPUS |
| 198 | int |
| 199 | default 8 |
| 200 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 201 | config VGA_BIOS_ID |
| 202 | string |
Martin Roth | 86ba0d7 | 2020-02-05 16:46:30 -0700 | [diff] [blame] | 203 | default "1002,15d8,c1" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 204 | help |
| 205 | The default VGA BIOS PCI vendor/device ID should be set to the |
Martin Roth | 86ba0d7 | 2020-02-05 16:46:30 -0700 | [diff] [blame] | 206 | result of the map_oprom_vendev_rev() function in northbridge.c. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 207 | |
| 208 | config VGA_BIOS_FILE |
| 209 | string |
Raul E Rangel | f39dab1 | 2020-05-13 16:46:57 -0600 | [diff] [blame] | 210 | default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 211 | |
Martin Roth | 86ba0d7 | 2020-02-05 16:46:30 -0700 | [diff] [blame] | 212 | config VGA_BIOS_SECOND |
| 213 | def_bool y |
| 214 | |
| 215 | config VGA_BIOS_SECOND_ID |
| 216 | string |
| 217 | default "1002,15dd,c4" |
| 218 | help |
| 219 | Because Dali and Picasso need different video BIOSes, but have the |
| 220 | same vendor/device IDs, we need an alternate method to determine the |
| 221 | correct video BIOS. In map_oprom_vendev_rev(), we look at the cpuid |
| 222 | and decide which rom to load. |
| 223 | |
| 224 | Even though the hardware has the same vendor/device IDs, the vBIOS |
| 225 | contains a *different* device ID, confusing the situation even more. |
| 226 | |
| 227 | config VGA_BIOS_SECOND_FILE |
| 228 | string |
| 229 | default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin" |
| 230 | |
| 231 | config CHECK_REV_IN_OPROM_NAME |
| 232 | bool |
| 233 | default y |
| 234 | help |
| 235 | Select this in the platform BIOS or chipset if the option rom has a |
| 236 | revision that needs to be checked when searching CBFS. |
| 237 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 238 | config S3_VGA_ROM_RUN |
| 239 | bool |
| 240 | default n |
| 241 | |
| 242 | config HEAP_SIZE |
| 243 | hex |
| 244 | default 0xc0000 |
| 245 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 246 | config SERIRQ_CONTINUOUS_MODE |
| 247 | bool |
| 248 | default n |
| 249 | help |
| 250 | Set this option to y for serial IRQ in continuous mode. |
| 251 | Otherwise it is in quiet mode. |
| 252 | |
Felix Held | e738299 | 2021-01-12 23:05:56 +0100 | [diff] [blame] | 253 | config CONSOLE_UART_BASE_ADDRESS |
| 254 | depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART |
| 255 | hex |
| 256 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 257 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| 258 | default 0xfedc3000 if UART_FOR_CONSOLE = 2 |
| 259 | default 0xfedcf000 if UART_FOR_CONSOLE = 3 |
| 260 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 261 | config SMM_TSEG_SIZE |
| 262 | hex |
Felix Held | e22eef7 | 2021-02-10 22:22:07 +0100 | [diff] [blame] | 263 | default 0x800000 if HAVE_SMI_HANDLER |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 264 | default 0x0 |
| 265 | |
| 266 | config SMM_RESERVED_SIZE |
| 267 | hex |
Marshall Dawson | 3e2fabf | 2020-06-12 10:28:04 -0600 | [diff] [blame] | 268 | default 0x180000 |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 269 | |
| 270 | config SMM_MODULE_STACK_SIZE |
| 271 | hex |
| 272 | default 0x800 |
| 273 | |
| 274 | config ACPI_CPU_STRING |
| 275 | string |
Jason Glenesk | f2a59a4 | 2020-08-10 00:58:37 -0700 | [diff] [blame] | 276 | default "\\_SB.C%03d" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 277 | |
| 278 | config ACPI_BERT |
| 279 | bool "Build ACPI BERT Table" |
| 280 | default y |
| 281 | depends on HAVE_ACPI_TABLES |
| 282 | help |
| 283 | Report Machine Check errors identified in POST to the OS in an |
Marshall Dawson | 03743b7 | 2020-06-18 10:23:48 -0600 | [diff] [blame] | 284 | ACPI Boot Error Record Table. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 285 | |
Marshall Dawson | 901cb9c | 2020-01-21 14:53:45 -0700 | [diff] [blame] | 286 | config ACPI_BERT_SIZE |
| 287 | hex |
Marshall Dawson | 03743b7 | 2020-06-18 10:23:48 -0600 | [diff] [blame] | 288 | default 0x4000 if ACPI_BERT |
| 289 | default 0x0 |
Marshall Dawson | 901cb9c | 2020-01-21 14:53:45 -0700 | [diff] [blame] | 290 | help |
| 291 | Specify the amount of DRAM reserved for gathering the data used to |
| 292 | generate the ACPI table. |
| 293 | |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 294 | config ACPI_SSDT_PSD_INDEPENDENT |
| 295 | bool "Allow core p-state independent transitions" |
| 296 | default y |
| 297 | help |
| 298 | AMD recommends the ACPI _PSD object to be configured to cause |
| 299 | cores to transition between p-states independently. A vendor may |
| 300 | choose to generate _PSD object to allow cores to transition together. |
| 301 | |
Furquan Shaikh | 40a3888 | 2020-05-01 10:43:48 -0700 | [diff] [blame] | 302 | config CHROMEOS |
Rob Barnes | 5ac928d | 2020-07-07 16:16:12 -0600 | [diff] [blame] | 303 | select ALWAYS_LOAD_OPROM |
| 304 | select ALWAYS_RUN_OPROM |
Furquan Shaikh | 40a3888 | 2020-05-01 10:43:48 -0700 | [diff] [blame] | 305 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 306 | config RO_REGION_ONLY |
| 307 | string |
| 308 | depends on CHROMEOS |
| 309 | default "apu/amdfw" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 310 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 311 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 312 | int |
Martin Roth | 4017de0 | 2019-12-16 23:21:05 -0700 | [diff] [blame] | 313 | default 150 |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 314 | |
Aaron Durbin | 1d0b99b | 2020-04-11 11:58:57 -0600 | [diff] [blame] | 315 | config DISABLE_SPI_FLASH_ROM_SHARING |
| 316 | def_bool n |
| 317 | help |
| 318 | Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin |
| 319 | which indicates a board level ROM transaction request. This |
| 320 | removes arbitration with board and assumes the chipset controls |
| 321 | the SPI flash bus entirely. |
| 322 | |
Felix Held | 27b295b | 2021-03-25 01:20:41 +0100 | [diff] [blame^] | 323 | config DISABLE_KEYBOARD_RESET_PIN |
| 324 | bool |
| 325 | help |
| 326 | Instruct the SoC to not use the state of GPIO_129 as keyboard reset |
| 327 | signal. When this pin is used as GPIO and the keyboard reset |
| 328 | functionality isn't disabled, configuring it as an output and driving |
| 329 | it as 0 will cause a reset. |
| 330 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 331 | config MAINBOARD_POWER_RESTORE |
| 332 | def_bool n |
| 333 | help |
| 334 | This option determines what state to go to once power is restored |
| 335 | after having been lost in S0. Select this option to automatically |
| 336 | return to S0. Otherwise the system will remain in S5 once power |
| 337 | is restored. |
| 338 | |
Marshall Dawson | 00a2208 | 2020-01-20 23:05:31 -0700 | [diff] [blame] | 339 | config FSP_TEMP_RAM_SIZE |
| 340 | hex |
Marshall Dawson | 00a2208 | 2020-01-20 23:05:31 -0700 | [diff] [blame] | 341 | default 0x40000 |
| 342 | help |
| 343 | The amount of coreboot-allocated heap and stack usage by the FSP. |
| 344 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 345 | menu "PSP Configuration Options" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 346 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 347 | config AMD_FWM_POSITION_INDEX |
| 348 | int "Firmware Directory Table location (0 to 5)" |
| 349 | range 0 5 |
| 350 | default 0 if BOARD_ROMSIZE_KB_512 |
| 351 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 352 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 353 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 354 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 355 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 356 | help |
| 357 | Typically this is calculated by the ROM size, but there may |
| 358 | be situations where you want to put the firmware directory |
| 359 | table in a different location. |
| 360 | 0: 512 KB - 0xFFFA0000 |
| 361 | 1: 1 MB - 0xFFF20000 |
| 362 | 2: 2 MB - 0xFFE20000 |
| 363 | 3: 4 MB - 0xFFC20000 |
| 364 | 4: 8 MB - 0xFF820000 |
| 365 | 5: 16 MB - 0xFF020000 |
| 366 | |
| 367 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 368 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 369 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 370 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 371 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 372 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 373 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 374 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 375 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 376 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 377 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 378 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 379 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 380 | config AMDFW_CONFIG_FILE |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 381 | string |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 382 | default "src/soc/amd/picasso/fw.cfg" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 383 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 384 | config PSP_LOAD_MP2_FW |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 385 | bool |
Furquan Shaikh | 47cdf43 | 2020-04-23 18:01:34 -0700 | [diff] [blame] | 386 | default n |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 387 | help |
| 388 | Include the MP2 firmwares and configuration into the PSP build. |
| 389 | |
Furquan Shaikh | 47cdf43 | 2020-04-23 18:01:34 -0700 | [diff] [blame] | 390 | If unsure, answer 'n' |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 391 | |
| 392 | config PSP_LOAD_S0I3_FW |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 393 | bool |
Furquan Shaikh | 30bc5b3 | 2020-04-23 18:02:53 -0700 | [diff] [blame] | 394 | default n |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 395 | help |
| 396 | Select this item to include the S0i3 file into the PSP build. |
| 397 | |
| 398 | config HAVE_PSP_WHITELIST_FILE |
| 399 | bool "Include a debug whitelist file in PSP build" |
| 400 | default n |
| 401 | help |
| 402 | Support secured unlock prior to reset using a whitelisted |
| 403 | number? This feature requires a signed whitelist image and |
| 404 | bootloader from AMD. |
| 405 | |
| 406 | If unsure, answer 'n' |
| 407 | |
| 408 | config PSP_WHITELIST_FILE |
Martin Roth | 49b09a0 | 2020-02-20 13:54:06 -0700 | [diff] [blame] | 409 | string "Debug whitelist file path" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 410 | depends on HAVE_PSP_WHITELIST_FILE |
Raul E Rangel | f39dab1 | 2020-05-13 16:46:57 -0600 | [diff] [blame] | 411 | default "3rdparty/amd_blobs/picasso/PSP/wtl-rvn.sbin" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 412 | |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 413 | config PSP_SHAREDMEM_SIZE |
| 414 | hex "Maximum size of shared memory area" |
| 415 | default 0x3000 if VBOOT |
| 416 | default 0x0 |
| 417 | help |
| 418 | Sets the maximum size for the PSP to pass the vboot workbuf and |
| 419 | any logs or timestamps back to coreboot. This will be copied |
| 420 | into main memory by the PSP and will be available when the x86 is |
| 421 | started. |
| 422 | |
Furquan Shaikh | 577db02 | 2020-04-24 15:52:04 -0700 | [diff] [blame] | 423 | config PSP_UNLOCK_SECURE_DEBUG |
| 424 | bool "Unlock secure debug" |
| 425 | default n |
| 426 | help |
| 427 | Select this item to enable secure debug options in PSP. |
| 428 | |
Martin Roth | de49833 | 2020-09-01 11:00:28 -0600 | [diff] [blame] | 429 | config PSP_VERSTAGE_FILE |
| 430 | string "Specify the PSP_verstage file path" |
| 431 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 432 | default "$(obj)/psp_verstage.bin" |
| 433 | help |
| 434 | Add psp_verstage file to the build & PSP Directory Table |
| 435 | |
Martin Roth | fe87d76 | 2020-09-01 11:04:21 -0600 | [diff] [blame] | 436 | config PSP_VERSTAGE_SIGNING_TOKEN |
| 437 | string "Specify the PSP_verstage Signature Token file path" |
| 438 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 439 | default "" |
| 440 | help |
| 441 | Add psp_verstage signature token to the build & PSP Directory Table |
| 442 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 443 | endmenu |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 444 | |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 445 | config VBOOT |
| 446 | select VBOOT_VBNV_CMOS |
Martin Roth | e7e6c4e | 2020-07-15 11:54:14 -0600 | [diff] [blame] | 447 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 448 | |
| 449 | config VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 450 | def_bool n |
| 451 | depends on VBOOT |
| 452 | select ARCH_VERSTAGE_ARMV7 |
| 453 | help |
| 454 | Runs verstage on the PSP. Only available on |
| 455 | certain Chrome OS branded parts from AMD. |
| 456 | |
Martin Roth | 5632c6b | 2020-10-28 11:52:30 -0600 | [diff] [blame] | 457 | config VBOOT_HASH_BLOCK_SIZE |
| 458 | hex |
| 459 | default 0x9000 |
| 460 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 461 | help |
| 462 | Because the bulk of the time in psp_verstage to hash the RO cbfs is |
| 463 | spent in the overhead of doing svc calls, increasing the hash block |
| 464 | size significantly cuts the verstage hashing time as seen below. |
| 465 | |
| 466 | 4k takes 180ms |
| 467 | 16k takes 44ms |
| 468 | 32k takes 33.7ms |
| 469 | 36k takes 32.5ms |
| 470 | There's actually still room for an even bigger stack, but we've |
| 471 | reached a point of diminishing returns. |
| 472 | |
Martin Roth | 50cca76 | 2020-08-13 11:06:18 -0600 | [diff] [blame] | 473 | config CMOS_RECOVERY_BYTE |
| 474 | hex |
| 475 | default 0x51 |
| 476 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 477 | help |
| 478 | If the workbuf is not passed from the PSP to coreboot, set the |
| 479 | recovery flag and reboot. The PSP will read this byte, mark the |
| 480 | recovery request in VBNV, and reset the system into recovery mode. |
| 481 | |
| 482 | This is the byte before the default first byte used by VBNV |
| 483 | (0x26 + 0x0E - 1) |
| 484 | |
Martin Roth | 9aa8d11 | 2020-06-04 21:31:41 -0600 | [diff] [blame] | 485 | if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 486 | |
| 487 | config RWA_REGION_ONLY |
| 488 | string |
| 489 | default "apu/amdfw_a" |
| 490 | help |
| 491 | Add a space-delimited list of filenames that should only be in the |
| 492 | RW-A section. |
| 493 | |
| 494 | config RWB_REGION_ONLY |
| 495 | string |
| 496 | default "apu/amdfw_b" |
| 497 | help |
| 498 | Add a space-delimited list of filenames that should only be in the |
| 499 | RW-B section. |
| 500 | |
| 501 | config PICASSO_FW_A_POSITION |
| 502 | hex |
| 503 | help |
| 504 | Location of the AMD firmware in the RW_A region |
| 505 | |
| 506 | config PICASSO_FW_B_POSITION |
| 507 | hex |
| 508 | help |
| 509 | Location of the AMD firmware in the RW_B region |
| 510 | |
| 511 | endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 512 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 513 | endif # SOC_AMD_PICASSO |