Felix Held | 4a8cd72 | 2020-04-18 22:26:39 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | # This file is part of the coreboot project. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 3 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 4 | config SOC_AMD_PICASSO |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 5 | bool |
| 6 | help |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 7 | AMD Picasso support |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 8 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 9 | if SOC_AMD_PICASSO |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 10 | |
| 11 | config CPU_SPECIFIC_OPTIONS |
| 12 | def_bool y |
| 13 | select ARCH_BOOTBLOCK_X86_32 |
| 14 | select ARCH_VERSTAGE_X86_32 |
| 15 | select ARCH_ROMSTAGE_X86_32 |
| 16 | select ARCH_RAMSTAGE_X86_32 |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 17 | select RESET_VECTOR_IN_RAM |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 18 | select X86_AMD_FIXED_MTRRS |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 19 | select X86_AMD_INIT_SIPI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 20 | select ACPI_AMD_HARDWARE_SLEEP_VALUES |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 21 | select DRIVERS_I2C_DESIGNWARE |
| 22 | select GENERIC_GPIO_LIB |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 23 | select IOAPIC |
Furquan Shaikh | 0eabe13 | 2020-04-28 21:57:07 -0700 | [diff] [blame^] | 24 | select HAVE_EM100_SUPPORT |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 25 | select HAVE_USBDEBUG_OPTIONS |
Marshall Dawson | 80d0b01 | 2019-06-19 12:29:23 -0600 | [diff] [blame] | 26 | select TSC_MONOTONIC_TIMER |
Richard Spiegel | 65562cd65 | 2019-08-21 10:27:05 -0700 | [diff] [blame] | 27 | select SOC_AMD_COMMON_BLOCK_SPI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 28 | select TSC_SYNC_LFENCE |
Marshall Dawson | 80d0b01 | 2019-06-19 12:29:23 -0600 | [diff] [blame] | 29 | select UDELAY_TSC |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 30 | select SOC_AMD_COMMON |
| 31 | select SOC_AMD_COMMON_BLOCK |
| 32 | select SOC_AMD_COMMON_BLOCK_IOMMU |
| 33 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
| 34 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
| 35 | select SOC_AMD_COMMON_BLOCK_ACPI |
Furquan Shaikh | 9e1a49c | 2020-04-23 14:01:12 -0700 | [diff] [blame] | 36 | select SOC_AMD_COMMON_BLOCK_GRAPHICS |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 37 | select SOC_AMD_COMMON_BLOCK_LPC |
| 38 | select SOC_AMD_COMMON_BLOCK_PCI |
| 39 | select SOC_AMD_COMMON_BLOCK_HDA |
| 40 | select SOC_AMD_COMMON_BLOCK_SATA |
Aaron Durbin | 3d2e18a | 2020-01-28 11:20:05 -0700 | [diff] [blame] | 41 | select SOC_AMD_COMMON_BLOCK_SMBUS |
Marshall Dawson | 5a73fc3 | 2020-01-24 09:42:57 -0700 | [diff] [blame] | 42 | select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 43 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
| 44 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 45 | select PARALLEL_MP |
| 46 | select PARALLEL_MP_AP_WORK |
| 47 | select HAVE_SMI_HANDLER |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 48 | select SSE2 |
| 49 | select RTC |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 50 | |
Felix Held | 8cb5c30 | 2020-03-27 20:04:32 +0100 | [diff] [blame] | 51 | config AMD_FP5 |
| 52 | def_bool y if !AMD_FT5 |
| 53 | help |
| 54 | The FP5 package supports higher-wattage parts and dual channel DDR4 memory. |
| 55 | |
| 56 | config AMD_FT5 |
| 57 | def_bool n |
| 58 | help |
| 59 | The FT5 package supports low-power parts and single-channel DDR4 memory. |
| 60 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 61 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 62 | hex |
| 63 | default 0x1600 |
| 64 | help |
| 65 | Increase this value if preram cbmem console is getting truncated |
| 66 | |
| 67 | config CPU_ADDR_BITS |
| 68 | int |
| 69 | default 48 |
| 70 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 71 | config MMCONF_BASE_ADDRESS |
| 72 | hex |
| 73 | default 0xF8000000 |
| 74 | |
| 75 | config MMCONF_BUS_NUMBER |
| 76 | int |
| 77 | default 64 |
| 78 | |
| 79 | config VGA_BIOS_ID |
| 80 | string |
Marshall Dawson | 0d441da | 2019-07-09 18:19:05 -0500 | [diff] [blame] | 81 | default "1002,15d8" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 82 | help |
| 83 | The default VGA BIOS PCI vendor/device ID should be set to the |
| 84 | result of the map_oprom_vendev() function in northbridge.c. |
| 85 | |
| 86 | config VGA_BIOS_FILE |
| 87 | string |
Marshall Dawson | 0d441da | 2019-07-09 18:19:05 -0500 | [diff] [blame] | 88 | default "3rdparty/blobs/soc/amd/picasso/PicassoGenericVbios.bin" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 89 | |
| 90 | config S3_VGA_ROM_RUN |
| 91 | bool |
| 92 | default n |
| 93 | |
| 94 | config HEAP_SIZE |
| 95 | hex |
| 96 | default 0xc0000 |
| 97 | |
| 98 | config EHCI_BAR |
| 99 | hex |
| 100 | default 0xfef00000 |
| 101 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 102 | config SERIRQ_CONTINUOUS_MODE |
| 103 | bool |
| 104 | default n |
| 105 | help |
| 106 | Set this option to y for serial IRQ in continuous mode. |
| 107 | Otherwise it is in quiet mode. |
| 108 | |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 109 | config PICASSO_ACPI_IO_BASE |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 110 | hex |
| 111 | default 0x400 |
| 112 | help |
| 113 | Base address for the ACPI registers. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 114 | |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 115 | config PICASSO_UART |
| 116 | bool "UART controller on Picasso" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 117 | default n |
| 118 | select DRIVERS_UART_8250MEM |
| 119 | select DRIVERS_UART_8250MEM_32 |
| 120 | select NO_UART_ON_SUPERIO |
| 121 | select UART_OVERRIDE_REFCLK |
| 122 | help |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 123 | There are four memory-mapped UARTs controllers in Picasso at: |
| 124 | 0: 0xfedc9000 |
| 125 | 1: 0xfedca000 |
| 126 | 2: 0xfedc3000 |
| 127 | 3: 0xfedcf000 |
| 128 | |
| 129 | choice PICASSO_UART_CLOCK_SOURCE |
| 130 | prompt "UART Frequency" |
| 131 | depends on PICASSO_UART |
| 132 | default PICASSO_UART_48MZ |
| 133 | |
| 134 | config PICASSO_UART_48MZ |
| 135 | bool "48 MHz clock" |
| 136 | help |
| 137 | Select this option for the most compatibility. |
| 138 | |
| 139 | config PICASSO_UART_1_8MZ |
| 140 | bool "1.8432 MHz clock" |
| 141 | help |
| 142 | Select this option if an old payload or Linux ttyS0 arguments |
| 143 | require it. |
| 144 | |
| 145 | endchoice |
| 146 | |
| 147 | config PICASSO_UART_LEGACY |
| 148 | bool "Decode legacy I/O range" |
| 149 | depends on PICASSO_UART |
| 150 | help |
| 151 | Assign I/O 3F8, 2F8, etc. to a Picasso UART. Only a single UART may |
| 152 | decode legacy addresses and this option enables the one used for the |
| 153 | console. A UART accessed with I/O does not allow all the features |
| 154 | of MMIO. The MMIO decode is still present when this option is used. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 155 | |
| 156 | config CONSOLE_UART_BASE_ADDRESS |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 157 | depends on CONSOLE_SERIAL && PICASSO_UART |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 158 | hex |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 159 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 160 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| 161 | default 0xfedc3000 if UART_FOR_CONSOLE = 2 |
| 162 | default 0xfedcf000 if UART_FOR_CONSOLE = 3 |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 163 | |
| 164 | config SMM_TSEG_SIZE |
| 165 | hex |
| 166 | default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER |
| 167 | default 0x0 |
| 168 | |
| 169 | config SMM_RESERVED_SIZE |
| 170 | hex |
| 171 | default 0x150000 |
| 172 | |
| 173 | config SMM_MODULE_STACK_SIZE |
| 174 | hex |
| 175 | default 0x800 |
| 176 | |
| 177 | config ACPI_CPU_STRING |
| 178 | string |
| 179 | default "\\_PR.P%03d" |
| 180 | |
| 181 | config ACPI_BERT |
| 182 | bool "Build ACPI BERT Table" |
| 183 | default y |
| 184 | depends on HAVE_ACPI_TABLES |
| 185 | help |
| 186 | Report Machine Check errors identified in POST to the OS in an |
| 187 | ACPI Boot Error Record Table. This option reserves an 8MB region |
| 188 | for building the error structures. |
| 189 | |
Marshall Dawson | 901cb9c | 2020-01-21 14:53:45 -0700 | [diff] [blame] | 190 | config ACPI_BERT_SIZE |
| 191 | hex |
| 192 | default 0x4000 |
| 193 | help |
| 194 | Specify the amount of DRAM reserved for gathering the data used to |
| 195 | generate the ACPI table. |
| 196 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 197 | config RO_REGION_ONLY |
| 198 | string |
| 199 | depends on CHROMEOS |
| 200 | default "apu/amdfw" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 201 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 202 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 203 | int |
Martin Roth | 4017de0 | 2019-12-16 23:21:05 -0700 | [diff] [blame] | 204 | default 150 |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 205 | |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 206 | config PICASSO_LPC_IOMUX |
| 207 | bool |
| 208 | help |
| 209 | Picasso's LPC bus signals are MUXed with some of the EMMC signals. |
| 210 | Select this option if LPC signals are required. |
| 211 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 212 | config MAINBOARD_POWER_RESTORE |
| 213 | def_bool n |
| 214 | help |
| 215 | This option determines what state to go to once power is restored |
| 216 | after having been lost in S0. Select this option to automatically |
| 217 | return to S0. Otherwise the system will remain in S5 once power |
| 218 | is restored. |
| 219 | |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 220 | config X86_RESET_VECTOR |
| 221 | hex |
| 222 | default 0x807fff0 |
| 223 | |
| 224 | config EARLYRAM_BSP_STACK_SIZE |
| 225 | hex |
| 226 | default 0x800 |
| 227 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 228 | menu "PSP Configuration Options" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 229 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 230 | config AMDFW_OUTSIDE_CBFS |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 231 | bool |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 232 | default n |
| 233 | help |
| 234 | The AMDFW (PSP) is typically locatable in cbfs. Select this |
| 235 | option to manually attach the generated amdfw.rom outside of |
| 236 | cbfs. The location is selected by the FWM position. |
| 237 | |
| 238 | config AMD_FWM_POSITION_INDEX |
| 239 | int "Firmware Directory Table location (0 to 5)" |
| 240 | range 0 5 |
| 241 | default 0 if BOARD_ROMSIZE_KB_512 |
| 242 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 243 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 244 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 245 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 246 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 247 | help |
| 248 | Typically this is calculated by the ROM size, but there may |
| 249 | be situations where you want to put the firmware directory |
| 250 | table in a different location. |
| 251 | 0: 512 KB - 0xFFFA0000 |
| 252 | 1: 1 MB - 0xFFF20000 |
| 253 | 2: 2 MB - 0xFFE20000 |
| 254 | 3: 4 MB - 0xFFC20000 |
| 255 | 4: 8 MB - 0xFF820000 |
| 256 | 5: 16 MB - 0xFF020000 |
| 257 | |
| 258 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 259 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 260 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 261 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 262 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 263 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 264 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 265 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 266 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 267 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 268 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 269 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 270 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 271 | config AMD_PUBKEY_FILE |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 272 | string |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 273 | default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 274 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 275 | config PSP_APCB_FILE |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 276 | string |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 277 | help |
Marshall Dawson | 4357a82 | 2019-09-25 11:07:56 -0600 | [diff] [blame] | 278 | The name of the AGESA Parameter Customization Block. This image is |
| 279 | instance ID 0 in the PSP's BIOS Directory Table. |
| 280 | |
| 281 | config PSP_APCB1_FILE |
| 282 | string |
| 283 | help |
| 284 | If specified, this image is instance ID 1 in the PSP's BIOS |
| 285 | Directory Table. |
| 286 | |
| 287 | config PSP_APCB2_FILE |
| 288 | string |
| 289 | help |
| 290 | If specified, this image is instance ID 2 in the PSP's BIOS |
| 291 | Directory Table. |
| 292 | |
| 293 | config PSP_APCB3_FILE |
| 294 | string |
| 295 | help |
| 296 | If specified, this image is instance ID 3 in the PSP's BIOS |
| 297 | Directory Table. |
| 298 | |
| 299 | config PSP_APCB4_FILE |
| 300 | string |
| 301 | help |
| 302 | If specified, this image is instance ID 4 in the PSP's BIOS |
| 303 | Directory Table. |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 304 | |
| 305 | config PSP_APOB_DESTINATION |
| 306 | hex |
| 307 | default 0x9f00000 |
| 308 | help |
| 309 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 310 | Block. |
| 311 | |
| 312 | config PSP_APOB_NV_ADDRESS |
| 313 | hex "Base address of APOB NV" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 314 | help |
| 315 | Location in flash where the PSP can find the S3 restore information. |
| 316 | Place this on a boundary that the flash device can erase. |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 317 | |
| 318 | config PSP_APOB_NV_SIZE |
| 319 | hex "Size of APOB NV to be reserved" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 320 | help |
| 321 | Size of the S3 restore information. Make this a multiple of the |
| 322 | size the flash device can erase. |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 323 | |
| 324 | config USE_PSPSCUREOS |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 325 | bool |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 326 | default y |
| 327 | help |
| 328 | Include the PspSecureOs and PspTrustlet binaries in the PSP build. |
| 329 | |
| 330 | If unsure, answer 'y' |
| 331 | |
| 332 | config PSP_LOAD_MP2_FW |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 333 | bool |
Furquan Shaikh | 47cdf43 | 2020-04-23 18:01:34 -0700 | [diff] [blame] | 334 | default n |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 335 | help |
| 336 | Include the MP2 firmwares and configuration into the PSP build. |
| 337 | |
Furquan Shaikh | 47cdf43 | 2020-04-23 18:01:34 -0700 | [diff] [blame] | 338 | If unsure, answer 'n' |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 339 | |
| 340 | config PSP_LOAD_S0I3_FW |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 341 | bool |
Furquan Shaikh | 30bc5b3 | 2020-04-23 18:02:53 -0700 | [diff] [blame] | 342 | default n |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 343 | help |
| 344 | Select this item to include the S0i3 file into the PSP build. |
| 345 | |
| 346 | config HAVE_PSP_WHITELIST_FILE |
| 347 | bool "Include a debug whitelist file in PSP build" |
| 348 | default n |
| 349 | help |
| 350 | Support secured unlock prior to reset using a whitelisted |
| 351 | number? This feature requires a signed whitelist image and |
| 352 | bootloader from AMD. |
| 353 | |
| 354 | If unsure, answer 'n' |
| 355 | |
| 356 | config PSP_WHITELIST_FILE |
| 357 | string "Debug whitelist file name" |
| 358 | depends on HAVE_PSP_WHITELIST_FILE |
| 359 | default "3rdparty/blobs/soc/amd/picasso/PSP/wtl-rvn.sbin" |
| 360 | |
Furquan Shaikh | 577db02 | 2020-04-24 15:52:04 -0700 | [diff] [blame] | 361 | config PSP_UNLOCK_SECURE_DEBUG |
| 362 | bool "Unlock secure debug" |
| 363 | default n |
| 364 | help |
| 365 | Select this item to enable secure debug options in PSP. |
| 366 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 367 | endmenu |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 368 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 369 | endif # SOC_AMD_PICASSO |