Felix Held | 4a8cd72 | 2020-04-18 22:26:39 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 2 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 3 | config SOC_AMD_PICASSO |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 4 | bool |
| 5 | help |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 6 | AMD Picasso support |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 7 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 8 | if SOC_AMD_PICASSO |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 9 | |
| 10 | config CPU_SPECIFIC_OPTIONS |
| 11 | def_bool y |
| 12 | select ARCH_BOOTBLOCK_X86_32 |
| 13 | select ARCH_VERSTAGE_X86_32 |
| 14 | select ARCH_ROMSTAGE_X86_32 |
| 15 | select ARCH_RAMSTAGE_X86_32 |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 16 | select RESET_VECTOR_IN_RAM |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 17 | select X86_AMD_FIXED_MTRRS |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 18 | select X86_AMD_INIT_SIPI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 19 | select ACPI_AMD_HARDWARE_SLEEP_VALUES |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 20 | select DRIVERS_I2C_DESIGNWARE |
| 21 | select GENERIC_GPIO_LIB |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 22 | select IOAPIC |
Furquan Shaikh | 0eabe13 | 2020-04-28 21:57:07 -0700 | [diff] [blame] | 23 | select HAVE_EM100_SUPPORT |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 24 | select HAVE_USBDEBUG_OPTIONS |
Marshall Dawson | 80d0b01 | 2019-06-19 12:29:23 -0600 | [diff] [blame] | 25 | select TSC_MONOTONIC_TIMER |
Richard Spiegel | 65562cd65 | 2019-08-21 10:27:05 -0700 | [diff] [blame] | 26 | select SOC_AMD_COMMON_BLOCK_SPI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 27 | select TSC_SYNC_LFENCE |
Marshall Dawson | 80d0b01 | 2019-06-19 12:29:23 -0600 | [diff] [blame] | 28 | select UDELAY_TSC |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 29 | select SOC_AMD_COMMON |
| 30 | select SOC_AMD_COMMON_BLOCK |
Furquan Shaikh | 702cf30 | 2020-05-09 18:30:51 -0700 | [diff] [blame] | 31 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 32 | select SOC_AMD_COMMON_BLOCK_IOMMU |
| 33 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
| 34 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
| 35 | select SOC_AMD_COMMON_BLOCK_ACPI |
Furquan Shaikh | 9e1a49c | 2020-04-23 14:01:12 -0700 | [diff] [blame] | 36 | select SOC_AMD_COMMON_BLOCK_GRAPHICS |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 37 | select SOC_AMD_COMMON_BLOCK_LPC |
| 38 | select SOC_AMD_COMMON_BLOCK_PCI |
| 39 | select SOC_AMD_COMMON_BLOCK_HDA |
| 40 | select SOC_AMD_COMMON_BLOCK_SATA |
Aaron Durbin | 3d2e18a | 2020-01-28 11:20:05 -0700 | [diff] [blame] | 41 | select SOC_AMD_COMMON_BLOCK_SMBUS |
Marshall Dawson | 5a73fc3 | 2020-01-24 09:42:57 -0700 | [diff] [blame] | 42 | select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
Aaron Durbin | 1d0b99b | 2020-04-11 11:58:57 -0600 | [diff] [blame] | 43 | select PROVIDES_ROM_SHARING |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 44 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
| 45 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 46 | select PARALLEL_MP |
| 47 | select PARALLEL_MP_AP_WORK |
| 48 | select HAVE_SMI_HANDLER |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 49 | select SSE2 |
| 50 | select RTC |
Marshall Dawson | 00a2208 | 2020-01-20 23:05:31 -0700 | [diff] [blame] | 51 | select PLATFORM_USES_FSP2_0 |
Furquan Shaikh | c3063c5 | 2020-05-28 11:58:20 -0700 | [diff] [blame] | 52 | select FSP_COMPRESS_FSP_M_LZMA |
| 53 | select FSP_COMPRESS_FSP_S_LZMA |
Marshall Dawson | 00a2208 | 2020-01-20 23:05:31 -0700 | [diff] [blame] | 54 | select FSP_USES_CB_STACK |
| 55 | select UDK_2017_BINDING |
| 56 | select HAVE_CF9_RESET |
Zheng Bao | 6ba591b | 2020-06-09 09:47:06 +0800 | [diff] [blame] | 57 | select SUPPORT_CPU_UCODE_IN_CBFS |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 58 | |
Furquan Shaikh | 3b03206 | 2020-06-10 11:52:49 -0700 | [diff] [blame] | 59 | config MEMLAYOUT_LD_FILE |
| 60 | string |
| 61 | default "src/soc/amd/picasso/memlayout.ld" |
| 62 | |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame^] | 63 | config EARLY_RESERVED_DRAM_BASE |
| 64 | hex |
| 65 | default 0x2000000 |
| 66 | help |
| 67 | This variable defines the base address of the DRAM which is reserved |
| 68 | for usage by coreboot in early stages (i.e. before ramstage is up). |
| 69 | This memory gets reserved in BIOS tables to ensure that the OS does |
| 70 | not use it, thus preventing corruption of OS memory in case of S3 |
| 71 | resume. |
| 72 | |
| 73 | config EARLYRAM_BSP_STACK_SIZE |
| 74 | hex |
| 75 | default 0x1000 |
| 76 | |
| 77 | config PSP_APOB_DRAM_ADDRESS |
| 78 | hex |
| 79 | default 0x2001000 |
| 80 | help |
| 81 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 82 | Block. |
| 83 | |
| 84 | config PSP_SHAREDMEM_BASE |
| 85 | hex |
| 86 | default 0x2011000 if VBOOT |
| 87 | default 0x0 |
| 88 | help |
| 89 | This variable defines the base address in DRAM memory where PSP copies |
| 90 | vboot workbuf to. This is used in linker script to have a static |
| 91 | allocation for the buffer as well as for adding relevant entries in |
| 92 | BIOS directory table for the PSP. |
| 93 | |
| 94 | config PSP_SHAREDMEM_SIZE |
| 95 | hex |
| 96 | default 0x8000 if VBOOT |
| 97 | default 0x0 |
| 98 | help |
| 99 | Sets the maximum size for the PSP to pass the vboot workbuf and |
| 100 | any logs or timestamps back to coreboot. This will be copied |
| 101 | into main memory by the PSP and will be available when the x86 is |
| 102 | started. The workbuf's base depends on the address of the reset |
| 103 | vector. |
| 104 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 105 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 106 | hex |
| 107 | default 0x1600 |
| 108 | help |
| 109 | Increase this value if preram cbmem console is getting truncated |
| 110 | |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame^] | 111 | config BOOTBLOCK_ADDR |
| 112 | hex |
| 113 | default 0x2030000 |
| 114 | help |
| 115 | Sets the address in DRAM where bootblock should be loaded. |
| 116 | |
| 117 | config C_ENV_BOOTBLOCK_SIZE |
| 118 | hex |
| 119 | default 0x10000 |
| 120 | help |
| 121 | Sets the size of the bootblock stage that should be loaded in DRAM. |
| 122 | This variable controls the DRAM allocation size in linker script |
| 123 | for bootblock stage. |
| 124 | |
| 125 | config X86_RESET_VECTOR |
| 126 | hex |
| 127 | depends on ARCH_X86 |
| 128 | default 0x203fff0 |
| 129 | help |
| 130 | Sets the reset vector within bootblock where x86 starts execution. |
| 131 | Reset vector is supposed to live at offset -0x10 from end of |
| 132 | bootblock i.e. BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10. |
| 133 | |
| 134 | config ROMSTAGE_ADDR |
| 135 | hex |
| 136 | default 0x2040000 |
| 137 | help |
| 138 | Sets the address in DRAM where romstage should be loaded. |
| 139 | |
| 140 | config ROMSTAGE_SIZE |
| 141 | hex |
| 142 | default 0x80000 |
| 143 | help |
| 144 | Sets the size of DRAM allocation for romstage in linker script. |
| 145 | |
| 146 | config FSP_M_ADDR |
| 147 | hex |
| 148 | default 0x20C0000 |
| 149 | help |
| 150 | Sets the address in DRAM where FSP-M should be loaded. cbfstool |
| 151 | performs relocation of FSP-M to this address. |
| 152 | |
| 153 | config FSP_M_SIZE |
| 154 | hex |
| 155 | default 0x80000 |
| 156 | help |
| 157 | Sets the size of DRAM allocation for FSP-M in linker script. |
| 158 | |
| 159 | config VERSTAGE_ADDR |
| 160 | hex |
| 161 | depends on VBOOT_SEPARATE_VERSTAGE |
| 162 | default 0x2140000 |
| 163 | help |
| 164 | Sets the address in DRAM where verstage should be loaded if running |
| 165 | as a separate stage on x86. |
| 166 | |
| 167 | config VERSTAGE_SIZE |
| 168 | hex |
| 169 | depends on VBOOT_SEPARATE_VERSTAGE |
| 170 | default 0x80000 |
| 171 | help |
| 172 | Sets the size of DRAM allocation for verstage in linker script if |
| 173 | running as a separate stage on x86. |
| 174 | |
| 175 | config RAMBASE |
| 176 | hex |
| 177 | default 0x10000000 |
| 178 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 179 | config CPU_ADDR_BITS |
| 180 | int |
| 181 | default 48 |
| 182 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 183 | config MMCONF_BASE_ADDRESS |
| 184 | hex |
| 185 | default 0xF8000000 |
| 186 | |
| 187 | config MMCONF_BUS_NUMBER |
| 188 | int |
| 189 | default 64 |
| 190 | |
Raul E Rangel | 5f52c0e | 2020-05-13 13:22:48 -0600 | [diff] [blame] | 191 | config VERSTAGE_ADDR |
| 192 | hex |
| 193 | default 0x4000000 |
| 194 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 195 | config VGA_BIOS_ID |
| 196 | string |
Marshall Dawson | 0d441da | 2019-07-09 18:19:05 -0500 | [diff] [blame] | 197 | default "1002,15d8" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 198 | help |
| 199 | The default VGA BIOS PCI vendor/device ID should be set to the |
| 200 | result of the map_oprom_vendev() function in northbridge.c. |
| 201 | |
| 202 | config VGA_BIOS_FILE |
| 203 | string |
Raul E Rangel | f39dab1 | 2020-05-13 16:46:57 -0600 | [diff] [blame] | 204 | default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 205 | |
| 206 | config S3_VGA_ROM_RUN |
| 207 | bool |
| 208 | default n |
| 209 | |
| 210 | config HEAP_SIZE |
| 211 | hex |
| 212 | default 0xc0000 |
| 213 | |
| 214 | config EHCI_BAR |
| 215 | hex |
| 216 | default 0xfef00000 |
| 217 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 218 | config SERIRQ_CONTINUOUS_MODE |
| 219 | bool |
| 220 | default n |
| 221 | help |
| 222 | Set this option to y for serial IRQ in continuous mode. |
| 223 | Otherwise it is in quiet mode. |
| 224 | |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 225 | config PICASSO_ACPI_IO_BASE |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 226 | hex |
| 227 | default 0x400 |
| 228 | help |
| 229 | Base address for the ACPI registers. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 230 | |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 231 | config PICASSO_UART |
| 232 | bool "UART controller on Picasso" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 233 | default n |
| 234 | select DRIVERS_UART_8250MEM |
| 235 | select DRIVERS_UART_8250MEM_32 |
| 236 | select NO_UART_ON_SUPERIO |
| 237 | select UART_OVERRIDE_REFCLK |
| 238 | help |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 239 | There are four memory-mapped UARTs controllers in Picasso at: |
| 240 | 0: 0xfedc9000 |
| 241 | 1: 0xfedca000 |
| 242 | 2: 0xfedc3000 |
| 243 | 3: 0xfedcf000 |
| 244 | |
| 245 | choice PICASSO_UART_CLOCK_SOURCE |
| 246 | prompt "UART Frequency" |
| 247 | depends on PICASSO_UART |
| 248 | default PICASSO_UART_48MZ |
| 249 | |
| 250 | config PICASSO_UART_48MZ |
| 251 | bool "48 MHz clock" |
| 252 | help |
| 253 | Select this option for the most compatibility. |
| 254 | |
| 255 | config PICASSO_UART_1_8MZ |
| 256 | bool "1.8432 MHz clock" |
| 257 | help |
| 258 | Select this option if an old payload or Linux ttyS0 arguments |
| 259 | require it. |
| 260 | |
| 261 | endchoice |
| 262 | |
| 263 | config PICASSO_UART_LEGACY |
| 264 | bool "Decode legacy I/O range" |
| 265 | depends on PICASSO_UART |
| 266 | help |
| 267 | Assign I/O 3F8, 2F8, etc. to a Picasso UART. Only a single UART may |
| 268 | decode legacy addresses and this option enables the one used for the |
| 269 | console. A UART accessed with I/O does not allow all the features |
| 270 | of MMIO. The MMIO decode is still present when this option is used. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 271 | |
| 272 | config CONSOLE_UART_BASE_ADDRESS |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 273 | depends on CONSOLE_SERIAL && PICASSO_UART |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 274 | hex |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 275 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 276 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| 277 | default 0xfedc3000 if UART_FOR_CONSOLE = 2 |
| 278 | default 0xfedcf000 if UART_FOR_CONSOLE = 3 |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 279 | |
| 280 | config SMM_TSEG_SIZE |
| 281 | hex |
| 282 | default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER |
| 283 | default 0x0 |
| 284 | |
| 285 | config SMM_RESERVED_SIZE |
| 286 | hex |
| 287 | default 0x150000 |
| 288 | |
| 289 | config SMM_MODULE_STACK_SIZE |
| 290 | hex |
| 291 | default 0x800 |
| 292 | |
| 293 | config ACPI_CPU_STRING |
| 294 | string |
Marshall Dawson | 879eba5 | 2019-11-22 17:52:39 -0700 | [diff] [blame] | 295 | default "\\_PR.C%03d" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 296 | |
| 297 | config ACPI_BERT |
| 298 | bool "Build ACPI BERT Table" |
| 299 | default y |
| 300 | depends on HAVE_ACPI_TABLES |
| 301 | help |
| 302 | Report Machine Check errors identified in POST to the OS in an |
| 303 | ACPI Boot Error Record Table. This option reserves an 8MB region |
| 304 | for building the error structures. |
| 305 | |
Marshall Dawson | 901cb9c | 2020-01-21 14:53:45 -0700 | [diff] [blame] | 306 | config ACPI_BERT_SIZE |
| 307 | hex |
| 308 | default 0x4000 |
| 309 | help |
| 310 | Specify the amount of DRAM reserved for gathering the data used to |
| 311 | generate the ACPI table. |
| 312 | |
Furquan Shaikh | 40a3888 | 2020-05-01 10:43:48 -0700 | [diff] [blame] | 313 | config CHROMEOS |
| 314 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 315 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 316 | config RO_REGION_ONLY |
| 317 | string |
| 318 | depends on CHROMEOS |
| 319 | default "apu/amdfw" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 320 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 321 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 322 | int |
Martin Roth | 4017de0 | 2019-12-16 23:21:05 -0700 | [diff] [blame] | 323 | default 150 |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 324 | |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 325 | config PICASSO_LPC_IOMUX |
| 326 | bool |
| 327 | help |
| 328 | Picasso's LPC bus signals are MUXed with some of the EMMC signals. |
| 329 | Select this option if LPC signals are required. |
| 330 | |
Aaron Durbin | 1d0b99b | 2020-04-11 11:58:57 -0600 | [diff] [blame] | 331 | config DISABLE_SPI_FLASH_ROM_SHARING |
| 332 | def_bool n |
| 333 | help |
| 334 | Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin |
| 335 | which indicates a board level ROM transaction request. This |
| 336 | removes arbitration with board and assumes the chipset controls |
| 337 | the SPI flash bus entirely. |
| 338 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 339 | config MAINBOARD_POWER_RESTORE |
| 340 | def_bool n |
| 341 | help |
| 342 | This option determines what state to go to once power is restored |
| 343 | after having been lost in S0. Select this option to automatically |
| 344 | return to S0. Otherwise the system will remain in S5 once power |
| 345 | is restored. |
| 346 | |
Marshall Dawson | 00a2208 | 2020-01-20 23:05:31 -0700 | [diff] [blame] | 347 | config FSP_TEMP_RAM_SIZE |
| 348 | hex |
| 349 | depends on FSP_USES_CB_STACK |
| 350 | default 0x40000 |
| 351 | help |
| 352 | The amount of coreboot-allocated heap and stack usage by the FSP. |
| 353 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 354 | menu "PSP Configuration Options" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 355 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 356 | config AMDFW_OUTSIDE_CBFS |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 357 | bool |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 358 | default n |
| 359 | help |
| 360 | The AMDFW (PSP) is typically locatable in cbfs. Select this |
| 361 | option to manually attach the generated amdfw.rom outside of |
| 362 | cbfs. The location is selected by the FWM position. |
| 363 | |
| 364 | config AMD_FWM_POSITION_INDEX |
| 365 | int "Firmware Directory Table location (0 to 5)" |
| 366 | range 0 5 |
| 367 | default 0 if BOARD_ROMSIZE_KB_512 |
| 368 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 369 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 370 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 371 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 372 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 373 | help |
| 374 | Typically this is calculated by the ROM size, but there may |
| 375 | be situations where you want to put the firmware directory |
| 376 | table in a different location. |
| 377 | 0: 512 KB - 0xFFFA0000 |
| 378 | 1: 1 MB - 0xFFF20000 |
| 379 | 2: 2 MB - 0xFFE20000 |
| 380 | 3: 4 MB - 0xFFC20000 |
| 381 | 4: 8 MB - 0xFF820000 |
| 382 | 5: 16 MB - 0xFF020000 |
| 383 | |
| 384 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 385 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 386 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 387 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 388 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 389 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 390 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 391 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 392 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 393 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 394 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 395 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 396 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 397 | config AMD_PUBKEY_FILE |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 398 | string |
Raul E Rangel | f39dab1 | 2020-05-13 16:46:57 -0600 | [diff] [blame] | 399 | default "3rdparty/amd_blobs/picasso/PSP/AmdPubKeyRV.bin" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 400 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 401 | config USE_PSPSCUREOS |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 402 | bool |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 403 | default y |
| 404 | help |
| 405 | Include the PspSecureOs and PspTrustlet binaries in the PSP build. |
| 406 | |
| 407 | If unsure, answer 'y' |
| 408 | |
| 409 | config PSP_LOAD_MP2_FW |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 410 | bool |
Furquan Shaikh | 47cdf43 | 2020-04-23 18:01:34 -0700 | [diff] [blame] | 411 | default n |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 412 | help |
| 413 | Include the MP2 firmwares and configuration into the PSP build. |
| 414 | |
Furquan Shaikh | 47cdf43 | 2020-04-23 18:01:34 -0700 | [diff] [blame] | 415 | If unsure, answer 'n' |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 416 | |
| 417 | config PSP_LOAD_S0I3_FW |
Furquan Shaikh | d4ef9a4 | 2020-04-24 11:49:32 -0700 | [diff] [blame] | 418 | bool |
Furquan Shaikh | 30bc5b3 | 2020-04-23 18:02:53 -0700 | [diff] [blame] | 419 | default n |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 420 | help |
| 421 | Select this item to include the S0i3 file into the PSP build. |
| 422 | |
| 423 | config HAVE_PSP_WHITELIST_FILE |
| 424 | bool "Include a debug whitelist file in PSP build" |
| 425 | default n |
| 426 | help |
| 427 | Support secured unlock prior to reset using a whitelisted |
| 428 | number? This feature requires a signed whitelist image and |
| 429 | bootloader from AMD. |
| 430 | |
| 431 | If unsure, answer 'n' |
| 432 | |
| 433 | config PSP_WHITELIST_FILE |
Martin Roth | 49b09a0 | 2020-02-20 13:54:06 -0700 | [diff] [blame] | 434 | string "Debug whitelist file path" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 435 | depends on HAVE_PSP_WHITELIST_FILE |
Raul E Rangel | f39dab1 | 2020-05-13 16:46:57 -0600 | [diff] [blame] | 436 | default "3rdparty/amd_blobs/picasso/PSP/wtl-rvn.sbin" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 437 | |
Martin Roth | 49b09a0 | 2020-02-20 13:54:06 -0700 | [diff] [blame] | 438 | config PSP_BOOTLOADER_FILE |
| 439 | string "Specify the PSP Bootloader file path" |
| 440 | default "3rdparty/amd_blobs/picasso/PSP/PspBootLoader_WL_RV.sbin" if HAVE_PSP_WHITELIST_FILE |
| 441 | default "3rdparty/amd_blobs/picasso/PSP/PspBootLoader_prod_RV.sbin" |
| 442 | help |
| 443 | Supply the name of the PSP bootloader file. |
| 444 | |
| 445 | Note that this option may conflict with the whitelist file if a |
| 446 | different PSP bootloader binary is specified. |
| 447 | |
Furquan Shaikh | 577db02 | 2020-04-24 15:52:04 -0700 | [diff] [blame] | 448 | config PSP_UNLOCK_SECURE_DEBUG |
| 449 | bool "Unlock secure debug" |
| 450 | default n |
| 451 | help |
| 452 | Select this item to enable secure debug options in PSP. |
| 453 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 454 | endmenu |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 455 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 456 | endif # SOC_AMD_PICASSO |