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Patrick Georgi0588d192009-08-12 15:00:51 +00001##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00002## This file is part of the coreboot project.
Patrick Georgi0588d192009-08-12 15:00:51 +00003##
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -05004## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
Stefan Reinauer16f515a2010-01-20 18:44:30 +00005## Copyright (C) 2009-2010 coresystems GmbH
Patrick Georgi0588d192009-08-12 15:00:51 +00006##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00007## This program is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; version 2 of the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +010018## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Patrick Georgi0588d192009-08-12 15:00:51 +000019##
20
Uwe Hermannad8c95f2012-04-12 22:00:03 +020021mainmenu "coreboot configuration"
Patrick Georgi0588d192009-08-12 15:00:51 +000022
Uwe Hermannc04be932009-10-05 13:55:28 +000023menu "General setup"
24
Uwe Hermanna29ad5c2009-10-18 18:35:50 +000025config EXPERT
26 bool "Expert mode"
27 help
28 This allows you to select certain advanced configuration options.
29
30 Warning: Only enable this option if you really know what you are
31 doing! You have been warned!
32
Uwe Hermannc04be932009-10-05 13:55:28 +000033config LOCALVERSION
Uwe Hermann168b11b2009-10-07 16:15:40 +000034 string "Local version string"
Uwe Hermannc04be932009-10-05 13:55:28 +000035 help
36 Append an extra string to the end of the coreboot version.
37
Uwe Hermann168b11b2009-10-07 16:15:40 +000038 This can be useful if, for instance, you want to append the
39 respective board's hostname or some other identifying string to
40 the coreboot version number, so that you can easily distinguish
41 boot logs of different boards from each other.
42
Patrick Georgi4b8a2412010-02-09 19:35:16 +000043config CBFS_PREFIX
44 string "CBFS prefix to use"
45 default "fallback"
46 help
47 Select the prefix to all files put into the image. It's "fallback"
48 by default, "normal" is a common alternative.
49
Vadim Bendeburyadcb0952014-05-01 12:23:09 -070050config COMMON_CBFS_SPI_WRAPPER
51 bool
52 default n
53 depends on SPI_FLASH
54 depends on !ARCH_X86
55 help
56 Use common wrapper to interface CBFS to SPI bootrom.
57
Vadim Bendebury6bfabce2014-12-25 15:07:22 -080058config MULTIPLE_CBFS_INSTANCES
59 bool "Multiple CBFS instances in the bootrom"
60 default n
61 depends on !ARCH_X86
62 help
63 Account for the firmware image containing more than one CBFS
64 instance. Locations of instances are known at build time and are
65 communicated between coreboot stages to make sure the next stage is
66 loaded from the appropriate instance.
67
Patrick Georgi23d89cc2010-03-16 01:17:19 +000068choice
Uwe Hermannad8c95f2012-04-12 22:00:03 +020069 prompt "Compiler to use"
Patrick Georgi23d89cc2010-03-16 01:17:19 +000070 default COMPILER_GCC
71 help
72 This option allows you to select the compiler used for building
73 coreboot.
74
75config COMPILER_GCC
76 bool "GCC"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020077 help
78 Use the GNU Compiler Collection (GCC) to build coreboot.
79
80 For details see http://gcc.gnu.org.
81
Patrick Georgi23d89cc2010-03-16 01:17:19 +000082config COMPILER_LLVM_CLANG
83 bool "LLVM/clang"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020084 help
85 Use LLVM/clang to build coreboot.
86
87 For details see http://clang.llvm.org.
88
Patrick Georgi23d89cc2010-03-16 01:17:19 +000089endchoice
90
Patrick Georgi9b0de712013-12-29 18:45:23 +010091config ANY_TOOLCHAIN
92 bool "Allow building with any toolchain"
93 default n
94 depends on COMPILER_GCC
95 help
96 Many toolchains break when building coreboot since it uses quite
97 unusual linker features. Unless developers explicitely request it,
98 we'll have to assume that they use their distro compiler by mistake.
99 Make sure that using patched compilers is a conscious decision.
100
Patrick Georgi516a2a72010-03-25 21:45:25 +0000101config CCACHE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200102 bool "Use ccache to speed up (re)compilation"
Patrick Georgi516a2a72010-03-25 21:45:25 +0000103 default n
104 help
105 Enables the use of ccache for faster builds.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200106
107 Requires the ccache utility in your system $PATH.
108
109 For details see https://ccache.samba.org.
Patrick Georgi516a2a72010-03-25 21:45:25 +0000110
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000111config SCONFIG_GENPARSER
112 bool "Generate SCONFIG parser using flex and bison"
113 default n
114 depends on EXPERT
115 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200116 Enable this option if you are working on the sconfig device tree
117 parser and made changes to sconfig.l and sconfig.y.
118
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000119 Otherwise, say N.
120
Joe Korty6d772522010-05-19 18:41:15 +0000121config USE_OPTION_TABLE
122 bool "Use CMOS for configuration values"
123 default n
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000124 depends on HAVE_OPTION_TABLE
Joe Korty6d772522010-05-19 18:41:15 +0000125 help
126 Enable this option if coreboot shall read options from the "CMOS"
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200127 NVRAM instead of using hard-coded values.
Joe Korty6d772522010-05-19 18:41:15 +0000128
Timothy Pearsonf20c6e82015-02-14 16:15:31 -0600129config STATIC_OPTION_TABLE
130 bool "Load default configuration values into CMOS on each boot"
131 default n
132 depends on USE_OPTION_TABLE
133 help
134 Enable this option to reset "CMOS" NVRAM values to default on
135 every boot. Use this if you want the NVRAM configuration to
136 never be modified from its default values.
137
Julius Wernercdf92ea2014-12-09 12:18:00 -0800138config UNCOMPRESSED_RAMSTAGE
139 bool
140 default n
141
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000142config COMPRESS_RAMSTAGE
143 bool "Compress ramstage with LZMA"
Julius Wernercdf92ea2014-12-09 12:18:00 -0800144 default y if !UNCOMPRESSED_RAMSTAGE
145 default n
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000146 help
147 Compress ramstage to save memory in the flash image. Note
148 that decompression might slow down booting if the boot flash
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200149 is connected through a slow link (i.e. SPI).
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000150
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200151config INCLUDE_CONFIG_FILE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200152 bool "Include the coreboot .config file into the ROM image"
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200153 default y
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200154 help
155 Include the .config file that was used to compile coreboot
156 in the (CBFS) ROM image. This is useful if you want to know which
157 options were used to build a specific coreboot.rom image.
158
Daniele Forsi53847a22014-07-22 18:00:56 +0200159 Saying Y here will increase the image size by 2-3KB.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200160
161 You can use the following command to easily list the options:
162
163 grep -a CONFIG_ coreboot.rom
164
165 Alternatively, you can also use cbfstool to print the image
166 contents (including the raw 'config' item we're looking for).
167
168 Example:
169
170 $ cbfstool coreboot.rom print
171 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
172 offset 0x0
173 Alignment: 64 bytes
Steve Goodrichf0269122012-05-18 11:18:47 -0600174
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200175 Name Offset Type Size
176 cmos_layout.bin 0x0 cmos layout 1159
177 fallback/romstage 0x4c0 stage 339756
Daniele Forsi53847a22014-07-22 18:00:56 +0200178 fallback/ramstage 0x53440 stage 186664
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200179 fallback/payload 0x80dc0 payload 51526
180 config 0x8d740 raw 3324
181 (empty) 0x8e480 null 3610440
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200182
Kyösti Mälkkif8bf5a12013-10-11 22:08:02 +0300183config EARLY_CBMEM_INIT
Kyösti Mälkki3bf38542014-12-18 22:22:04 +0200184 def_bool !LATE_CBMEM_INIT
185
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700186config COLLECT_TIMESTAMPS
187 bool "Create a table of timestamps collected during boot"
Kyösti Mälkki26447932013-10-11 21:14:59 +0300188 default n
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700189 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200190 Make coreboot create a table of timer-ID/timer-value pairs to
191 allow measuring time spent at different phases of the boot process.
192
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200193config USE_BLOBS
194 bool "Allow use of binary-only repository"
195 default n
196 help
197 This draws in the blobs repository, which contains binary files that
198 might be required for some chipsets or boards.
199 This flag ensures that a "Free" option remains available for users.
200
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800201config COVERAGE
202 bool "Code coverage support"
203 depends on COMPILER_GCC
204 default n
205 help
206 Add code coverage support for coreboot. This will store code
207 coverage information in CBMEM for extraction from user space.
208 If unsure, say N.
209
Stefan Reinauer58470e32014-10-17 13:08:36 +0200210config RELOCATABLE_MODULES
211 bool "Relocatable Modules"
212 default n
213 help
214 If RELOCATABLE_MODULES is selected then support is enabled for
215 building relocatable modules in the RAM stage. Those modules can be
216 loaded anywhere and all the relocations are handled automatically.
217
218config RELOCATABLE_RAMSTAGE
Kyösti Mälkkiae98e832014-11-28 11:24:19 +0200219 depends on (RELOCATABLE_MODULES && EARLY_CBMEM_INIT)
Stefan Reinauer58470e32014-10-17 13:08:36 +0200220 bool "Build the ramstage to be relocatable in 32-bit address space."
221 default n
222 help
223 The reloctable ramstage support allows for the ramstage to be built
224 as a relocatable module. The stage loader can identify a place
225 out of the OS way so that copying memory is unnecessary during an S3
226 wake. When selecting this option the romstage is responsible for
227 determing a stack location to use for loading the ramstage.
228
229config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
230 depends on RELOCATABLE_RAMSTAGE
231 bool "Cache the relocated ramstage outside of cbmem."
232 default n
233 help
234 The relocated ramstage is saved in an area specified by the
235 by the board and/or chipset.
236
237choice
238 prompt "Bootblock behaviour"
239 default BOOTBLOCK_SIMPLE
240
241config BOOTBLOCK_SIMPLE
242 bool "Always load fallback"
243
244config BOOTBLOCK_NORMAL
245 bool "Switch to normal if CMOS says so"
246
247endchoice
248
249config BOOTBLOCK_SOURCE
250 string
251 default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
252 default "bootblock_normal.c" if BOOTBLOCK_NORMAL
253
Timothy Pearson44724082015-03-16 11:47:45 -0500254config SKIP_MAX_REBOOT_CNT_CLEAR
255 bool "Do not clear reboot count after successful boot"
256 default n
257 depends on EXPERT
258 help
259 Do not clear the reboot count immediately after successful boot.
260 Set to allow the payload to control normal/fallback image recovery.
261
Stefan Reinauer58470e32014-10-17 13:08:36 +0200262config UPDATE_IMAGE
263 bool "Update existing coreboot.rom image"
264 default n
265 help
266 If this option is enabled, no new coreboot.rom file
267 is created. Instead it is expected that there already
268 is a suitable file for further processing.
269 The bootblock will not be modified.
270
Stefan Reinauerd06258c2015-03-26 16:29:00 -0700271config GENERIC_GPIO_LIB
272 bool
273 default n
274 help
275 If enabled, compile the generic GPIO library. A "generic" GPIO
276 implies configurability usually found on SoCs, particularly the
277 ability to control internal pull resistors.
278
279config BOARD_ID_AUTO
280 bool
281 default n
282 help
283 Mainboards that can read a board ID from the hardware straps
284 (ie. GPIO) select this configuration option.
285
286config BOARD_ID_MANUAL
287 bool "Add board ID file to CBFS"
288 default n
289 depends on !BOARD_ID_AUTO
290 help
291 If you want to maintain a board ID, but the hardware does not
292 have straps to automatically determine the ID, you can say Y
293 here and add a file named 'board_id' to CBFS. If you don't know
294 what this is about, say N.
295
296config BOARD_ID_STRING
297 string "Board ID"
298 default "(none)"
299 depends on BOARD_ID_MANUAL
300 help
301 This string is placed in the 'board_id' CBFS file for indicating
302 board type.
303
David Hendricks627b3bd2014-11-03 17:42:09 -0800304config RAM_CODE_SUPPORT
305 bool "Discover RAM configuration code and store it in coreboot table"
306 default n
307 help
308 If enabled, coreboot discovers RAM configuration (value obtained by
309 reading board straps) and stores it in coreboot table.
310
Uwe Hermannc04be932009-10-05 13:55:28 +0000311endmenu
312
Stefan Reinauera48ca842015-04-04 01:58:28 +0200313source "src/mainboard/Kconfig"
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000314
Stefan Reinauera48ca842015-04-04 01:58:28 +0200315source "src/arch/*/Kconfig"
Ronald G. Minnich78a16672012-11-29 16:28:21 -0800316
Stefan Reinauera48ca842015-04-04 01:58:28 +0200317source "src/vendorcode/*/Kconfig"
Peter Stuge4d77ed92014-02-07 03:58:24 +0100318
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200319config SYSTEM_TYPE_LAPTOP
320 default n
321 bool
322
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000323menu "Chipset"
324
325comment "CPU"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200326source "src/cpu/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000327comment "Northbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200328source "src/northbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000329comment "Southbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200330source "src/southbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000331comment "Super I/O"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200332source "src/superio/*/Kconfig"
Sven Schnelle7592e8b2011-01-27 11:43:03 +0000333comment "Embedded Controllers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200334source "src/ec/acpi/Kconfig"
335source "src/ec/*/*/Kconfig"
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500336comment "SoC"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200337source "src/soc/*/*/Kconfig"
Marc Jones78687972015-04-22 23:16:31 -0600338source "src/drivers/intel/fsp1_0/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000339
340endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000341
Stefan Reinauera48ca842015-04-04 01:58:28 +0200342source "src/device/Kconfig"
Stefan Reinauer95a63962012-11-13 17:00:01 -0800343
Rudolf Marekd9c25492010-05-16 15:31:53 +0000344menu "Generic Drivers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200345source "src/drivers/*/Kconfig"
Rudolf Marekd9c25492010-05-16 15:31:53 +0000346endmenu
347
Patrick Georgi0770f252015-04-22 13:28:21 +0200348config RTC
349 bool
350 default n
351
Stefan Reinauer7cb01e02013-08-29 16:05:02 -0700352config TPM
353 bool
354 default n
355 select LPC_TPM if ARCH_X86
Gabe Black51edd542013-09-30 23:00:33 -0700356 select I2C_TPM if ARCH_ARM
Furquan Shaikh2af76f42014-04-28 16:39:40 -0700357 select I2C_TPM if ARCH_ARM64
Stefan Reinauer7cb01e02013-08-29 16:05:02 -0700358 help
359 Enable this option to enable TPM support in coreboot.
360
361 If unsure, say N.
362
Kyösti Mälkkieaee6e22014-04-30 01:35:29 +0300363config RAMTOP
364 hex
365 default 0x200000
366 depends on ARCH_X86
367
Patrick Georgi0588d192009-08-12 15:00:51 +0000368config HEAP_SIZE
369 hex
Myles Watson04000f42009-10-16 19:12:49 +0000370 default 0x4000
Patrick Georgi0588d192009-08-12 15:00:51 +0000371
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700372config STACK_SIZE
373 hex
Julius Werner89be1542014-12-18 19:24:48 -0800374 default 0x0 if (ARCH_RAMSTAGE_ARM || ARCH_RAMSTAGE_MIPS)
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700375 default 0x1000
376
Patrick Georgi0588d192009-08-12 15:00:51 +0000377config MAX_CPUS
378 int
379 default 1
380
381config MMCONF_SUPPORT_DEFAULT
382 bool
383 default n
384
385config MMCONF_SUPPORT
386 bool
387 default n
388
Kyösti Mälkki5687fc92013-11-28 18:11:49 +0200389config BOOTMODE_STRAPS
390 bool
391 default n
392
Stefan Reinauera48ca842015-04-04 01:58:28 +0200393source "src/console/Kconfig"
Patrick Georgi0588d192009-08-12 15:00:51 +0000394
395config HAVE_ACPI_RESUME
396 bool
397 default n
398
Stefan Reinauerc4f1a772010-06-05 10:03:08 +0000399config HAVE_ACPI_SLIC
400 bool
401 default n
402
Patrick Georgi0588d192009-08-12 15:00:51 +0000403config HAVE_HARD_RESET
404 bool
Uwe Hermann748475b2009-10-09 11:47:21 +0000405 default n
Patrick Georgi37bdb872010-02-27 08:39:04 +0000406 help
407 This variable specifies whether a given board has a hard_reset
408 function, no matter if it's provided by board code or chipset code.
409
Aaron Durbina4217912013-04-29 22:31:51 -0500410config HAVE_MONOTONIC_TIMER
411 def_bool n
412 help
413 The board/chipset provides a monotonic timer.
414
Aaron Durbine5e36302014-09-25 10:05:15 -0500415config GENERIC_UDELAY
416 def_bool n
417 depends on HAVE_MONOTONIC_TIMER
418 help
419 The board/chipset uses a generic udelay function utilizing the
420 monotonic timer.
421
Aaron Durbin340ca912013-04-30 09:58:12 -0500422config TIMER_QUEUE
423 def_bool n
424 depends on HAVE_MONOTONIC_TIMER
425 help
Kyösti Mälkkiecd84242013-09-13 07:57:49 +0300426 Provide a timer queue for performing time-based callbacks.
Aaron Durbin340ca912013-04-30 09:58:12 -0500427
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500428config COOP_MULTITASKING
429 def_bool n
Aaron Durbin38c326d2013-05-06 12:22:23 -0500430 depends on TIMER_QUEUE && ARCH_X86
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500431 help
432 Cooperative multitasking allows callbacks to be multiplexed on the
433 main thread of ramstage. With this enabled it allows for multiple
434 execution paths to take place when they have udelay() calls within
435 their code.
436
437config NUM_THREADS
438 int
439 default 4
440 depends on COOP_MULTITASKING
441 help
442 How many execution threads to cooperatively multitask with.
443
Patrick Georgi0588d192009-08-12 15:00:51 +0000444config HAVE_OPTION_TABLE
445 bool
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000446 default n
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000447 help
448 This variable specifies whether a given board has a cmos.layout
449 file containing NVRAM/CMOS bit definitions.
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000450 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
Patrick Georgi0588d192009-08-12 15:00:51 +0000451
Patrick Georgi0588d192009-08-12 15:00:51 +0000452config PIRQ_ROUTE
453 bool
454 default n
455
456config HAVE_SMI_HANDLER
457 bool
458 default n
459
460config PCI_IO_CFG_EXT
461 bool
462 default n
463
464config IOAPIC
465 bool
466 default n
467
Stefan Reinauer5b635792012-08-16 14:05:42 -0700468config CBFS_SIZE
Julius Wernerf780c402014-11-10 13:11:50 -0800469 hex "Size of CBFS filesystem in ROM"
Stefan Reinauer5b635792012-08-16 14:05:42 -0700470 default ROM_SIZE
Julius Wernerf780c402014-11-10 13:11:50 -0800471 help
472 This is the part of the ROM actually managed by CBFS, located at the
473 end of the ROM (passed through cbfstool -o) on x86 and at at the start
474 of the ROM (passed through cbfstool -s) everywhere else. Defaults to
475 span the whole ROM but can be overwritten to make coreboot live
476 alongside other components (like ChromeOS's vboot/FMAP).
Stefan Reinauer5b635792012-08-16 14:05:42 -0700477
Kyösti Mälkki107f72e2014-01-06 11:06:26 +0200478config CACHE_ROM_SIZE_OVERRIDE
Stefan Reinauer5b635792012-08-16 14:05:42 -0700479 hex
Kyösti Mälkki107f72e2014-01-06 11:06:26 +0200480 default 0
Stefan Reinauer5b635792012-08-16 14:05:42 -0700481
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000482# TODO: Can probably be removed once all chipsets have kconfig options for it.
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000483config VIDEO_MB
484 int
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000485 default 0
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000486
Myles Watson45bb25f2009-09-22 18:49:08 +0000487config USE_WATCHDOG_ON_BOOT
488 bool
489 default n
490
491config VGA
492 bool
493 default n
494 help
495 Build board-specific VGA code.
496
497config GFXUMA
498 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000499 default n
Myles Watson45bb25f2009-09-22 18:49:08 +0000500 help
501 Enable Unified Memory Architecture for graphics.
502
Myles Watsonb8e20272009-10-15 13:35:47 +0000503config HAVE_ACPI_TABLES
504 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000505 help
506 This variable specifies whether a given board has ACPI table support.
507 It is usually set in mainboard/*/Kconfig.
Myles Watsonb8e20272009-10-15 13:35:47 +0000508
509config HAVE_MP_TABLE
510 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000511 help
512 This variable specifies whether a given board has MP table support.
513 It is usually set in mainboard/*/Kconfig.
514 Whether or not the MP table is actually generated by coreboot
515 is configurable by the user via GENERATE_MP_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000516
517config HAVE_PIRQ_TABLE
518 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000519 help
520 This variable specifies whether a given board has PIRQ table support.
521 It is usually set in mainboard/*/Kconfig.
522 Whether or not the PIRQ table is actually generated by coreboot
523 is configurable by the user via GENERATE_PIRQ_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000524
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -0500525config MAX_PIRQ_LINKS
526 int
527 default 4
528 help
529 This variable specifies the number of PIRQ interrupt links which are
530 routable. On most chipsets, this is 4, INTA through INTD. Some
531 chipsets offer more than four links, commonly up to INTH. They may
532 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
533 table specifies links greater than 4, pirq_route_irqs will not
534 function properly, unless this variable is correctly set.
535
Vladimir Serbinenko2d7bd8a2014-08-30 19:28:05 +0200536config PER_DEVICE_ACPI_TABLES
537 bool
538 default n
539
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200540config COMMON_FADT
541 bool
542 default n
543
Myles Watsond73c1b52009-10-26 15:14:07 +0000544#These Options are here to avoid "undefined" warnings.
545#The actual selection and help texts are in the following menu.
546
Uwe Hermann168b11b2009-10-07 16:15:40 +0000547menu "System tables"
Myles Watson45bb25f2009-09-22 18:49:08 +0000548
Myles Watsonb8e20272009-10-15 13:35:47 +0000549config GENERATE_MP_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800550 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
551 bool
552 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000553 help
554 Generate an MP table (conforming to the Intel MultiProcessor
555 specification 1.4) for this board.
556
557 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000558
Myles Watsonb8e20272009-10-15 13:35:47 +0000559config GENERATE_PIRQ_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800560 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
561 bool
562 default HAVE_PIRQ_TABLE
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000563 help
564 Generate a PIRQ table for this board.
565
566 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000567
Sven Schnelle164bcfd2011-08-14 20:56:34 +0200568config GENERATE_SMBIOS_TABLES
569 depends on ARCH_X86
570 bool "Generate SMBIOS tables"
571 default y
572 help
573 Generate SMBIOS tables for this board.
574
575 If unsure, say Y.
576
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200577config MAINBOARD_SERIAL_NUMBER
578 string "SMBIOS Serial Number"
579 depends on GENERATE_SMBIOS_TABLES
580 default "123456789"
581 help
582 The Serial Number to store in SMBIOS structures.
583
584config MAINBOARD_VERSION
585 string "SMBIOS Version Number"
586 depends on GENERATE_SMBIOS_TABLES
587 default "1.0"
588 help
589 The Version Number to store in SMBIOS structures.
590
591config MAINBOARD_SMBIOS_MANUFACTURER
592 string "SMBIOS Manufacturer"
593 depends on GENERATE_SMBIOS_TABLES
594 default MAINBOARD_VENDOR
595 help
596 Override the default Manufacturer stored in SMBIOS structures.
597
598config MAINBOARD_SMBIOS_PRODUCT_NAME
599 string "SMBIOS Product name"
600 depends on GENERATE_SMBIOS_TABLES
601 default MAINBOARD_PART_NUMBER
602 help
603 Override the default Product name stored in SMBIOS structures.
604
Myles Watson45bb25f2009-09-22 18:49:08 +0000605endmenu
606
Patrick Georgi0588d192009-08-12 15:00:51 +0000607menu "Payload"
608
Patrick Georgi0588d192009-08-12 15:00:51 +0000609choice
Uwe Hermann168b11b2009-10-07 16:15:40 +0000610 prompt "Add a payload"
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000611 default PAYLOAD_NONE if !ARCH_X86
612 default PAYLOAD_SEABIOS if ARCH_X86
Patrick Georgi0588d192009-08-12 15:00:51 +0000613
Uwe Hermann168b11b2009-10-07 16:15:40 +0000614config PAYLOAD_NONE
615 bool "None"
616 help
617 Select this option if you want to create an "empty" coreboot
618 ROM image for a certain mainboard, i.e. a coreboot ROM image
619 which does not yet contain a payload.
620
621 For such an image to be useful, you have to use 'cbfstool'
622 to add a payload to the ROM image later.
623
Patrick Georgi0588d192009-08-12 15:00:51 +0000624config PAYLOAD_ELF
Uwe Hermann168b11b2009-10-07 16:15:40 +0000625 bool "An ELF executable payload"
Patrick Georgi0588d192009-08-12 15:00:51 +0000626 help
627 Select this option if you have a payload image (an ELF file)
628 which coreboot should run as soon as the basic hardware
629 initialization is completed.
630
631 You will be able to specify the location and file name of the
632 payload image later.
Patrick Georgi0588d192009-08-12 15:00:51 +0000633
Patrick Georgi16ae95c2013-08-31 08:26:52 +0200634config PAYLOAD_LINUX
635 bool "A Linux payload"
636 help
637 Select this option if you have a Linux bzImage which coreboot
638 should run as soon as the basic hardware initialization
639 is completed.
640
641 You will be able to specify the location and file name of the
642 payload image later.
643
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000644config PAYLOAD_SEABIOS
645 bool "SeaBIOS"
646 depends on ARCH_X86
647 help
648 Select this option if you want to build a coreboot image
649 with a SeaBIOS payload. If you don't know what this is
650 about, just leave it enabled.
651
652 See http://coreboot.org/Payloads for more information.
653
Stefan Reinauere50952f2011-04-15 03:34:05 +0000654config PAYLOAD_FILO
655 bool "FILO"
656 help
657 Select this option if you want to build a coreboot image
658 with a FILO payload. If you don't know what this is
659 about, just leave it enabled.
660
661 See http://coreboot.org/Payloads for more information.
662
Vladimir Serbinenko113a3662013-11-14 12:10:08 +0100663config PAYLOAD_GRUB2
664 bool "GRUB2"
665 help
666 Select this option if you want to build a coreboot image
667 with a GRUB2 payload. If you don't know what this is
668 about, just leave it enabled.
669
670 See http://coreboot.org/Payloads for more information.
671
Stefan Reinauercc5b3442013-01-15 17:02:58 -0800672config PAYLOAD_TIANOCORE
673 bool "Tiano Core"
674 help
675 Select this option if you want to build a coreboot image
676 with a Tiano Core payload. If you don't know what this is
677 about, just leave it enabled.
678
679 See http://coreboot.org/Payloads for more information.
680
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000681endchoice
682
683choice
684 prompt "SeaBIOS version"
685 default SEABIOS_STABLE
686 depends on PAYLOAD_SEABIOS
687
688config SEABIOS_STABLE
Edward O'Callaghanaca67ed2014-09-13 20:43:45 +1000689 bool "1.7.5"
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000690 help
691 Stable SeaBIOS version
692config SEABIOS_MASTER
693 bool "master"
694 help
695 Newest SeaBIOS version
Daniele Forsi53847a22014-07-22 18:00:56 +0200696
Patrick Georgi0588d192009-08-12 15:00:51 +0000697endchoice
698
Peter Stugef0408582013-07-09 19:43:09 +0200699config SEABIOS_PS2_TIMEOUT
700 prompt "PS/2 keyboard controller initialization timeout (milliseconds)" if PAYLOAD_SEABIOS
Patrick Georgi1e44c3f2013-08-16 10:14:38 +0200701 default 0
Peter Stugef0408582013-07-09 19:43:09 +0200702 depends on EXPERT
703 int
704 help
705 Some PS/2 keyboard controllers don't respond to commands immediately
706 after powering on. This specifies how long SeaBIOS will wait for the
707 keyboard controller to become ready before giving up.
708
Idwer Vollering7c1a49b2014-04-01 22:47:33 +0000709config SEABIOS_THREAD_OPTIONROMS
710 prompt "Hardware init during option ROM execution" if PAYLOAD_SEABIOS
711 default n
712 bool
713 help
714 Allow hardware init to run in parallel with optionrom execution.
715
716 This can reduce boot time, but can cause some timing
717 variations during option ROM code execution. It is not
718 known if all option ROMs will behave properly with this option.
719
Martin Roth4d7d25f2014-07-25 14:39:05 -0600720config SEABIOS_MALLOC_UPPERMEMORY
721 bool
722 default y
723 depends on PAYLOAD_SEABIOS
724 help
725 Use the "Upper Memory Block" area (0xc0000-0xf0000) for internal
726 "low memory" allocations. If this is not selected, the memory is
727 instead allocated from the "9-segment" (0x90000-0xa0000).
728 This is not typically needed, but may be required on some platforms
729 to allow USB and SATA buffers to be written correctly by the
730 hardware. In general, if this is desired, the option will be
731 set to 'N' by the chipset Kconfig.
732
Edward O'Callaghana296f9e2014-09-13 03:43:49 +1000733config SEABIOS_VGA_COREBOOT
734 prompt "Include generated option rom that implements legacy VGA BIOS compatibility" if PAYLOAD_SEABIOS
735 default n
Timothy Pearsonadb59082015-02-05 10:47:40 -0600736 depends on !VGA_BIOS && (MAINBOARD_DO_NATIVE_VGA_INIT || MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG)
Edward O'Callaghana296f9e2014-09-13 03:43:49 +1000737 bool
738 help
739 Coreboot can initialize the GPU of some mainboards.
740
741 After initializing the GPU, the information about it can be passed to the payload.
742 Provide an option rom that implements this legacy VGA BIOS compatibility requirement.
743
Stefan Reinauere50952f2011-04-15 03:34:05 +0000744choice
Vladimir Serbinenko113a3662013-11-14 12:10:08 +0100745 prompt "GRUB2 version"
746 default GRUB2_MASTER
747 depends on PAYLOAD_GRUB2
748
749config GRUB2_MASTER
750 bool "HEAD"
751 help
752 Newest GRUB2 version
Daniele Forsi53847a22014-07-22 18:00:56 +0200753
Vladimir Serbinenko113a3662013-11-14 12:10:08 +0100754endchoice
755
756choice
Stefan Reinauere50952f2011-04-15 03:34:05 +0000757 prompt "FILO version"
758 default FILO_STABLE
759 depends on PAYLOAD_FILO
760
761config FILO_STABLE
762 bool "0.6.0"
763 help
764 Stable FILO version
Daniele Forsi53847a22014-07-22 18:00:56 +0200765
Stefan Reinauere50952f2011-04-15 03:34:05 +0000766config FILO_MASTER
767 bool "HEAD"
768 help
769 Newest FILO version
Daniele Forsi53847a22014-07-22 18:00:56 +0200770
Stefan Reinauere50952f2011-04-15 03:34:05 +0000771endchoice
772
Stefan Reinauerbccbbe62010-12-19 21:20:14 +0000773config PAYLOAD_FILE
Cristi Magherusanb5034d42009-08-17 14:47:32 +0000774 string "Payload path and filename"
Patrick Georgi0588d192009-08-12 15:00:51 +0000775 depends on PAYLOAD_ELF
776 default "payload.elf"
777 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000778 The path and filename of the ELF executable file to use as payload.
Patrick Georgi0588d192009-08-12 15:00:51 +0000779
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000780config PAYLOAD_FILE
Patrick Georgi16ae95c2013-08-31 08:26:52 +0200781 string "Linux path and filename"
782 depends on PAYLOAD_LINUX
783 default "bzImage"
784 help
785 The path and filename of the bzImage kernel to use as payload.
786
787config PAYLOAD_FILE
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000788 depends on PAYLOAD_SEABIOS
Idwer Volleringab11a6a92014-08-11 16:09:07 +0200789 default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000790
Edward O'Callaghana296f9e2014-09-13 03:43:49 +1000791config PAYLOAD_VGABIOS_FILE
792 string
793 depends on PAYLOAD_SEABIOS && SEABIOS_VGA_COREBOOT
794 default "payloads/external/SeaBIOS/seabios/out/vgabios.bin"
795
Stefan Reinauere50952f2011-04-15 03:34:05 +0000796config PAYLOAD_FILE
797 depends on PAYLOAD_FILO
798 default "payloads/external/FILO/filo/build/filo.elf"
799
Stefan Reinauer275fb632013-02-05 13:58:29 -0800800config PAYLOAD_FILE
Vladimir Serbinenko113a3662013-11-14 12:10:08 +0100801 depends on PAYLOAD_GRUB2
802 default "payloads/external/GRUB2/grub2/build/default_payload.elf"
803
804config PAYLOAD_FILE
Stefan Reinauer275fb632013-02-05 13:58:29 -0800805 string "Tianocore firmware volume"
806 depends on PAYLOAD_TIANOCORE
807 default "COREBOOT.fd"
808 help
809 The result of a corebootPkg build
810
Uwe Hermann168b11b2009-10-07 16:15:40 +0000811# TODO: Defined if no payload? Breaks build?
812config COMPRESSED_PAYLOAD_LZMA
813 bool "Use LZMA compression for payloads"
814 default y
Vladimir Serbinenko113a3662013-11-14 12:10:08 +0100815 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO || PAYLOAD_TIANOCORE || PAYLOAD_GRUB2
Uwe Hermann168b11b2009-10-07 16:15:40 +0000816 help
817 In order to reduce the size payloads take up in the ROM chip
818 coreboot can compress them using the LZMA algorithm.
819
Patrick Georgi16ae95c2013-08-31 08:26:52 +0200820config LINUX_COMMAND_LINE
821 string "Linux command line"
822 depends on PAYLOAD_LINUX
823 default ""
824 help
825 A command line to add to the Linux kernel.
826
827config LINUX_INITRD
828 string "Linux initrd"
829 depends on PAYLOAD_LINUX
830 default ""
831 help
832 An initrd image to add to the Linux kernel.
833
Peter Stugea758ca22009-09-17 16:21:31 +0000834endmenu
835
Uwe Hermann168b11b2009-10-07 16:15:40 +0000836menu "Debugging"
837
838# TODO: Better help text and detailed instructions.
Patrick Georgi0588d192009-08-12 15:00:51 +0000839config GDB_STUB
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000840 bool "GDB debugging support"
Rudolf Marek65888022012-03-25 20:51:16 +0200841 default n
Patrick Georgi0588d192009-08-12 15:00:51 +0000842 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000843 If enabled, you will be able to set breakpoints for gdb debugging.
Stefan Reinauer8677a232010-12-11 20:33:41 +0000844 See src/arch/x86/lib/c_start.S for details.
Patrick Georgi0588d192009-08-12 15:00:51 +0000845
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200846config GDB_WAIT
847 bool "Wait for a GDB connection"
848 default n
849 depends on GDB_STUB
850 help
851 If enabled, coreboot will wait for a GDB connection.
852
Julius Wernerd82e0cf2015-02-17 17:27:23 -0800853config FATAL_ASSERTS
854 bool "Halt when hitting a BUG() or assertion error"
855 default n
856 help
857 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
858
Stefan Reinauerfe422182012-05-02 16:33:18 -0700859config DEBUG_CBFS
860 bool "Output verbose CBFS debug messages"
861 default n
Stefan Reinauerfe422182012-05-02 16:33:18 -0700862 help
863 This option enables additional CBFS related debug messages.
864
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000865config HAVE_DEBUG_RAM_SETUP
866 def_bool n
867
Uwe Hermann01ce6012010-03-05 10:03:50 +0000868config DEBUG_RAM_SETUP
869 bool "Output verbose RAM init debug messages"
870 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000871 depends on HAVE_DEBUG_RAM_SETUP
Uwe Hermann01ce6012010-03-05 10:03:50 +0000872 help
873 This option enables additional RAM init related debug messages.
874 It is recommended to enable this when debugging issues on your
875 board which might be RAM init related.
876
877 Note: This option will increase the size of the coreboot image.
878
879 If unsure, say N.
880
Patrick Georgie82618d2010-10-01 14:50:12 +0000881config HAVE_DEBUG_CAR
882 def_bool n
883
Peter Stuge5015f792010-11-10 02:00:32 +0000884config DEBUG_CAR
885 def_bool n
886 depends on HAVE_DEBUG_CAR
887
888if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
Uwe Hermanna953f372010-11-10 00:14:32 +0000889# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
890# printk(BIOS_DEBUG, ...) calls.
Patrick Georgie82618d2010-10-01 14:50:12 +0000891config DEBUG_CAR
892 bool "Output verbose Cache-as-RAM debug messages"
893 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000894 depends on HAVE_DEBUG_CAR
Patrick Georgie82618d2010-10-01 14:50:12 +0000895 help
896 This option enables additional CAR related debug messages.
Peter Stuge5015f792010-11-10 02:00:32 +0000897endif
Patrick Georgie82618d2010-10-01 14:50:12 +0000898
Myles Watson80e914ff2010-06-01 19:25:31 +0000899config DEBUG_PIRQ
900 bool "Check PIRQ table consistency"
901 default n
902 depends on GENERATE_PIRQ_TABLE
903 help
904 If unsure, say N.
905
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000906config HAVE_DEBUG_SMBUS
907 def_bool n
908
Uwe Hermann01ce6012010-03-05 10:03:50 +0000909config DEBUG_SMBUS
910 bool "Output verbose SMBus debug messages"
911 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000912 depends on HAVE_DEBUG_SMBUS
Uwe Hermann01ce6012010-03-05 10:03:50 +0000913 help
914 This option enables additional SMBus (and SPD) debug messages.
915
916 Note: This option will increase the size of the coreboot image.
917
918 If unsure, say N.
919
920config DEBUG_SMI
921 bool "Output verbose SMI debug messages"
922 default n
923 depends on HAVE_SMI_HANDLER
924 help
925 This option enables additional SMI related debug messages.
926
927 Note: This option will increase the size of the coreboot image.
928
929 If unsure, say N.
930
Stefan Reinauerbc0f7a62010-08-01 15:41:14 +0000931config DEBUG_SMM_RELOCATION
932 bool "Debug SMM relocation code"
933 default n
934 depends on HAVE_SMI_HANDLER
935 help
936 This option enables additional SMM handler relocation related
937 debug messages.
938
939 Note: This option will increase the size of the coreboot image.
940
941 If unsure, say N.
942
Uwe Hermanna953f372010-11-10 00:14:32 +0000943# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
944# printk(BIOS_DEBUG, ...) calls.
945config DEBUG_MALLOC
Stefan Reinauer95a63962012-11-13 17:00:01 -0800946 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
947 bool
Uwe Hermanna953f372010-11-10 00:14:32 +0000948 default n
Uwe Hermanna953f372010-11-10 00:14:32 +0000949 help
950 This option enables additional malloc related debug messages.
951
952 Note: This option will increase the size of the coreboot image.
953
954 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300955
956# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
957# printk(BIOS_DEBUG, ...) calls.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300958config DEBUG_ACPI
Stefan Reinauer95a63962012-11-13 17:00:01 -0800959 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
960 bool
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300961 default n
962 help
963 This option enables additional ACPI related debug messages.
964
965 Note: This option will slightly increase the size of the coreboot image.
966
967 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300968
Uwe Hermanna953f372010-11-10 00:14:32 +0000969# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
970# printk(BIOS_DEBUG, ...) calls.
Myles Watson6c9bc012010-09-07 22:30:15 +0000971config REALMODE_DEBUG
Stefan Reinauer95a63962012-11-13 17:00:01 -0800972 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
973 bool
Myles Watson6c9bc012010-09-07 22:30:15 +0000974 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000975 depends on PCI_OPTION_ROM_RUN_REALMODE
Myles Watson6c9bc012010-09-07 22:30:15 +0000976 help
977 This option enables additional x86emu related debug messages.
978
979 Note: This option will increase the time to emulate a ROM.
980
981 If unsure, say N.
982
Uwe Hermann01ce6012010-03-05 10:03:50 +0000983config X86EMU_DEBUG
984 bool "Output verbose x86emu debug messages"
985 default n
986 depends on PCI_OPTION_ROM_RUN_YABEL
987 help
988 This option enables additional x86emu related debug messages.
989
990 Note: This option will increase the size of the coreboot image.
991
992 If unsure, say N.
993
994config X86EMU_DEBUG_JMP
995 bool "Trace JMP/RETF"
996 default n
997 depends on X86EMU_DEBUG
998 help
999 Print information about JMP and RETF opcodes from x86emu.
1000
1001 Note: This option will increase the size of the coreboot image.
1002
1003 If unsure, say N.
1004
1005config X86EMU_DEBUG_TRACE
1006 bool "Trace all opcodes"
1007 default n
1008 depends on X86EMU_DEBUG
1009 help
1010 Print _all_ opcodes that are executed by x86emu.
Stefan Reinauer14e22772010-04-27 06:56:47 +00001011
Uwe Hermann01ce6012010-03-05 10:03:50 +00001012 WARNING: This will produce a LOT of output and take a long time.
1013
1014 Note: This option will increase the size of the coreboot image.
1015
1016 If unsure, say N.
1017
1018config X86EMU_DEBUG_PNP
1019 bool "Log Plug&Play accesses"
1020 default n
1021 depends on X86EMU_DEBUG
1022 help
1023 Print Plug And Play accesses made by option ROMs.
1024
1025 Note: This option will increase the size of the coreboot image.
1026
1027 If unsure, say N.
1028
1029config X86EMU_DEBUG_DISK
1030 bool "Log Disk I/O"
1031 default n
1032 depends on X86EMU_DEBUG
1033 help
1034 Print Disk I/O related messages.
1035
1036 Note: This option will increase the size of the coreboot image.
1037
1038 If unsure, say N.
1039
1040config X86EMU_DEBUG_PMM
1041 bool "Log PMM"
1042 default n
1043 depends on X86EMU_DEBUG
1044 help
1045 Print messages related to POST Memory Manager (PMM).
1046
1047 Note: This option will increase the size of the coreboot image.
1048
1049 If unsure, say N.
1050
1051
1052config X86EMU_DEBUG_VBE
1053 bool "Debug VESA BIOS Extensions"
1054 default n
1055 depends on X86EMU_DEBUG
1056 help
1057 Print messages related to VESA BIOS Extension (VBE) functions.
1058
1059 Note: This option will increase the size of the coreboot image.
1060
1061 If unsure, say N.
1062
1063config X86EMU_DEBUG_INT10
1064 bool "Redirect INT10 output to console"
1065 default n
1066 depends on X86EMU_DEBUG
1067 help
1068 Let INT10 (i.e. character output) calls print messages to debug output.
1069
1070 Note: This option will increase the size of the coreboot image.
1071
1072 If unsure, say N.
1073
1074config X86EMU_DEBUG_INTERRUPTS
1075 bool "Log intXX calls"
1076 default n
1077 depends on X86EMU_DEBUG
1078 help
1079 Print messages related to interrupt handling.
1080
1081 Note: This option will increase the size of the coreboot image.
1082
1083 If unsure, say N.
1084
1085config X86EMU_DEBUG_CHECK_VMEM_ACCESS
1086 bool "Log special memory accesses"
1087 default n
1088 depends on X86EMU_DEBUG
1089 help
1090 Print messages related to accesses to certain areas of the virtual
1091 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
1092
1093 Note: This option will increase the size of the coreboot image.
1094
1095 If unsure, say N.
1096
1097config X86EMU_DEBUG_MEM
1098 bool "Log all memory accesses"
1099 default n
1100 depends on X86EMU_DEBUG
1101 help
1102 Print memory accesses made by option ROM.
1103 Note: This also includes accesses to fetch instructions.
1104
1105 Note: This option will increase the size of the coreboot image.
1106
1107 If unsure, say N.
1108
1109config X86EMU_DEBUG_IO
1110 bool "Log IO accesses"
1111 default n
1112 depends on X86EMU_DEBUG
1113 help
1114 Print I/O accesses made by option ROM.
1115
1116 Note: This option will increase the size of the coreboot image.
1117
1118 If unsure, say N.
1119
Denis 'GNUtoo' Carikli4cdc5d62013-05-15 00:19:49 +02001120config X86EMU_DEBUG_TIMINGS
1121 bool "Output timing information"
1122 default n
1123 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
1124 help
1125 Print timing information needed by i915tool.
1126
1127 If unsure, say N.
1128
Stefan Reinauerdfb098d2011-11-17 12:50:54 -08001129config DEBUG_TPM
1130 bool "Output verbose TPM debug messages"
1131 default n
1132 depends on TPM
1133 help
1134 This option enables additional TPM related debug messages.
1135
Stefan Reinauer1c56d9b2012-05-10 11:27:32 -07001136config DEBUG_SPI_FLASH
1137 bool "Output verbose SPI flash debug messages"
1138 default n
1139 depends on SPI_FLASH
1140 help
1141 This option enables additional SPI flash related debug messages.
1142
Kyösti Mälkki3be80cc2013-06-06 10:46:37 +03001143config DEBUG_USBDEBUG
1144 bool "Output verbose USB 2.0 EHCI debug dongle messages"
1145 default n
1146 depends on USBDEBUG
1147 help
1148 This option enables additional USB 2.0 debug dongle related messages.
1149
1150 Select this to debug the connection of usbdebug dongle. Note that
1151 you need some other working console to receive the messages.
1152
Stefan Reinauer8e073822012-04-04 00:07:22 +02001153if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1154# Only visible with the right southbridge and loglevel.
1155config DEBUG_INTEL_ME
1156 bool "Verbose logging for Intel Management Engine"
1157 default n
1158 help
1159 Enable verbose logging for Intel Management Engine driver that
1160 is present on Intel 6-series chipsets.
1161endif
1162
Rudolf Marek7f0e9302011-09-02 23:23:41 +02001163config TRACE
1164 bool "Trace function calls"
1165 default n
1166 help
1167 If enabled, every function will print information to console once
1168 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1169 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1170 of calling function. Please note some printk releated functions
1171 are omitted from trace to have good looking console dumps.
Stefan Reinauerd37ab452012-12-18 16:23:28 -08001172
1173config DEBUG_COVERAGE
1174 bool "Debug code coverage"
1175 default n
1176 depends on COVERAGE
1177 help
1178 If enabled, the code coverage hooks in coreboot will output some
1179 information about the coverage data that is dumped.
1180
Uwe Hermann168b11b2009-10-07 16:15:40 +00001181endmenu
1182
Myles Watsond73c1b52009-10-26 15:14:07 +00001183# These probably belong somewhere else, but they are needed somewhere.
Myles Watsond73c1b52009-10-26 15:14:07 +00001184config ENABLE_APIC_EXT_ID
1185 bool
1186 default n
Myles Watson2e672732009-11-12 16:38:03 +00001187
1188config WARNINGS_ARE_ERRORS
1189 bool
Edward O'Callaghan63f6dc72014-11-18 03:17:54 +11001190 default y
Patrick Georgi436f99b2009-11-27 16:55:13 +00001191
Peter Stuge51eafde2010-10-13 06:23:02 +00001192# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1193# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1194# mutually exclusive. One of these options must be selected in the
1195# mainboard Kconfig if the chipset supports enabling and disabling of
1196# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1197# in mainboard/Kconfig to know if the button should be enabled or not.
1198
1199config POWER_BUTTON_DEFAULT_ENABLE
1200 def_bool n
1201 help
1202 Select when the board has a power button which can optionally be
1203 disabled by the user.
1204
1205config POWER_BUTTON_DEFAULT_DISABLE
1206 def_bool n
1207 help
1208 Select when the board has a power button which can optionally be
1209 enabled by the user, e.g. when the board ships with a jumper over
1210 the power switch contacts.
1211
1212config POWER_BUTTON_FORCE_ENABLE
1213 def_bool n
1214 help
1215 Select when the board requires that the power button is always
1216 enabled.
1217
1218config POWER_BUTTON_FORCE_DISABLE
1219 def_bool n
1220 help
1221 Select when the board requires that the power button is always
1222 disabled, e.g. when it has been hardwired to ground.
1223
1224config POWER_BUTTON_IS_OPTIONAL
1225 bool
1226 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1227 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1228 help
1229 Internal option that controls ENABLE_POWER_BUTTON visibility.
Duncan Laurie72748002013-10-31 08:26:23 -07001230
1231config REG_SCRIPT
1232 bool
Duncan Laurie72748002013-10-31 08:26:23 -07001233 default n
1234 help
1235 Internal option that controls whether we compile in register scripts.
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001236
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001237config MAX_REBOOT_CNT
1238 int
1239 default 3
Timothy Pearson17ada2e2015-03-18 01:31:34 -05001240 help
1241 Internal option that sets the maximum number of bootblock executions allowed
1242 with the normal image enabled before assuming the normal image is defective
Vadim Bendebury9c9c3362014-07-23 09:40:02 -07001243 and switching to the fallback image.