Duncan Laurie | 9db8c25 | 2020-05-10 11:16:45 -0700 | [diff] [blame] | 1 | fw_config |
Nick Vaccaro | 2cc0600 | 2020-06-18 12:19:08 -0700 | [diff] [blame] | 2 | field DB_USB 0 3 |
| 3 | option USB_ABSENT 0 |
| 4 | option USB4_GEN2 1 |
| 5 | option USB3_ACTIVE 2 |
| 6 | option USB4_GEN3 3 |
| 7 | option USB3_PASSIVE 4 |
| 8 | option USB3_NO_A 5 |
Duncan Laurie | 5abf040 | 2020-10-28 15:14:27 -0700 | [diff] [blame] | 9 | option USB3_NO_C 6 |
Duncan Laurie | 9db8c25 | 2020-05-10 11:16:45 -0700 | [diff] [blame] | 10 | end |
| 11 | field THERMAL 4 7 end |
| 12 | field AUDIO 8 10 |
| 13 | option NONE 0 |
| 14 | option MAX98357_ALC5682I_I2S 1 |
| 15 | option MAX98373_ALC5682I_I2S 2 |
| 16 | option MAX98373_ALC5682_SNDW 3 |
Frank Wu | 362bcee | 2020-08-19 09:56:43 +0800 | [diff] [blame] | 17 | option MAX98373_ALC5682I_I2S_UP4 4 |
Wisley Chen | 35010ef | 2020-11-06 17:16:59 +0800 | [diff] [blame] | 18 | option MAX98360_ALC5682I_I2S 5 |
Stanley Wu | 64f7bdf | 2020-10-30 12:01:20 +0800 | [diff] [blame] | 19 | option RT1011_ALC5682I_I2S 6 |
Duncan Laurie | 9db8c25 | 2020-05-10 11:16:45 -0700 | [diff] [blame] | 20 | end |
| 21 | field TABLETMODE 11 |
Nick Vaccaro | 2cc0600 | 2020-06-18 12:19:08 -0700 | [diff] [blame] | 22 | option TABLETMODE_DISABLED 0 |
| 23 | option TABLETMODE_ENABLED 1 |
Duncan Laurie | 9db8c25 | 2020-05-10 11:16:45 -0700 | [diff] [blame] | 24 | end |
Nick Vaccaro | 2cc0600 | 2020-06-18 12:19:08 -0700 | [diff] [blame] | 25 | field DB_LTE 12 13 |
| 26 | option LTE_ABSENT 0 |
| 27 | option LTE_PRESENT 1 |
| 28 | end |
Duncan Laurie | 14efbb4 | 2020-09-08 20:35:06 +0000 | [diff] [blame] | 29 | field KB_BL 14 |
| 30 | option KB_BL_ABSENT 0 |
| 31 | option KB_BL_PRESENT 1 |
| 32 | end |
| 33 | field NUMPAD 15 |
| 34 | option NUMPAD_ABSENT 0 |
| 35 | option NUMPAD_PRESENT 1 |
| 36 | end |
Nick Vaccaro | 2cc0600 | 2020-06-18 12:19:08 -0700 | [diff] [blame] | 37 | field DB_SD 16 19 |
| 38 | option SD_ABSENT 0 |
| 39 | option SD_GL9755S 1 |
| 40 | option SD_RTS5261 2 |
Zhuohao Lee | b3b4ccf | 2020-11-23 11:41:25 +0800 | [diff] [blame] | 41 | option SD_RTS5227S 3 |
Duncan Laurie | 912d9ec | 2020-11-30 10:09:42 -0800 | [diff] [blame] | 42 | option SD_GL9750 4 |
Zhuohao Lee | b3b4ccf | 2020-11-23 11:41:25 +0800 | [diff] [blame] | 43 | option SD_OZ711LV2LN 5 |
Duncan Laurie | 9db8c25 | 2020-05-10 11:16:45 -0700 | [diff] [blame] | 44 | end |
Duncan Laurie | bd04995 | 2020-11-11 13:01:27 -0800 | [diff] [blame] | 45 | field KB_LAYOUT 20 21 |
| 46 | option KB_LAYOUT_DEFAULT 0 |
| 47 | option KB_LAYOUT_1 1 |
| 48 | end |
Duncan Laurie | 89bbe14 | 2020-11-30 10:12:56 -0800 | [diff] [blame] | 49 | field BOOT_DEVICE_EMMC 22 |
| 50 | option BOOT_EMMC_DISABLED 0 |
| 51 | option BOOT_EMMC_ENABLED 1 |
| 52 | end |
| 53 | field BOOT_DEVICE_NVME 23 |
| 54 | option BOOT_NVME_DISABLED 0 |
| 55 | option BOOT_NVME_ENABLED 1 |
| 56 | end |
| 57 | field BOOT_DEVICE_SATA 24 |
| 58 | option BOOT_SATA_DISABLED 0 |
| 59 | option BOOT_SATA_ENABLED 1 |
| 60 | end |
Zhuohao Lee | 275440e | 2021-01-19 13:06:18 +0800 | [diff] [blame] | 61 | field TOUCHPAD 25 |
| 62 | option REGULAR_TOUCHPAD 0 |
| 63 | option NUMPAD_TOUCHPAD 1 |
| 64 | end |
Kevin Chang | 1c02f6f | 2021-03-10 09:22:09 +0800 | [diff] [blame] | 65 | field WIFI_SAR_ID 26 27 |
| 66 | option WIFI_SAR_ID_0 0 |
| 67 | option WIFI_SAR_ID_1 1 |
| 68 | option WIFI_SAR_ID_2 2 |
| 69 | option WIFI_SAR_ID_3 3 |
| 70 | end |
Duncan Laurie | 9db8c25 | 2020-05-10 11:16:45 -0700 | [diff] [blame] | 71 | end |
| 72 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 73 | chip soc/intel/tigerlake |
| 74 | |
| 75 | device cpu_cluster 0 on |
| 76 | device lapic 0 on end |
| 77 | end |
| 78 | |
| 79 | # GPE configuration |
| 80 | # Note that GPE events called out in ASL code rely on this |
| 81 | # route. i.e. If this route changes then the affected GPE |
| 82 | # offset bits also need to be changed. |
| 83 | register "pmc_gpe0_dw0" = "GPP_C" |
| 84 | register "pmc_gpe0_dw1" = "GPP_D" |
| 85 | register "pmc_gpe0_dw2" = "GPP_E" |
| 86 | |
Jamie Ryu | 154625b | 2020-06-12 02:59:26 -0700 | [diff] [blame] | 87 | # Enable heci communication |
| 88 | register "HeciEnabled" = "1" |
| 89 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 90 | # FSP configuration |
Shreesh Chhabbi | 3708687 | 2020-06-17 12:40:42 -0700 | [diff] [blame] | 91 | register "SaGv" = "SaGv_Enabled" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 92 | register "SmbusEnable" = "0" |
| 93 | |
| 94 | register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 |
| 95 | register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 |
| 96 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN |
| 97 | register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Cl |
| 98 | register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 99 | register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Co |
| 100 | register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth |
| 101 | |
| 102 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 |
| 103 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 |
| 104 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN |
| 105 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 Camera |
| 106 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 107 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 108 | register "gen1_dec" = "0x00fc0801" |
| 109 | register "gen2_dec" = "0x000c0201" |
| 110 | # EC memory map range is 0x900-0x9ff |
| 111 | register "gen3_dec" = "0x00fc0901" |
| 112 | |
| 113 | # Enable NVMe PCIE 9 using clk 0 |
| 114 | register "PcieRpEnable[8]" = "1" |
Wonkyu Kim | e3bf8ba | 2020-04-07 23:34:12 -0700 | [diff] [blame] | 115 | register "PcieRpLtrEnable[8]" = "1" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 116 | register "PcieClkSrcUsage[0]" = "8" |
| 117 | register "PcieClkSrcClkReq[0]" = "0" |
| 118 | |
Venkata Krishna Nimmagadda | c34bb38 | 2020-01-15 10:13:26 -0800 | [diff] [blame] | 119 | # Enable Optane PCIE 11 using clk 0 |
| 120 | register "PcieRpEnable[10]" = "1" |
Wonkyu Kim | e3bf8ba | 2020-04-07 23:34:12 -0700 | [diff] [blame] | 121 | register "PcieRpLtrEnable[10]" = "1" |
Shaunak Saha | b27b0fd | 2020-09-22 23:09:24 -0700 | [diff] [blame] | 122 | register "HybridStorageMode" = "0" |
Venkata Krishna Nimmagadda | c34bb38 | 2020-01-15 10:13:26 -0800 | [diff] [blame] | 123 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 124 | # Enable SD Card PCIE 8 using clk 3 |
| 125 | register "PcieRpEnable[7]" = "1" |
Wonkyu Kim | e3bf8ba | 2020-04-07 23:34:12 -0700 | [diff] [blame] | 126 | register "PcieRpLtrEnable[7]" = "1" |
nick_xr_chen | f446b81 | 2020-06-30 09:34:33 +0800 | [diff] [blame] | 127 | register "PcieRpHotPlug[7]" = "1" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 128 | register "PcieClkSrcUsage[3]" = "7" |
| 129 | register "PcieClkSrcClkReq[3]" = "3" |
| 130 | |
| 131 | # Enable WLAN PCIE 7 using clk 1 |
| 132 | register "PcieRpEnable[6]" = "1" |
Wonkyu Kim | e3bf8ba | 2020-04-07 23:34:12 -0700 | [diff] [blame] | 133 | register "PcieRpLtrEnable[6]" = "1" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 134 | register "PcieClkSrcUsage[1]" = "6" |
| 135 | register "PcieClkSrcClkReq[1]" = "1" |
| 136 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 137 | # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality |
David Wu | 7d1a137 | 2020-10-21 10:42:25 +0800 | [diff] [blame] | 138 | register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" |
| 139 | register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" |
| 140 | register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" |
| 141 | register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 142 | |
| 143 | # Enable SATA |
| 144 | register "SataEnable" = "1" |
| 145 | register "SataMode" = "0" |
| 146 | register "SataSalpSupport" = "1" |
| 147 | register "SataPortsEnable[0]" = "0" |
| 148 | register "SataPortsEnable[1]" = "1" |
| 149 | register "SataPortsDevSlp[0]" = "0" |
Wonkyu Kim | b8bfe14 | 2020-04-21 17:07:57 -0700 | [diff] [blame] | 150 | register "SataPortsDevSlp[1]" = "1" |
Shaunak Saha | 60e6f6e | 2020-06-15 23:59:52 -0700 | [diff] [blame] | 151 | register "SataPortsEnableDitoConfig[1]" = "1" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 152 | |
| 153 | register "SerialIoI2cMode" = "{ |
| 154 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 155 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 156 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 157 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 158 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 159 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 160 | }" |
| 161 | |
| 162 | register "SerialIoGSpiMode" = "{ |
| 163 | [PchSerialIoIndexGSPI0] = PchSerialIoPci, |
| 164 | [PchSerialIoIndexGSPI1] = PchSerialIoPci, |
| 165 | [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, |
| 166 | [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, |
| 167 | }" |
| 168 | |
| 169 | register "SerialIoGSpiCsMode" = "{ |
| 170 | [PchSerialIoIndexGSPI0] = 1, |
| 171 | [PchSerialIoIndexGSPI1] = 1, |
| 172 | [PchSerialIoIndexGSPI2] = 0, |
| 173 | [PchSerialIoIndexGSPI3] = 0, |
| 174 | }" |
| 175 | |
| 176 | register "SerialIoGSpiCsState" = "{ |
Caveh Jalali | 85e4c43 | 2020-09-12 03:05:48 -0700 | [diff] [blame] | 177 | [PchSerialIoIndexGSPI0] = 1, |
| 178 | [PchSerialIoIndexGSPI1] = 1, |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 179 | [PchSerialIoIndexGSPI2] = 0, |
| 180 | [PchSerialIoIndexGSPI3] = 0, |
| 181 | }" |
| 182 | |
| 183 | register "SerialIoUartMode" = "{ |
| 184 | [PchSerialIoIndexUART0] = PchSerialIoPci, |
| 185 | [PchSerialIoIndexUART1] = PchSerialIoDisabled, |
| 186 | [PchSerialIoIndexUART2] = PchSerialIoDisabled, |
| 187 | }" |
| 188 | |
Jamie Ryu | 8053595 | 2020-08-18 19:10:43 -0700 | [diff] [blame] | 189 | # Set the minimum assertion width |
| 190 | # PchPmSlpS3MinAssert: |
| 191 | # - 1: 60us |
| 192 | # - 2: 1ms |
| 193 | # - 3: 50ms |
| 194 | # - 4: 2s |
| 195 | register "PchPmSlpS3MinAssert" = "3" # 50ms |
| 196 | # PchPmSlpS4MinAssert: |
| 197 | # - 1 = 1s |
| 198 | # - 2 = 2s |
| 199 | # - 3 = 3s |
| 200 | # - 4 = 4s |
| 201 | register "PchPmSlpS4MinAssert" = "1" # 1s |
| 202 | # PchPmSlpSusMinAssert: |
| 203 | # - 1 = 0ms |
| 204 | # - 2 = 500ms |
| 205 | # - 3 = 1s |
| 206 | # - 4 = 4s |
| 207 | register "PchPmSlpSusMinAssert" = "3" # 1s |
| 208 | # PchPmSlpAMinAssert |
| 209 | # - 1 = 0ms |
| 210 | # - 2 = 4s |
| 211 | # - 3 = 98ms |
| 212 | # - 4 = 2s |
| 213 | register "PchPmSlpAMinAssert" = "3" # 98ms |
| 214 | |
| 215 | # NOTE: Duration programmed in the below register should never be smaller than the |
| 216 | # stretch duration programmed in the following registers - |
| 217 | # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) |
| 218 | # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) |
| 219 | # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) |
| 220 | # - PM_CFG.SLP_LAN_MIN_ASST_WDTH |
| 221 | register "PchPmPwrCycDur" = "1" # 1s |
| 222 | |
Srinidhi N Kaushik | 22d5b07 | 2020-03-06 10:47:17 -0800 | [diff] [blame] | 223 | # HD Audio |
| 224 | register "PchHdaDspEnable" = "1" |
| 225 | register "PchHdaAudioLinkHdaEnable" = "0" |
Duncan Laurie | 4dffa9c | 2020-05-10 11:20:20 -0700 | [diff] [blame] | 226 | register "PchHdaAudioLinkDmicEnable[0]" = "0" |
| 227 | register "PchHdaAudioLinkDmicEnable[1]" = "0" |
| 228 | register "PchHdaAudioLinkSspEnable[0]" = "0" |
| 229 | register "PchHdaAudioLinkSspEnable[1]" = "0" |
| 230 | register "PchHdaAudioLinkSndwEnable[0]" = "0" |
| 231 | register "PchHdaAudioLinkSndwEnable[1]" = "0" |
Srinidhi N Kaushik | 22d5b07 | 2020-03-06 10:47:17 -0800 | [diff] [blame] | 232 | |
Brandon Breitenstein | 01ec713 | 2020-03-06 10:51:30 -0800 | [diff] [blame] | 233 | # TCSS USB3 |
Brandon Breitenstein | 40b5358 | 2020-12-21 14:57:50 -0800 | [diff] [blame] | 234 | register "UsbTcPortEn" = "0x3" |
Brandon Breitenstein | 01ec713 | 2020-03-06 10:51:30 -0800 | [diff] [blame] | 235 | register "TcssXhciEn" = "1" |
Brandon Breitenstein | 1df3b70 | 2020-08-10 15:02:41 -0700 | [diff] [blame] | 236 | register "TcssAuxOri" = "0" |
Brandon Breitenstein | b7911c8 | 2020-04-06 15:34:19 -0700 | [diff] [blame] | 237 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 238 | # DP port |
| 239 | register "DdiPortAConfig" = "1" # eDP |
| 240 | register "DdiPortBConfig" = "0" |
| 241 | |
| 242 | register "DdiPortAHpd" = "1" |
| 243 | register "DdiPortBHpd" = "1" |
| 244 | register "DdiPortCHpd" = "0" |
| 245 | register "DdiPort1Hpd" = "1" |
| 246 | register "DdiPort2Hpd" = "1" |
| 247 | register "DdiPort3Hpd" = "0" |
| 248 | register "DdiPort4Hpd" = "0" |
| 249 | |
| 250 | register "DdiPortADdc" = "0" |
| 251 | register "DdiPortBDdc" = "1" |
| 252 | register "DdiPortCDdc" = "0" |
| 253 | register "DdiPort1Ddc" = "0" |
| 254 | register "DdiPort2Ddc" = "0" |
| 255 | register "DdiPort3Ddc" = "0" |
| 256 | register "DdiPort4Ddc" = "0" |
| 257 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 258 | # Enable S0ix |
| 259 | register "s0ix_enable" = "1" |
| 260 | |
Sumeet R Pawnikar | 7d6bc60 | 2020-05-08 19:22:07 +0530 | [diff] [blame] | 261 | # Enable DPTF |
| 262 | register "dptf_enable" = "1" |
| 263 | |
Shreesh Chhabbi | 3c6ad8d | 2021-02-04 13:16:24 -0800 | [diff] [blame] | 264 | # Enable External Bypass |
| 265 | register "external_bypass" = "1" |
| 266 | |
| 267 | # Enable External Clk Gate |
| 268 | register "external_clk_gated" = "1" |
| 269 | |
| 270 | # Enable External Phy Gate |
| 271 | register "external_phy_gated" = "1" |
| 272 | |
Sumeet R Pawnikar | 1a62150 | 2020-07-20 15:44:59 +0530 | [diff] [blame] | 273 | register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ |
| 274 | .tdp_pl1_override = 15, |
| 275 | .tdp_pl2_override = 38, |
| 276 | .tdp_pl4 = 71, |
| 277 | }" |
Tim Wawrzynczak | 2dcca0f | 2020-06-16 10:50:47 -0600 | [diff] [blame] | 278 | register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ |
Sumeet R Pawnikar | 7d6bc60 | 2020-05-08 19:22:07 +0530 | [diff] [blame] | 279 | .tdp_pl1_override = 15, |
| 280 | .tdp_pl2_override = 60, |
Tim Wawrzynczak | 2dcca0f | 2020-06-16 10:50:47 -0600 | [diff] [blame] | 281 | .tdp_pl4 = 105, |
| 282 | }" |
Sumeet R Pawnikar | 1a62150 | 2020-07-20 15:44:59 +0530 | [diff] [blame] | 283 | register "power_limits_config[POWER_LIMITS_Y_2_CORE]" = "{ |
| 284 | .tdp_pl1_override = 9, |
| 285 | .tdp_pl2_override = 35, |
| 286 | .tdp_pl4 = 66, |
| 287 | }" |
| 288 | register "power_limits_config[POWER_LIMITS_Y_4_CORE]" = "{ |
| 289 | .tdp_pl1_override = 9, |
| 290 | .tdp_pl2_override = 40, |
| 291 | .tdp_pl4 = 83, |
Sumeet R Pawnikar | 7d6bc60 | 2020-05-08 19:22:07 +0530 | [diff] [blame] | 292 | }" |
| 293 | |
| 294 | register "Device4Enable" = "1" |
| 295 | |
Sumeet R Pawnikar | 9f9b97e | 2020-06-30 14:18:41 +0530 | [diff] [blame] | 296 | register "tcc_offset" = "10" # TCC of 90 |
| 297 | |
Cliff Huang | 2eee6c3 | 2021-02-05 14:29:27 -0800 | [diff] [blame^] | 298 | register "CnviBtCore" = "true" |
| 299 | |
Angel Pons | 98521c5 | 2021-03-01 21:16:49 +0100 | [diff] [blame] | 300 | register "CnviBtAudioOffload" = "true" |
John Zhao | c8e3097 | 2020-09-21 13:20:57 -0700 | [diff] [blame] | 301 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 302 | # Intel Common SoC Config |
| 303 | #+-------------------+---------------------------+ |
| 304 | #| Field | Value | |
| 305 | #+-------------------+---------------------------+ |
| 306 | #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | |
| 307 | #| GSPI0 | cr50 TPM. Early init is | |
| 308 | #| | required to set up a BAR | |
| 309 | #| | for TPM communication | |
| 310 | #| | before memory is up | |
Alex Levin | 3bc41cf | 2020-03-06 10:54:10 -0800 | [diff] [blame] | 311 | #| GSPI1 | Fingerprint MCU | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 312 | #| I2C0 | Audio | |
| 313 | #| I2C1 | Touchscreen | |
| 314 | #| I2C2 | WLAN, SAR0 | |
| 315 | #| I2C3 | Camera, SAR1 | |
| 316 | #| I2C5 | Trackpad | |
| 317 | #+-------------------+---------------------------+ |
| 318 | register "common_soc_config" = "{ |
| 319 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 320 | .gspi[0] = { |
| 321 | .speed_mhz = 1, |
| 322 | .early_init = 1, |
| 323 | }, |
| 324 | .i2c[0] = { |
| 325 | .speed = I2C_SPEED_FAST, |
| 326 | }, |
| 327 | .i2c[1] = { |
| 328 | .speed = I2C_SPEED_FAST, |
| 329 | }, |
| 330 | .i2c[2] = { |
| 331 | .speed = I2C_SPEED_FAST, |
| 332 | }, |
| 333 | .i2c[3] = { |
| 334 | .speed = I2C_SPEED_FAST, |
| 335 | }, |
| 336 | .i2c[5] = { |
| 337 | .speed = I2C_SPEED_FAST, |
| 338 | }, |
| 339 | }" |
| 340 | |
Venkata Krishna Nimmagadda | 7368da3 | 2020-06-09 00:11:34 -0700 | [diff] [blame] | 341 | register "ext_fivr_settings" = "{ |
| 342 | .configure_ext_fivr = 1, |
| 343 | .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, |
| 344 | .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, |
| 345 | .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | |
| 346 | FIVR_VOLTAGE_MIN_ACTIVE | |
| 347 | FIVR_VOLTAGE_MIN_RETENTION, |
| 348 | .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | |
| 349 | FIVR_VOLTAGE_MIN_ACTIVE | |
| 350 | FIVR_VOLTAGE_MIN_RETENTION, |
| 351 | .v1p05_icc_max_ma = 500, |
| 352 | .vnn_sx_voltage_mv = 1250, |
| 353 | }" |
| 354 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 355 | device domain 0 on |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 356 | device ref igpu on end |
| 357 | device ref dptf on |
Tim Wawrzynczak | 07ac2ec | 2020-05-29 15:58:19 -0600 | [diff] [blame] | 358 | # Default DPTF Policy for all Volteer boards if not overridden |
| 359 | chip drivers/intel/dptf |
| 360 | ## Active Policy |
Tim Wawrzynczak | a5cb564 | 2020-09-08 13:14:09 -0600 | [diff] [blame] | 361 | register "policies.active" = "{ |
| 362 | [0] = {.target = DPTF_CPU, |
| 363 | .thresholds = {TEMP_PCT(85, 90), |
| 364 | TEMP_PCT(80, 69), |
| 365 | TEMP_PCT(75, 56), |
| 366 | TEMP_PCT(70, 46), |
| 367 | TEMP_PCT(65, 36),}}, |
| 368 | [1] = {.target = DPTF_TEMP_SENSOR_0, |
| 369 | .thresholds = {TEMP_PCT(50, 90), |
| 370 | TEMP_PCT(47, 69), |
| 371 | TEMP_PCT(45, 56), |
| 372 | TEMP_PCT(42, 46), |
| 373 | TEMP_PCT(39, 36),}}, |
| 374 | [2] = {.target = DPTF_TEMP_SENSOR_1, |
| 375 | .thresholds = {TEMP_PCT(50, 90), |
| 376 | TEMP_PCT(47, 69), |
| 377 | TEMP_PCT(45, 56), |
| 378 | TEMP_PCT(42, 46), |
| 379 | TEMP_PCT(39, 36),}}, |
| 380 | [3] = {.target = DPTF_TEMP_SENSOR_2, |
| 381 | .thresholds = {TEMP_PCT(50, 90), |
| 382 | TEMP_PCT(47, 69), |
| 383 | TEMP_PCT(45, 56), |
| 384 | TEMP_PCT(42, 46), |
| 385 | TEMP_PCT(39, 36),}}, |
| 386 | [4] = {.target = DPTF_TEMP_SENSOR_3, |
| 387 | .thresholds = {TEMP_PCT(50, 90), |
| 388 | TEMP_PCT(47, 69), |
| 389 | TEMP_PCT(45, 56), |
| 390 | TEMP_PCT(42, 46), |
| 391 | TEMP_PCT(39, 36),}}}" |
Tim Wawrzynczak | 07ac2ec | 2020-05-29 15:58:19 -0600 | [diff] [blame] | 392 | |
| 393 | ## Passive Policy |
Tim Wawrzynczak | a5cb564 | 2020-09-08 13:14:09 -0600 | [diff] [blame] | 394 | register "policies.passive" = "{ |
| 395 | [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), |
| 396 | [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), |
| 397 | [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), |
| 398 | [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000), |
| 399 | [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" |
Tim Wawrzynczak | 07ac2ec | 2020-05-29 15:58:19 -0600 | [diff] [blame] | 400 | |
| 401 | ## Critical Policy |
Tim Wawrzynczak | a5cb564 | 2020-09-08 13:14:09 -0600 | [diff] [blame] | 402 | register "policies.critical" = "{ |
| 403 | [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), |
| 404 | [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), |
| 405 | [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), |
| 406 | [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), |
| 407 | [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" |
Tim Wawrzynczak | 07ac2ec | 2020-05-29 15:58:19 -0600 | [diff] [blame] | 408 | |
| 409 | ## Power Limits Control |
Sumeet R Pawnikar | 88352c5 | 2020-10-08 21:15:42 +0530 | [diff] [blame] | 410 | # 3-15W PL1 in 200mW increments, avg over 28-32s interval |
| 411 | # PL2 ranges from 15 to 60W, avg over 28-32s interval |
Tim Wawrzynczak | a5cb564 | 2020-09-08 13:14:09 -0600 | [diff] [blame] | 412 | register "controls.power_limits" = "{ |
| 413 | .pl1 = {.min_power = 3000, |
| 414 | .max_power = 15000, |
| 415 | .time_window_min = 28 * MSECS_PER_SEC, |
| 416 | .time_window_max = 32 * MSECS_PER_SEC, |
| 417 | .granularity = 200,}, |
Sumeet R Pawnikar | a97fb7f | 2020-12-04 11:48:24 +0530 | [diff] [blame] | 418 | .pl2 = {.min_power = 60000, |
Tim Wawrzynczak | a5cb564 | 2020-09-08 13:14:09 -0600 | [diff] [blame] | 419 | .max_power = 60000, |
| 420 | .time_window_min = 28 * MSECS_PER_SEC, |
| 421 | .time_window_max = 32 * MSECS_PER_SEC, |
| 422 | .granularity = 1000,}}" |
Tim Wawrzynczak | 07ac2ec | 2020-05-29 15:58:19 -0600 | [diff] [blame] | 423 | |
| 424 | ## Charger Performance Control (Control, mA) |
Tim Wawrzynczak | a5cb564 | 2020-09-08 13:14:09 -0600 | [diff] [blame] | 425 | register "controls.charger_perf" = "{ |
| 426 | [0] = { 255, 1700 }, |
| 427 | [1] = { 24, 1500 }, |
| 428 | [2] = { 16, 1000 }, |
| 429 | [3] = { 8, 500 }}" |
Tim Wawrzynczak | 07ac2ec | 2020-05-29 15:58:19 -0600 | [diff] [blame] | 430 | |
| 431 | ## Fan Performance Control (Percent, Speed, Noise, Power) |
Tim Wawrzynczak | a5cb564 | 2020-09-08 13:14:09 -0600 | [diff] [blame] | 432 | register "controls.fan_perf" = "{ |
| 433 | [0] = { 90, 6700, 220, 2200, }, |
| 434 | [1] = { 80, 5800, 180, 1800, }, |
| 435 | [2] = { 70, 5000, 145, 1450, }, |
| 436 | [3] = { 60, 4900, 115, 1150, }, |
| 437 | [4] = { 50, 3838, 90, 900, }, |
| 438 | [5] = { 40, 2904, 55, 550, }, |
| 439 | [6] = { 30, 2337, 30, 300, }, |
| 440 | [7] = { 20, 1608, 15, 150, }, |
| 441 | [8] = { 10, 800, 10, 100, }, |
| 442 | [9] = { 0, 0, 0, 50, }}" |
Tim Wawrzynczak | 07ac2ec | 2020-05-29 15:58:19 -0600 | [diff] [blame] | 443 | |
| 444 | # Fan options |
| 445 | register "options.fan.fine_grained_control" = "1" |
| 446 | register "options.fan.step_size" = "2" |
| 447 | |
| 448 | device generic 0 on end |
| 449 | end |
| 450 | end # DPTF 0x9A03 |
Duncan Laurie | 2b3de78 | 2020-10-28 14:26:26 -0700 | [diff] [blame] | 451 | # Volteer reference design does not have PCIe on Type-C port C0 so it should |
| 452 | # not have hotplug resources allocated. Marking the device hidden will ensure |
| 453 | # it is still enabled so it can participate in power management. |
| 454 | device ref tbt_pcie_rp0 hidden |
Brandon Breitenstein | 228d0e5 | 2020-07-23 14:40:14 -0700 | [diff] [blame] | 455 | probe DB_USB USB4_GEN2 |
| 456 | probe DB_USB USB4_GEN3 |
| 457 | end |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 458 | device ref tbt_pcie_rp1 on |
Brandon Breitenstein | 228d0e5 | 2020-07-23 14:40:14 -0700 | [diff] [blame] | 459 | probe DB_USB USB4_GEN2 |
| 460 | probe DB_USB USB4_GEN3 |
| 461 | end |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 462 | device ref tbt_dma0 on |
Brandon Breitenstein | 228d0e5 | 2020-07-23 14:40:14 -0700 | [diff] [blame] | 463 | probe DB_USB USB4_GEN2 |
| 464 | probe DB_USB USB4_GEN3 |
Duncan Laurie | 5b6ec3e | 2020-08-28 19:50:09 +0000 | [diff] [blame] | 465 | chip drivers/intel/usb4/retimer |
| 466 | register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H10)" |
| 467 | device generic 0 on end |
| 468 | end |
Brandon Breitenstein | 228d0e5 | 2020-07-23 14:40:14 -0700 | [diff] [blame] | 469 | end |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 470 | device ref gna on end |
| 471 | device ref north_xhci on end |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 472 | device ref south_xhci on end |
| 473 | device ref shared_ram on end |
Furquan Shaikh | edac4ef | 2020-10-09 08:50:14 -0700 | [diff] [blame] | 474 | device ref cnvi_wifi on |
| 475 | chip drivers/wifi/generic |
| 476 | register "wake" = "GPE0_PME_B0" |
| 477 | device generic 0 on end |
| 478 | end |
Srinidhi N Kaushik | ac7d6b4 | 2020-03-05 17:19:51 -0800 | [diff] [blame] | 479 | end |
Tim Wawrzynczak | c8340d4 | 2020-12-09 09:40:23 -0700 | [diff] [blame] | 480 | # MIPI camera devices are on I2C buses 2 and 3 |
| 481 | device ref i2c2 on end |
| 482 | device ref i2c3 on end |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 483 | device ref heci1 on end |
| 484 | device ref sata on end |
| 485 | device ref pcie_rp1 on end |
| 486 | device ref pcie_rp7 on end |
Duncan Laurie | 9d0fde3 | 2020-11-09 09:36:31 -0800 | [diff] [blame] | 487 | device ref pcie_rp8 on |
| 488 | probe DB_SD SD_GL9755S |
| 489 | probe DB_SD SD_RTS5261 |
Duncan Laurie | 912d9ec | 2020-11-30 10:09:42 -0800 | [diff] [blame] | 490 | probe DB_SD SD_RTS5227S |
| 491 | probe DB_SD SD_GL9750 |
| 492 | probe DB_SD SD_OZ711LV2LN |
Duncan Laurie | 9d0fde3 | 2020-11-09 09:36:31 -0800 | [diff] [blame] | 493 | chip soc/intel/common/block/pcie/rtd3 |
| 494 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" |
| 495 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)" |
| 496 | register "srcclk_pin" = "3" |
| 497 | device generic 0 on |
| 498 | probe DB_SD SD_GL9755S |
Duncan Laurie | 912d9ec | 2020-11-30 10:09:42 -0800 | [diff] [blame] | 499 | probe DB_SD SD_RTS5227S |
| 500 | probe DB_SD SD_GL9750 |
| 501 | probe DB_SD SD_OZ711LV2LN |
Duncan Laurie | 9d0fde3 | 2020-11-09 09:36:31 -0800 | [diff] [blame] | 502 | end |
| 503 | end |
| 504 | chip soc/intel/common/block/pcie/rtd3 |
| 505 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)" |
| 506 | register "srcclk_pin" = "3" |
| 507 | register "is_external" = "1" |
| 508 | device generic 1 on |
| 509 | probe DB_SD SD_RTS5261 |
| 510 | end |
| 511 | end |
| 512 | end |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 513 | device ref pcie_rp9 on end |
| 514 | device ref pcie_rp11 on end |
| 515 | device ref uart0 on end |
| 516 | device ref gspi0 on |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 517 | chip drivers/spi/acpi |
| 518 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 519 | register "compat_string" = ""google,cr50"" |
| 520 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" |
| 521 | device spi 0 on end |
| 522 | end |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 523 | end |
| 524 | device ref gspi1 on |
Alex Levin | 3bc41cf | 2020-03-06 10:54:10 -0800 | [diff] [blame] | 525 | chip drivers/spi/acpi |
| 526 | register "name" = ""CRFP"" |
| 527 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 528 | register "uid" = "1" |
| 529 | register "compat_string" = ""google,cros-ec-spi"" |
| 530 | register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" |
| 531 | device spi 0 on end |
| 532 | end # FPMCU |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 533 | end |
| 534 | device ref pch_espi on |
Nick Vaccaro | 9a3486e | 2020-04-17 10:14:57 -0700 | [diff] [blame] | 535 | chip ec/google/chromeec |
| 536 | device pnp 0c09.0 on end |
| 537 | end |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 538 | end |
Tim Wawrzynczak | 2f917e6 | 2020-12-09 10:11:06 -0700 | [diff] [blame] | 539 | device ref hda on |
| 540 | probe AUDIO MAX98357_ALC5682I_I2S |
| 541 | probe AUDIO MAX98373_ALC5682I_I2S |
| 542 | probe AUDIO MAX98373_ALC5682_SNDW |
| 543 | probe AUDIO MAX98373_ALC5682I_I2S_UP4 |
| 544 | probe AUDIO MAX98360_ALC5682I_I2S |
| 545 | end |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 546 | end |
| 547 | end |