Duncan Laurie | 9db8c25 | 2020-05-10 11:16:45 -0700 | [diff] [blame] | 1 | fw_config |
Nick Vaccaro | 2cc0600 | 2020-06-18 12:19:08 -0700 | [diff] [blame] | 2 | field DB_USB 0 3 |
| 3 | option USB_ABSENT 0 |
| 4 | option USB4_GEN2 1 |
| 5 | option USB3_ACTIVE 2 |
| 6 | option USB4_GEN3 3 |
| 7 | option USB3_PASSIVE 4 |
| 8 | option USB3_NO_A 5 |
Duncan Laurie | 5abf040 | 2020-10-28 15:14:27 -0700 | [diff] [blame] | 9 | option USB3_NO_C 6 |
Duncan Laurie | 9db8c25 | 2020-05-10 11:16:45 -0700 | [diff] [blame] | 10 | end |
| 11 | field THERMAL 4 7 end |
| 12 | field AUDIO 8 10 |
| 13 | option NONE 0 |
| 14 | option MAX98357_ALC5682I_I2S 1 |
| 15 | option MAX98373_ALC5682I_I2S 2 |
| 16 | option MAX98373_ALC5682_SNDW 3 |
Frank Wu | 362bcee | 2020-08-19 09:56:43 +0800 | [diff] [blame] | 17 | option MAX98373_ALC5682I_I2S_UP4 4 |
Wisley Chen | 35010ef | 2020-11-06 17:16:59 +0800 | [diff] [blame] | 18 | option MAX98360_ALC5682I_I2S 5 |
Stanley Wu | 64f7bdf | 2020-10-30 12:01:20 +0800 | [diff] [blame] | 19 | option RT1011_ALC5682I_I2S 6 |
Duncan Laurie | 9db8c25 | 2020-05-10 11:16:45 -0700 | [diff] [blame] | 20 | end |
| 21 | field TABLETMODE 11 |
Nick Vaccaro | 2cc0600 | 2020-06-18 12:19:08 -0700 | [diff] [blame] | 22 | option TABLETMODE_DISABLED 0 |
| 23 | option TABLETMODE_ENABLED 1 |
Duncan Laurie | 9db8c25 | 2020-05-10 11:16:45 -0700 | [diff] [blame] | 24 | end |
Nick Vaccaro | 2cc0600 | 2020-06-18 12:19:08 -0700 | [diff] [blame] | 25 | field DB_LTE 12 13 |
| 26 | option LTE_ABSENT 0 |
| 27 | option LTE_PRESENT 1 |
| 28 | end |
Duncan Laurie | 14efbb4 | 2020-09-08 20:35:06 +0000 | [diff] [blame] | 29 | field KB_BL 14 |
| 30 | option KB_BL_ABSENT 0 |
| 31 | option KB_BL_PRESENT 1 |
| 32 | end |
| 33 | field NUMPAD 15 |
| 34 | option NUMPAD_ABSENT 0 |
| 35 | option NUMPAD_PRESENT 1 |
| 36 | end |
Nick Vaccaro | 2cc0600 | 2020-06-18 12:19:08 -0700 | [diff] [blame] | 37 | field DB_SD 16 19 |
| 38 | option SD_ABSENT 0 |
| 39 | option SD_GL9755S 1 |
| 40 | option SD_RTS5261 2 |
Zhuohao Lee | b3b4ccf | 2020-11-23 11:41:25 +0800 | [diff] [blame] | 41 | option SD_RTS5227S 3 |
Duncan Laurie | 912d9ec | 2020-11-30 10:09:42 -0800 | [diff] [blame^] | 42 | option SD_GL9750 4 |
Zhuohao Lee | b3b4ccf | 2020-11-23 11:41:25 +0800 | [diff] [blame] | 43 | option SD_OZ711LV2LN 5 |
Duncan Laurie | 9db8c25 | 2020-05-10 11:16:45 -0700 | [diff] [blame] | 44 | end |
Duncan Laurie | bd04995 | 2020-11-11 13:01:27 -0800 | [diff] [blame] | 45 | field KB_LAYOUT 20 21 |
| 46 | option KB_LAYOUT_DEFAULT 0 |
| 47 | option KB_LAYOUT_1 1 |
| 48 | end |
Duncan Laurie | 9db8c25 | 2020-05-10 11:16:45 -0700 | [diff] [blame] | 49 | end |
| 50 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 51 | chip soc/intel/tigerlake |
| 52 | |
| 53 | device cpu_cluster 0 on |
| 54 | device lapic 0 on end |
| 55 | end |
| 56 | |
| 57 | # GPE configuration |
| 58 | # Note that GPE events called out in ASL code rely on this |
| 59 | # route. i.e. If this route changes then the affected GPE |
| 60 | # offset bits also need to be changed. |
| 61 | register "pmc_gpe0_dw0" = "GPP_C" |
| 62 | register "pmc_gpe0_dw1" = "GPP_D" |
| 63 | register "pmc_gpe0_dw2" = "GPP_E" |
| 64 | |
Jamie Ryu | 154625b | 2020-06-12 02:59:26 -0700 | [diff] [blame] | 65 | # Enable heci communication |
| 66 | register "HeciEnabled" = "1" |
| 67 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 68 | # FSP configuration |
Shreesh Chhabbi | 3708687 | 2020-06-17 12:40:42 -0700 | [diff] [blame] | 69 | register "SaGv" = "SaGv_Enabled" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 70 | register "SmbusEnable" = "0" |
| 71 | |
| 72 | register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 |
| 73 | register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 |
| 74 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN |
| 75 | register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Cl |
| 76 | register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 77 | register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Co |
| 78 | register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth |
| 79 | |
| 80 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 |
| 81 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 |
| 82 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN |
| 83 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 Camera |
| 84 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 85 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 86 | register "gen1_dec" = "0x00fc0801" |
| 87 | register "gen2_dec" = "0x000c0201" |
| 88 | # EC memory map range is 0x900-0x9ff |
| 89 | register "gen3_dec" = "0x00fc0901" |
| 90 | |
| 91 | # Enable NVMe PCIE 9 using clk 0 |
| 92 | register "PcieRpEnable[8]" = "1" |
Wonkyu Kim | e3bf8ba | 2020-04-07 23:34:12 -0700 | [diff] [blame] | 93 | register "PcieRpLtrEnable[8]" = "1" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 94 | register "PcieClkSrcUsage[0]" = "8" |
| 95 | register "PcieClkSrcClkReq[0]" = "0" |
| 96 | |
Venkata Krishna Nimmagadda | c34bb38 | 2020-01-15 10:13:26 -0800 | [diff] [blame] | 97 | # Enable Optane PCIE 11 using clk 0 |
| 98 | register "PcieRpEnable[10]" = "1" |
Wonkyu Kim | e3bf8ba | 2020-04-07 23:34:12 -0700 | [diff] [blame] | 99 | register "PcieRpLtrEnable[10]" = "1" |
Shaunak Saha | b27b0fd | 2020-09-22 23:09:24 -0700 | [diff] [blame] | 100 | register "HybridStorageMode" = "0" |
Venkata Krishna Nimmagadda | c34bb38 | 2020-01-15 10:13:26 -0800 | [diff] [blame] | 101 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 102 | # Enable SD Card PCIE 8 using clk 3 |
| 103 | register "PcieRpEnable[7]" = "1" |
Wonkyu Kim | e3bf8ba | 2020-04-07 23:34:12 -0700 | [diff] [blame] | 104 | register "PcieRpLtrEnable[7]" = "1" |
nick_xr_chen | f446b81 | 2020-06-30 09:34:33 +0800 | [diff] [blame] | 105 | register "PcieRpHotPlug[7]" = "1" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 106 | register "PcieClkSrcUsage[3]" = "7" |
| 107 | register "PcieClkSrcClkReq[3]" = "3" |
| 108 | |
| 109 | # Enable WLAN PCIE 7 using clk 1 |
| 110 | register "PcieRpEnable[6]" = "1" |
Wonkyu Kim | e3bf8ba | 2020-04-07 23:34:12 -0700 | [diff] [blame] | 111 | register "PcieRpLtrEnable[6]" = "1" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 112 | register "PcieClkSrcUsage[1]" = "6" |
| 113 | register "PcieClkSrcClkReq[1]" = "1" |
| 114 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 115 | # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality |
David Wu | 7d1a137 | 2020-10-21 10:42:25 +0800 | [diff] [blame] | 116 | register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" |
| 117 | register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" |
| 118 | register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" |
| 119 | register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 120 | |
| 121 | # Enable SATA |
| 122 | register "SataEnable" = "1" |
| 123 | register "SataMode" = "0" |
| 124 | register "SataSalpSupport" = "1" |
| 125 | register "SataPortsEnable[0]" = "0" |
| 126 | register "SataPortsEnable[1]" = "1" |
| 127 | register "SataPortsDevSlp[0]" = "0" |
Wonkyu Kim | b8bfe14 | 2020-04-21 17:07:57 -0700 | [diff] [blame] | 128 | register "SataPortsDevSlp[1]" = "1" |
Shaunak Saha | 60e6f6e | 2020-06-15 23:59:52 -0700 | [diff] [blame] | 129 | register "SataPortsEnableDitoConfig[1]" = "1" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 130 | |
| 131 | register "SerialIoI2cMode" = "{ |
| 132 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 133 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 134 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 135 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 136 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 137 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 138 | }" |
| 139 | |
| 140 | register "SerialIoGSpiMode" = "{ |
| 141 | [PchSerialIoIndexGSPI0] = PchSerialIoPci, |
| 142 | [PchSerialIoIndexGSPI1] = PchSerialIoPci, |
| 143 | [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, |
| 144 | [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, |
| 145 | }" |
| 146 | |
| 147 | register "SerialIoGSpiCsMode" = "{ |
| 148 | [PchSerialIoIndexGSPI0] = 1, |
| 149 | [PchSerialIoIndexGSPI1] = 1, |
| 150 | [PchSerialIoIndexGSPI2] = 0, |
| 151 | [PchSerialIoIndexGSPI3] = 0, |
| 152 | }" |
| 153 | |
| 154 | register "SerialIoGSpiCsState" = "{ |
Caveh Jalali | 85e4c43 | 2020-09-12 03:05:48 -0700 | [diff] [blame] | 155 | [PchSerialIoIndexGSPI0] = 1, |
| 156 | [PchSerialIoIndexGSPI1] = 1, |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 157 | [PchSerialIoIndexGSPI2] = 0, |
| 158 | [PchSerialIoIndexGSPI3] = 0, |
| 159 | }" |
| 160 | |
| 161 | register "SerialIoUartMode" = "{ |
| 162 | [PchSerialIoIndexUART0] = PchSerialIoPci, |
| 163 | [PchSerialIoIndexUART1] = PchSerialIoDisabled, |
| 164 | [PchSerialIoIndexUART2] = PchSerialIoDisabled, |
| 165 | }" |
| 166 | |
Jamie Ryu | 8053595 | 2020-08-18 19:10:43 -0700 | [diff] [blame] | 167 | # Set the minimum assertion width |
| 168 | # PchPmSlpS3MinAssert: |
| 169 | # - 1: 60us |
| 170 | # - 2: 1ms |
| 171 | # - 3: 50ms |
| 172 | # - 4: 2s |
| 173 | register "PchPmSlpS3MinAssert" = "3" # 50ms |
| 174 | # PchPmSlpS4MinAssert: |
| 175 | # - 1 = 1s |
| 176 | # - 2 = 2s |
| 177 | # - 3 = 3s |
| 178 | # - 4 = 4s |
| 179 | register "PchPmSlpS4MinAssert" = "1" # 1s |
| 180 | # PchPmSlpSusMinAssert: |
| 181 | # - 1 = 0ms |
| 182 | # - 2 = 500ms |
| 183 | # - 3 = 1s |
| 184 | # - 4 = 4s |
| 185 | register "PchPmSlpSusMinAssert" = "3" # 1s |
| 186 | # PchPmSlpAMinAssert |
| 187 | # - 1 = 0ms |
| 188 | # - 2 = 4s |
| 189 | # - 3 = 98ms |
| 190 | # - 4 = 2s |
| 191 | register "PchPmSlpAMinAssert" = "3" # 98ms |
| 192 | |
| 193 | # NOTE: Duration programmed in the below register should never be smaller than the |
| 194 | # stretch duration programmed in the following registers - |
| 195 | # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) |
| 196 | # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) |
| 197 | # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) |
| 198 | # - PM_CFG.SLP_LAN_MIN_ASST_WDTH |
| 199 | register "PchPmPwrCycDur" = "1" # 1s |
| 200 | |
Srinidhi N Kaushik | 22d5b07 | 2020-03-06 10:47:17 -0800 | [diff] [blame] | 201 | # HD Audio |
| 202 | register "PchHdaDspEnable" = "1" |
| 203 | register "PchHdaAudioLinkHdaEnable" = "0" |
Duncan Laurie | 4dffa9c | 2020-05-10 11:20:20 -0700 | [diff] [blame] | 204 | register "PchHdaAudioLinkDmicEnable[0]" = "0" |
| 205 | register "PchHdaAudioLinkDmicEnable[1]" = "0" |
| 206 | register "PchHdaAudioLinkSspEnable[0]" = "0" |
| 207 | register "PchHdaAudioLinkSspEnable[1]" = "0" |
| 208 | register "PchHdaAudioLinkSndwEnable[0]" = "0" |
| 209 | register "PchHdaAudioLinkSndwEnable[1]" = "0" |
Srinidhi N Kaushik | 22d5b07 | 2020-03-06 10:47:17 -0800 | [diff] [blame] | 210 | |
Brandon Breitenstein | 01ec713 | 2020-03-06 10:51:30 -0800 | [diff] [blame] | 211 | # TCSS USB3 |
| 212 | register "TcssXhciEn" = "1" |
Brandon Breitenstein | 1df3b70 | 2020-08-10 15:02:41 -0700 | [diff] [blame] | 213 | register "TcssAuxOri" = "0" |
| 214 | register "IomTypeCPortPadCfg[0]" = "0x09000000" |
| 215 | register "IomTypeCPortPadCfg[1]" = "0x09000000" |
Brandon Breitenstein | c9a3451 | 2020-06-10 17:04:29 -0700 | [diff] [blame] | 216 | register "IomTypeCPortPadCfg[2]" = "0x09000000" |
| 217 | register "IomTypeCPortPadCfg[3]" = "0x09000000" |
| 218 | register "IomTypeCPortPadCfg[4]" = "0x09000000" |
| 219 | register "IomTypeCPortPadCfg[5]" = "0x09000000" |
| 220 | register "IomTypeCPortPadCfg[6]" = "0x09000000" |
| 221 | register "IomTypeCPortPadCfg[7]" = "0x09000000" |
Brandon Breitenstein | b7911c8 | 2020-04-06 15:34:19 -0700 | [diff] [blame] | 222 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 223 | # DP port |
| 224 | register "DdiPortAConfig" = "1" # eDP |
| 225 | register "DdiPortBConfig" = "0" |
| 226 | |
| 227 | register "DdiPortAHpd" = "1" |
| 228 | register "DdiPortBHpd" = "1" |
| 229 | register "DdiPortCHpd" = "0" |
| 230 | register "DdiPort1Hpd" = "1" |
| 231 | register "DdiPort2Hpd" = "1" |
| 232 | register "DdiPort3Hpd" = "0" |
| 233 | register "DdiPort4Hpd" = "0" |
| 234 | |
| 235 | register "DdiPortADdc" = "0" |
| 236 | register "DdiPortBDdc" = "1" |
| 237 | register "DdiPortCDdc" = "0" |
| 238 | register "DdiPort1Ddc" = "0" |
| 239 | register "DdiPort2Ddc" = "0" |
| 240 | register "DdiPort3Ddc" = "0" |
| 241 | register "DdiPort4Ddc" = "0" |
| 242 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 243 | # Enable S0ix |
| 244 | register "s0ix_enable" = "1" |
| 245 | |
Sumeet R Pawnikar | 7d6bc60 | 2020-05-08 19:22:07 +0530 | [diff] [blame] | 246 | # Enable DPTF |
| 247 | register "dptf_enable" = "1" |
| 248 | |
Sumeet R Pawnikar | 1a62150 | 2020-07-20 15:44:59 +0530 | [diff] [blame] | 249 | register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ |
| 250 | .tdp_pl1_override = 15, |
| 251 | .tdp_pl2_override = 38, |
| 252 | .tdp_pl4 = 71, |
| 253 | }" |
Tim Wawrzynczak | 2dcca0f | 2020-06-16 10:50:47 -0600 | [diff] [blame] | 254 | register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ |
Sumeet R Pawnikar | 7d6bc60 | 2020-05-08 19:22:07 +0530 | [diff] [blame] | 255 | .tdp_pl1_override = 15, |
| 256 | .tdp_pl2_override = 60, |
Tim Wawrzynczak | 2dcca0f | 2020-06-16 10:50:47 -0600 | [diff] [blame] | 257 | .tdp_pl4 = 105, |
| 258 | }" |
Sumeet R Pawnikar | 1a62150 | 2020-07-20 15:44:59 +0530 | [diff] [blame] | 259 | register "power_limits_config[POWER_LIMITS_Y_2_CORE]" = "{ |
| 260 | .tdp_pl1_override = 9, |
| 261 | .tdp_pl2_override = 35, |
| 262 | .tdp_pl4 = 66, |
| 263 | }" |
| 264 | register "power_limits_config[POWER_LIMITS_Y_4_CORE]" = "{ |
| 265 | .tdp_pl1_override = 9, |
| 266 | .tdp_pl2_override = 40, |
| 267 | .tdp_pl4 = 83, |
Sumeet R Pawnikar | 7d6bc60 | 2020-05-08 19:22:07 +0530 | [diff] [blame] | 268 | }" |
| 269 | |
| 270 | register "Device4Enable" = "1" |
| 271 | |
Sumeet R Pawnikar | 9f9b97e | 2020-06-30 14:18:41 +0530 | [diff] [blame] | 272 | register "tcc_offset" = "10" # TCC of 90 |
| 273 | |
John Zhao | c8e3097 | 2020-09-21 13:20:57 -0700 | [diff] [blame] | 274 | register "CnviBtAudioOffload" = "FORCE_ENABLE" |
| 275 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 276 | # Intel Common SoC Config |
| 277 | #+-------------------+---------------------------+ |
| 278 | #| Field | Value | |
| 279 | #+-------------------+---------------------------+ |
| 280 | #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | |
| 281 | #| GSPI0 | cr50 TPM. Early init is | |
| 282 | #| | required to set up a BAR | |
| 283 | #| | for TPM communication | |
| 284 | #| | before memory is up | |
Alex Levin | 3bc41cf | 2020-03-06 10:54:10 -0800 | [diff] [blame] | 285 | #| GSPI1 | Fingerprint MCU | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 286 | #| I2C0 | Audio | |
| 287 | #| I2C1 | Touchscreen | |
| 288 | #| I2C2 | WLAN, SAR0 | |
| 289 | #| I2C3 | Camera, SAR1 | |
| 290 | #| I2C5 | Trackpad | |
| 291 | #+-------------------+---------------------------+ |
| 292 | register "common_soc_config" = "{ |
| 293 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 294 | .gspi[0] = { |
| 295 | .speed_mhz = 1, |
| 296 | .early_init = 1, |
| 297 | }, |
| 298 | .i2c[0] = { |
| 299 | .speed = I2C_SPEED_FAST, |
| 300 | }, |
| 301 | .i2c[1] = { |
| 302 | .speed = I2C_SPEED_FAST, |
| 303 | }, |
| 304 | .i2c[2] = { |
| 305 | .speed = I2C_SPEED_FAST, |
| 306 | }, |
| 307 | .i2c[3] = { |
| 308 | .speed = I2C_SPEED_FAST, |
| 309 | }, |
| 310 | .i2c[5] = { |
| 311 | .speed = I2C_SPEED_FAST, |
| 312 | }, |
| 313 | }" |
| 314 | |
Venkata Krishna Nimmagadda | 7368da3 | 2020-06-09 00:11:34 -0700 | [diff] [blame] | 315 | register "ext_fivr_settings" = "{ |
| 316 | .configure_ext_fivr = 1, |
| 317 | .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, |
| 318 | .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, |
| 319 | .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | |
| 320 | FIVR_VOLTAGE_MIN_ACTIVE | |
| 321 | FIVR_VOLTAGE_MIN_RETENTION, |
| 322 | .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | |
| 323 | FIVR_VOLTAGE_MIN_ACTIVE | |
| 324 | FIVR_VOLTAGE_MIN_RETENTION, |
| 325 | .v1p05_icc_max_ma = 500, |
| 326 | .vnn_sx_voltage_mv = 1250, |
| 327 | }" |
| 328 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 329 | device domain 0 on |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 330 | device ref igpu on end |
| 331 | device ref dptf on |
Tim Wawrzynczak | 07ac2ec | 2020-05-29 15:58:19 -0600 | [diff] [blame] | 332 | # Default DPTF Policy for all Volteer boards if not overridden |
| 333 | chip drivers/intel/dptf |
| 334 | ## Active Policy |
Tim Wawrzynczak | a5cb564 | 2020-09-08 13:14:09 -0600 | [diff] [blame] | 335 | register "policies.active" = "{ |
| 336 | [0] = {.target = DPTF_CPU, |
| 337 | .thresholds = {TEMP_PCT(85, 90), |
| 338 | TEMP_PCT(80, 69), |
| 339 | TEMP_PCT(75, 56), |
| 340 | TEMP_PCT(70, 46), |
| 341 | TEMP_PCT(65, 36),}}, |
| 342 | [1] = {.target = DPTF_TEMP_SENSOR_0, |
| 343 | .thresholds = {TEMP_PCT(50, 90), |
| 344 | TEMP_PCT(47, 69), |
| 345 | TEMP_PCT(45, 56), |
| 346 | TEMP_PCT(42, 46), |
| 347 | TEMP_PCT(39, 36),}}, |
| 348 | [2] = {.target = DPTF_TEMP_SENSOR_1, |
| 349 | .thresholds = {TEMP_PCT(50, 90), |
| 350 | TEMP_PCT(47, 69), |
| 351 | TEMP_PCT(45, 56), |
| 352 | TEMP_PCT(42, 46), |
| 353 | TEMP_PCT(39, 36),}}, |
| 354 | [3] = {.target = DPTF_TEMP_SENSOR_2, |
| 355 | .thresholds = {TEMP_PCT(50, 90), |
| 356 | TEMP_PCT(47, 69), |
| 357 | TEMP_PCT(45, 56), |
| 358 | TEMP_PCT(42, 46), |
| 359 | TEMP_PCT(39, 36),}}, |
| 360 | [4] = {.target = DPTF_TEMP_SENSOR_3, |
| 361 | .thresholds = {TEMP_PCT(50, 90), |
| 362 | TEMP_PCT(47, 69), |
| 363 | TEMP_PCT(45, 56), |
| 364 | TEMP_PCT(42, 46), |
| 365 | TEMP_PCT(39, 36),}}}" |
Tim Wawrzynczak | 07ac2ec | 2020-05-29 15:58:19 -0600 | [diff] [blame] | 366 | |
| 367 | ## Passive Policy |
Tim Wawrzynczak | a5cb564 | 2020-09-08 13:14:09 -0600 | [diff] [blame] | 368 | register "policies.passive" = "{ |
| 369 | [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), |
| 370 | [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), |
| 371 | [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), |
| 372 | [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000), |
| 373 | [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" |
Tim Wawrzynczak | 07ac2ec | 2020-05-29 15:58:19 -0600 | [diff] [blame] | 374 | |
| 375 | ## Critical Policy |
Tim Wawrzynczak | a5cb564 | 2020-09-08 13:14:09 -0600 | [diff] [blame] | 376 | register "policies.critical" = "{ |
| 377 | [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), |
| 378 | [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), |
| 379 | [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), |
| 380 | [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), |
| 381 | [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" |
Tim Wawrzynczak | 07ac2ec | 2020-05-29 15:58:19 -0600 | [diff] [blame] | 382 | |
| 383 | ## Power Limits Control |
Sumeet R Pawnikar | 88352c5 | 2020-10-08 21:15:42 +0530 | [diff] [blame] | 384 | # 3-15W PL1 in 200mW increments, avg over 28-32s interval |
| 385 | # PL2 ranges from 15 to 60W, avg over 28-32s interval |
Tim Wawrzynczak | a5cb564 | 2020-09-08 13:14:09 -0600 | [diff] [blame] | 386 | register "controls.power_limits" = "{ |
| 387 | .pl1 = {.min_power = 3000, |
| 388 | .max_power = 15000, |
| 389 | .time_window_min = 28 * MSECS_PER_SEC, |
| 390 | .time_window_max = 32 * MSECS_PER_SEC, |
| 391 | .granularity = 200,}, |
| 392 | .pl2 = {.min_power = 15000, |
| 393 | .max_power = 60000, |
| 394 | .time_window_min = 28 * MSECS_PER_SEC, |
| 395 | .time_window_max = 32 * MSECS_PER_SEC, |
| 396 | .granularity = 1000,}}" |
Tim Wawrzynczak | 07ac2ec | 2020-05-29 15:58:19 -0600 | [diff] [blame] | 397 | |
| 398 | ## Charger Performance Control (Control, mA) |
Tim Wawrzynczak | a5cb564 | 2020-09-08 13:14:09 -0600 | [diff] [blame] | 399 | register "controls.charger_perf" = "{ |
| 400 | [0] = { 255, 1700 }, |
| 401 | [1] = { 24, 1500 }, |
| 402 | [2] = { 16, 1000 }, |
| 403 | [3] = { 8, 500 }}" |
Tim Wawrzynczak | 07ac2ec | 2020-05-29 15:58:19 -0600 | [diff] [blame] | 404 | |
| 405 | ## Fan Performance Control (Percent, Speed, Noise, Power) |
Tim Wawrzynczak | a5cb564 | 2020-09-08 13:14:09 -0600 | [diff] [blame] | 406 | register "controls.fan_perf" = "{ |
| 407 | [0] = { 90, 6700, 220, 2200, }, |
| 408 | [1] = { 80, 5800, 180, 1800, }, |
| 409 | [2] = { 70, 5000, 145, 1450, }, |
| 410 | [3] = { 60, 4900, 115, 1150, }, |
| 411 | [4] = { 50, 3838, 90, 900, }, |
| 412 | [5] = { 40, 2904, 55, 550, }, |
| 413 | [6] = { 30, 2337, 30, 300, }, |
| 414 | [7] = { 20, 1608, 15, 150, }, |
| 415 | [8] = { 10, 800, 10, 100, }, |
| 416 | [9] = { 0, 0, 0, 50, }}" |
Tim Wawrzynczak | 07ac2ec | 2020-05-29 15:58:19 -0600 | [diff] [blame] | 417 | |
| 418 | # Fan options |
| 419 | register "options.fan.fine_grained_control" = "1" |
| 420 | register "options.fan.step_size" = "2" |
| 421 | |
| 422 | device generic 0 on end |
| 423 | end |
| 424 | end # DPTF 0x9A03 |
Duncan Laurie | 2b3de78 | 2020-10-28 14:26:26 -0700 | [diff] [blame] | 425 | # Volteer reference design does not have PCIe on Type-C port C0 so it should |
| 426 | # not have hotplug resources allocated. Marking the device hidden will ensure |
| 427 | # it is still enabled so it can participate in power management. |
| 428 | device ref tbt_pcie_rp0 hidden |
Brandon Breitenstein | 228d0e5 | 2020-07-23 14:40:14 -0700 | [diff] [blame] | 429 | probe DB_USB USB4_GEN2 |
| 430 | probe DB_USB USB4_GEN3 |
| 431 | end |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 432 | device ref tbt_pcie_rp1 on |
Brandon Breitenstein | 228d0e5 | 2020-07-23 14:40:14 -0700 | [diff] [blame] | 433 | probe DB_USB USB4_GEN2 |
| 434 | probe DB_USB USB4_GEN3 |
| 435 | end |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 436 | device ref tbt_dma0 on |
Brandon Breitenstein | 228d0e5 | 2020-07-23 14:40:14 -0700 | [diff] [blame] | 437 | probe DB_USB USB4_GEN2 |
| 438 | probe DB_USB USB4_GEN3 |
Duncan Laurie | 5b6ec3e | 2020-08-28 19:50:09 +0000 | [diff] [blame] | 439 | chip drivers/intel/usb4/retimer |
| 440 | register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H10)" |
| 441 | device generic 0 on end |
| 442 | end |
Brandon Breitenstein | 228d0e5 | 2020-07-23 14:40:14 -0700 | [diff] [blame] | 443 | end |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 444 | device ref gna on end |
| 445 | device ref north_xhci on end |
| 446 | device ref cnvi_bt on end |
| 447 | device ref south_xhci on end |
| 448 | device ref shared_ram on end |
Furquan Shaikh | edac4ef | 2020-10-09 08:50:14 -0700 | [diff] [blame] | 449 | device ref cnvi_wifi on |
| 450 | chip drivers/wifi/generic |
| 451 | register "wake" = "GPE0_PME_B0" |
| 452 | device generic 0 on end |
| 453 | end |
Srinidhi N Kaushik | ac7d6b4 | 2020-03-05 17:19:51 -0800 | [diff] [blame] | 454 | end |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 455 | device ref heci1 on end |
| 456 | device ref sata on end |
| 457 | device ref pcie_rp1 on end |
| 458 | device ref pcie_rp7 on end |
Duncan Laurie | 9d0fde3 | 2020-11-09 09:36:31 -0800 | [diff] [blame] | 459 | device ref pcie_rp8 on |
| 460 | probe DB_SD SD_GL9755S |
| 461 | probe DB_SD SD_RTS5261 |
Duncan Laurie | 912d9ec | 2020-11-30 10:09:42 -0800 | [diff] [blame^] | 462 | probe DB_SD SD_RTS5227S |
| 463 | probe DB_SD SD_GL9750 |
| 464 | probe DB_SD SD_OZ711LV2LN |
Duncan Laurie | 9d0fde3 | 2020-11-09 09:36:31 -0800 | [diff] [blame] | 465 | chip soc/intel/common/block/pcie/rtd3 |
| 466 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" |
| 467 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)" |
| 468 | register "srcclk_pin" = "3" |
| 469 | device generic 0 on |
| 470 | probe DB_SD SD_GL9755S |
Duncan Laurie | 912d9ec | 2020-11-30 10:09:42 -0800 | [diff] [blame^] | 471 | probe DB_SD SD_RTS5227S |
| 472 | probe DB_SD SD_GL9750 |
| 473 | probe DB_SD SD_OZ711LV2LN |
Duncan Laurie | 9d0fde3 | 2020-11-09 09:36:31 -0800 | [diff] [blame] | 474 | end |
| 475 | end |
| 476 | chip soc/intel/common/block/pcie/rtd3 |
| 477 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)" |
| 478 | register "srcclk_pin" = "3" |
| 479 | register "is_external" = "1" |
| 480 | device generic 1 on |
| 481 | probe DB_SD SD_RTS5261 |
| 482 | end |
| 483 | end |
| 484 | end |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 485 | device ref pcie_rp9 on end |
| 486 | device ref pcie_rp11 on end |
| 487 | device ref uart0 on end |
| 488 | device ref gspi0 on |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 489 | chip drivers/spi/acpi |
| 490 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 491 | register "compat_string" = ""google,cr50"" |
| 492 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" |
| 493 | device spi 0 on end |
| 494 | end |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 495 | end |
| 496 | device ref gspi1 on |
Alex Levin | 3bc41cf | 2020-03-06 10:54:10 -0800 | [diff] [blame] | 497 | chip drivers/spi/acpi |
| 498 | register "name" = ""CRFP"" |
| 499 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 500 | register "uid" = "1" |
| 501 | register "compat_string" = ""google,cros-ec-spi"" |
| 502 | register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" |
| 503 | device spi 0 on end |
| 504 | end # FPMCU |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 505 | end |
| 506 | device ref pch_espi on |
Nick Vaccaro | 9a3486e | 2020-04-17 10:14:57 -0700 | [diff] [blame] | 507 | chip ec/google/chromeec |
| 508 | device pnp 0c09.0 on end |
| 509 | end |
Duncan Laurie | b0e169a | 2020-07-29 16:33:10 -0700 | [diff] [blame] | 510 | end |
| 511 | device ref hda on end |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 512 | end |
| 513 | end |