| commit | 9f9b97e6bc57a9a80c6f75046a3987b223433e10 | [log] [tgz] |
|---|---|---|
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | Tue Jun 30 14:18:41 2020 +0530 |
| committer | Patrick Georgi <pgeorgi@google.com> | Tue Jun 30 18:08:31 2020 +0000 |
| tree | 642992d1c9d823e06f435aef1481731f7d1c6f72 | |
| parent | 6caa4769c763b10a440637ce9c8d11ef1764c90d [diff] [blame] |
mb/google/volteer: set tcc_offset value to 10 Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. BUG=None BRANCH=None TEST=Built for volteer platform and verified the MSR value Change-Id: I6438547e09a3ff3a1c01addfcc01383e89f5b435 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 0c581a5..300fb7e 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -222,6 +222,8 @@ register "Device4Enable" = "1" + register "tcc_offset" = "10" # TCC of 90 + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value |