commit 7d1a137b845ad0b4d1aa1553070b26411b899cf6
author David Wu <david_wu@quanta.corp-partner.google.com> Wed Oct 21 10:42:25 2020 +0800
committer Patrick Georgi <pgeorgi@google.com> Mon Oct 26 06:43:45 2020 +0000
tree 8388c4a24c83e669cd081c7e783f41bf72c29058
parent e738a7e337a7446a7dee6e1ddb540c4fa4919a26

mb/google/volteer: Use PCIE_CLK_NOTUSED in place of 0xFF

Use PCIE_CLK_NOTUSED in place of 0xFF for unused PCIe ports

BUG=none
BRANCH=master
TEST="emerge-volteer coreboot" compiles successfully.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I35f2bbce35420fa98541a35f77b14df7440e7980
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/mainboard/google/volteer/variants/baseboard/devicetree.cb

diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 7486aef..b76f627 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -103,10 +103,10 @@
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality
-	register "PcieClkSrcUsage[2]" = "0xFF"
-	register "PcieClkSrcUsage[4]" = "0xFF"
-	register "PcieClkSrcUsage[5]" = "0xFF"
-	register "PcieClkSrcUsage[6]" = "0xFF"
+	register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"
 
 	# Enable SATA
 	register "SataEnable" = "1"