src/mainboard/google/volteer/variants/baseboard/devicetree.cb

fw_config
	field DB_USB 0 3
		option USB_ABSENT 0
		option USB4_GEN2 1
		option USB3_ACTIVE 2
		option USB4_GEN3 3
		option USB3_PASSIVE 4
		option USB3_NO_A 5
	end
	field THERMAL 4 7 end
	field AUDIO 8 10
		option NONE 0
		option MAX98357_ALC5682I_I2S 1
		option MAX98373_ALC5682I_I2S 2
		option MAX98373_ALC5682_SNDW 3
	end
	field TABLETMODE 11
		option TABLETMODE_DISABLED 0
		option TABLETMODE_ENABLED 1
	end
	field DB_LTE 12 13
		option LTE_ABSENT 0
		option LTE_PRESENT 1
	end
	field DB_SD 16 19
		option SD_ABSENT 0
		option SD_GL9755S 1
		option SD_RTS5261 2
	end
end

chip soc/intel/tigerlake

	device cpu_cluster 0 on
		device lapic 0 on end
	end

	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	register "pmc_gpe0_dw0" = "GPP_C"
	register "pmc_gpe0_dw1" = "GPP_D"
	register "pmc_gpe0_dw2" = "GPP_E"

	# Enable heci communication
	register "HeciEnabled" = "1"

	# FSP configuration
	register "SaGv" = "SaGv_Enabled"
	register "SmbusEnable" = "0"

	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0
	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A1
	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C Cl
	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Camera
	register "usb2_ports[5]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
	register "usb2_ports[6]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C Co
	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth

	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port A0
	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"	# USB3/2 Type A port A1
	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN
	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 Camera

	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
	register "gen1_dec" = "0x00fc0801"
	register "gen2_dec" = "0x000c0201"
	# EC memory map range is 0x900-0x9ff
	register "gen3_dec" = "0x00fc0901"

	# Enable NVMe PCIE 9 using clk 0
	register "PcieRpEnable[8]" = "1"
	register "PcieRpLtrEnable[8]" = "1"
	register "PcieClkSrcUsage[0]" = "8"
	register "PcieClkSrcClkReq[0]" = "0"

	# Enable Optane PCIE 11 using clk 0
	register "PcieRpEnable[10]" = "1"
	register "PcieRpLtrEnable[10]" = "1"
	register "HybridStorageMode" = "1"

	# Enable SD Card PCIE 8 using clk 3
	register "PcieRpEnable[7]" = "1"
	register "PcieRpLtrEnable[7]" = "1"
	register "PcieRpHotPlug[7]" = "1"
	register "PcieClkSrcUsage[3]" = "7"
	register "PcieClkSrcClkReq[3]" = "3"

	# Enable WLAN PCIE 7 using clk 1
	register "PcieRpEnable[6]" = "1"
	register "PcieRpLtrEnable[6]" = "1"
	register "PcieClkSrcUsage[1]" = "6"
	register "PcieClkSrcClkReq[1]" = "1"

	# Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality
	register "PcieClkSrcUsage[2]" = "0xFF"
	register "PcieClkSrcUsage[4]" = "0xFF"
	register "PcieClkSrcUsage[5]" = "0xFF"
	register "PcieClkSrcUsage[6]" = "0xFF"

	# Enable SATA
	register "SataEnable" = "1"
	register "SataMode" = "0"
	register "SataSalpSupport" = "1"
	register "SataPortsEnable[0]" = "0"
	register "SataPortsEnable[1]" = "1"
	register "SataPortsDevSlp[0]" = "0"
	register "SataPortsDevSlp[1]" = "1"
	register "SataPortsEnableDitoConfig[1]" = "1"

	register "SerialIoI2cMode" = "{
		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
	}"

	register "SerialIoGSpiMode" = "{
		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
	}"

	register "SerialIoGSpiCsMode" = "{
		[PchSerialIoIndexGSPI0] = 1,
		[PchSerialIoIndexGSPI1] = 1,
		[PchSerialIoIndexGSPI2] = 0,
		[PchSerialIoIndexGSPI3] = 0,
	}"

	register "SerialIoGSpiCsState" = "{
		[PchSerialIoIndexGSPI0] = 0,
		[PchSerialIoIndexGSPI1] = 0,
		[PchSerialIoIndexGSPI2] = 0,
		[PchSerialIoIndexGSPI3] = 0,
	}"

	register "SerialIoUartMode" = "{
		[PchSerialIoIndexUART0] = PchSerialIoPci,
		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
	}"

	# HD Audio
	register "PchHdaDspEnable" = "1"
	register "PchHdaAudioLinkHdaEnable" = "0"
	register "PchHdaAudioLinkDmicEnable[0]" = "0"
	register "PchHdaAudioLinkDmicEnable[1]" = "0"
	register "PchHdaAudioLinkSspEnable[0]" = "0"
	register "PchHdaAudioLinkSspEnable[1]" = "0"
	register "PchHdaAudioLinkSndwEnable[0]" = "0"
	register "PchHdaAudioLinkSndwEnable[1]" = "0"

	# TCSS USB3
	register "TcssXhciEn" = "1"
	register "TcssAuxOri" = "1"
	register "IomTypeCPortPadCfg[0]" = "0x090E000A"
	register "IomTypeCPortPadCfg[1]" = "0x090E000D"
	register "IomTypeCPortPadCfg[2]" = "0x09000000"
	register "IomTypeCPortPadCfg[3]" = "0x09000000"
	register "IomTypeCPortPadCfg[4]" = "0x09000000"
	register "IomTypeCPortPadCfg[5]" = "0x09000000"
	register "IomTypeCPortPadCfg[6]" = "0x09000000"
	register "IomTypeCPortPadCfg[7]" = "0x09000000"

	# D3Hot and D3Cold for TCSS
	register "TcssD3HotEnable" = "1"
	register "TcssD3ColdEnable" = "0"

	# DP port
	register "DdiPortAConfig" = "1"	# eDP
	register "DdiPortBConfig" = "0"

	register "DdiPortAHpd" = "1"
	register "DdiPortBHpd" = "1"
	register "DdiPortCHpd" = "0"
	register "DdiPort1Hpd" = "1"
	register "DdiPort2Hpd" = "1"
	register "DdiPort3Hpd" = "0"
	register "DdiPort4Hpd" = "0"

	register "DdiPortADdc" = "0"
	register "DdiPortBDdc" = "1"
	register "DdiPortCDdc" = "0"
	register "DdiPort1Ddc" = "0"
	register "DdiPort2Ddc" = "0"
	register "DdiPort3Ddc" = "0"
	register "DdiPort4Ddc" = "0"

	# Disable PM to allow for shorter irq pulses
	register "gpio_override_pm" = "1"
	register "gpio_pm[0]" = "0"
	register "gpio_pm[1]" = "0"
	register "gpio_pm[2]" = "0"
	register "gpio_pm[3]" = "0"
	register "gpio_pm[4]" = "0"

	# Enable "Intel Speed Shift Technology"
	register "speed_shift_enable" = "1"

	# Enable S0ix
	register "s0ix_enable" = "1"

	# Enable DPTF
	register "dptf_enable" = "1"

	register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
		.tdp_pl1_override = 15,
		.tdp_pl2_override = 38,
		.tdp_pl4 = 71,
	}"
	register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
		.tdp_pl1_override = 15,
		.tdp_pl2_override = 60,
		.tdp_pl4 = 105,
	}"
	register "power_limits_config[POWER_LIMITS_Y_2_CORE]" = "{
		.tdp_pl1_override = 9,
		.tdp_pl2_override = 35,
		.tdp_pl4 = 66,
	}"
	register "power_limits_config[POWER_LIMITS_Y_4_CORE]" = "{
		.tdp_pl1_override = 9,
		.tdp_pl2_override = 40,
		.tdp_pl4 = 83,
	}"

	register "Device4Enable" = "1"

	register "tcc_offset" = "10"     # TCC of 90

	# Intel Common SoC Config
	#+-------------------+---------------------------+
	#| Field             |  Value                    |
	#+-------------------+---------------------------+
	#| chipset_lockdown  | CHIPSET_LOCKDOWN_COREBOOT |
	#| GSPI0             | cr50 TPM. Early init is   |
	#|                   | required to set up a BAR  |
	#|                   | for TPM communication     |
	#|                   | before memory is up       |
	#| GSPI1             | Fingerprint MCU           |
	#| I2C0              | Audio                     |
	#| I2C1              | Touchscreen               |
	#| I2C2              | WLAN, SAR0                |
	#| I2C3              | Camera, SAR1              |
	#| I2C5              | Trackpad                  |
	#+-------------------+---------------------------+
	register "common_soc_config" = "{
		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
		.gspi[0] = {
			.speed_mhz = 1,
			.early_init = 1,
		},
		.i2c[0] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[1] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[2] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[3] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[5] = {
			.speed = I2C_SPEED_FAST,
		},
	}"

	register "ext_fivr_settings" = "{
		.configure_ext_fivr = 1,
		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
		.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
		.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL |
						  FIVR_VOLTAGE_MIN_ACTIVE |
						  FIVR_VOLTAGE_MIN_RETENTION,
		.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL |
						FIVR_VOLTAGE_MIN_ACTIVE |
						FIVR_VOLTAGE_MIN_RETENTION,
		.v1p05_icc_max_ma = 500,
		.vnn_sx_voltage_mv = 1250,
	}"

	device domain 0 on
		#From EDS(575683)
		device pci 00.0 on  end # Host Bridge			0x9A14:U/0x9A12:Y
		device pci 02.0 on  end # Graphics
		device pci 04.0 on
			# Default DPTF Policy for all Volteer boards if not overridden
			chip drivers/intel/dptf
				## Active Policy
				register "policies.active[0]" = "{.target=DPTF_CPU,
					.thresholds={TEMP_PCT(85, 90),
						     TEMP_PCT(80, 69),
						     TEMP_PCT(75, 56),
						     TEMP_PCT(70, 46),
						     TEMP_PCT(65, 36),}}"
				register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
					.thresholds={TEMP_PCT(50, 90),
						     TEMP_PCT(47, 69),
						     TEMP_PCT(45, 56),
						     TEMP_PCT(42, 46),
						     TEMP_PCT(39, 36),}}"
				register "policies.active[2]" = "{.target=DPTF_TEMP_SENSOR_1,
					.thresholds={TEMP_PCT(50, 90),
						     TEMP_PCT(47, 69),
						     TEMP_PCT(45, 56),
						     TEMP_PCT(42, 46),
						     TEMP_PCT(39, 36),}}"
				register "policies.active[3]" = "{.target=DPTF_TEMP_SENSOR_2,
					.thresholds={TEMP_PCT(50, 90),
						     TEMP_PCT(47, 69),
						     TEMP_PCT(45, 56),
						     TEMP_PCT(42, 46),
						     TEMP_PCT(39, 36),}}"
				register "policies.active[4]" = "{.target=DPTF_TEMP_SENSOR_3,
					.thresholds={TEMP_PCT(50, 90),
						     TEMP_PCT(47, 69),
						     TEMP_PCT(45, 56),
						     TEMP_PCT(42, 46),
						     TEMP_PCT(39, 36),}}"

				## Passive Policy
				register "policies.passive[0]" = "DPTF_PASSIVE(CPU,     CPU,           95, 5000)"
				register "policies.passive[1]" = "DPTF_PASSIVE(CPU,     TEMP_SENSOR_1, 65, 6000)"
				register "policies.passive[2]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000)"
				register "policies.passive[3]" = "DPTF_PASSIVE(CPU,     TEMP_SENSOR_2, 65, 6000)"
				register "policies.passive[4]" = "DPTF_PASSIVE(CPU,     TEMP_SENSOR_3, 65, 6000)"

				## Critical Policy
				register "policies.critical[0]" = "DPTF_CRITICAL(CPU,          105, SHUTDOWN)"
				register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)"
				register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN)"
				register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN)"
				register "policies.critical[4]" = "DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)"

				## Power Limits Control
				# 10-15W PL1 in 200mW increments, avg over 28-32s interval
				# PL2 is fixed at 64W, avg over 28-32s interval
				register "controls.power_limits.pl1" = "{
					.min_power = 3000,
					.max_power = 15000,
					.time_window_min = 28 * MSECS_PER_SEC,
					.time_window_max = 32 * MSECS_PER_SEC,
					.granularity = 200,}"
				register "controls.power_limits.pl2" = "{
					.min_power = 15000,
					.max_power = 60000,
					.time_window_min = 28 * MSECS_PER_SEC,
					.time_window_max = 32 * MSECS_PER_SEC,
					.granularity = 1000,}"

				## Charger Performance Control (Control, mA)
				register "controls.charger_perf[0]" = "{ 255, 1700 }"
				register "controls.charger_perf[1]" = "{  24, 1500 }"
				register "controls.charger_perf[2]" = "{  16, 1000 }"
				register "controls.charger_perf[3]" = "{   8,  500 }"

				## Fan Performance Control (Percent, Speed, Noise, Power)
				register "controls.fan_perf[0]" = "{  90, 6700, 220, 2200, }"
				register "controls.fan_perf[1]" = "{  80, 5800, 180, 1800, }"
				register "controls.fan_perf[2]" = "{  70, 5000, 145, 1450, }"
				register "controls.fan_perf[3]" = "{  60, 4900, 115, 1150, }"
				register "controls.fan_perf[4]" = "{  50, 3838,  90,  900, }"
				register "controls.fan_perf[5]" = "{  40, 2904,  55,  550, }"
				register "controls.fan_perf[6]" = "{  30, 2337,  30,  300, }"
				register "controls.fan_perf[7]" = "{  20, 1608,  15,  150, }"
				register "controls.fan_perf[8]" = "{  10,  800,  10,  100, }"
				register "controls.fan_perf[9]" = "{   0,    0,   0,   50, }"

				# Fan options
				register "options.fan.fine_grained_control" = "1"
				register "options.fan.step_size" = "2"

				device generic 0 on end
			end
		end # DPTF				0x9A03
		device pci 05.0 off end # IPU				0x9A19
		device pci 06.0 off end # PEG60				0x9A09
		device pci 07.0 on  end # TBT_PCIe0			0x9A23
		device pci 07.1 on  end # TBT_PCIe1			0x9A25
		device pci 07.2 off end # TBT_PCIe2			0x9A27
		device pci 07.3 off end # TBT_PCIe3			0x9A29
		device pci 08.0 on  end # GNA				0x9A11
		device pci 09.0 off end # NPK				0x9A33
		device pci 0a.0 off end # Crash-log SRAM		0x9A0D
		device pci 0d.0 on  end # USB xHCI			0x9A13
		device pci 0d.1 off end # USB xDCI (OTG)		0x9A15
		device pci 0d.2 on  end # TBT DMA0			0x9A1B
		device pci 0d.3 off end # TBT DMA1			0x9A1D
		device pci 0e.0 off end # VMD				0x9A0B

		# From PCH EDS(576591)
		device pci 10.2 on  end # CNVi: BT			0xA0F5 - A0F7
		device pci 10.6 off end # THC0				0xA0D0
		device pci 10.7 off end # THC1				0xA0D1

		device pci 12.0 off end # SensorHUB			0xA0FC
		device pci 12.6 off end # GSPI2				0x34FB

		device pci 13.0 off end # GSPI3				0xA0FD

		device pci 14.0 on  end # USB3.1 xHCI			0xA0ED
		device pci 14.1 off end # USB3.1 xDCI			0xA0EE
		device pci 14.2 on  end # Shared RAM			0xA0EF
		chip drivers/intel/wifi
			register "wake" = "GPE0_PME_B0"
			device pci 14.3 on end # CNVi: WiFi		0xA0F0 - A0F3
		end
		device pci 15.0 on  end # I2C #0			0xA0E8
		device pci 15.1 on  end # I2C1				0xA0E9
		device pci 15.2 on  end # I2C2				0xA0EA
		device pci 15.3 on  end # I2C3				0xA0EB

		device pci 16.0 on  end # HECI1				0xA0E0
		device pci 16.1 off end # HECI2				0xA0E1
		device pci 16.2 off end # CSME				0xA0E2
		device pci 16.3 off end # CSME				0xA0E3
		device pci 16.4 off end # HECI3				0xA0E4
		device pci 16.5 off end # HECI4				0xA0E5

		device pci 17.0 on  end # SATA				0xA0D3

		device pci 19.0 on  end # I2C4				0xA0C5
		device pci 19.1 on  end # I2C5				0xA0C6
		device pci 19.2 off end # UART2				0xA0C7

		device pci 1c.0 on  end # RP1				0xA0B8
		device pci 1c.1 off end # RP2				0xA0B9
		device pci 1c.2 off end # RP3				0xA0BA
		device pci 1c.3 off end # RP4				0xA0BB
		device pci 1c.4 off end # RP5				0xA0BC
		device pci 1c.5 off end # WWAN RP6			0xA0BD
		device pci 1c.6 on  end # RP7				0xA0BE
		device pci 1c.7 on  end # SD Card RP8			0xA0BF

		device pci 1d.0 on  end # RP9				0xA0B0
		device pci 1d.1 off end # RP10				0xA0B1
		device pci 1d.2 on  end # RP11				0xA0B2
		device pci 1d.3 off end # RP12				0xA0B3

		device pci 1e.0 on  end # UART0				0xA0A8
		device pci 1e.1 off end # UART1				0xA0A9
		device pci 1e.2 on
			chip drivers/spi/acpi
				register "hid" = "ACPI_DT_NAMESPACE_HID"
				register "compat_string" = ""google,cr50""
				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)"
				device spi 0 on end
			end
		end # GSPI0						0xA0AA
		device pci 1e.3 on
			chip drivers/spi/acpi
				register "name" = ""CRFP""
				register "hid" = "ACPI_DT_NAMESPACE_HID"
				register "uid" = "1"
				register "compat_string" = ""google,cros-ec-spi""
				register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)"
				device spi 0 on end
			end # FPMCU
		end # GSPI1						0xA0AB
		device pci 1f.0 on
			chip ec/google/chromeec
				device pnp 0c09.0 on end
			end
		end # eSPI						0xA080 - A09F
		device pci 1f.1 off end # P2SB				0xA0A0
		device pci 1f.2 hidden end # PMC			0xA0A1
		device pci 1f.3 on  end # Intel HD audio		0xA0C8-A0CF
		device pci 1f.4 off end # SMBus				0xA0A3
		device pci 1f.5 on  end # SPI				0xA0A4
		device pci 1f.6 off end # GbE				0x15E1/0x15E2
		device pci 1f.7 off end # TH				0xA0A6
	end
end