soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU
Set power limits in devicetree for Tiger Lake Y-SKU based volteer
variant boards.
BUG=b:152639350
BRANCH=None
TEST=Built and tested power limits on volteer variant board.
Change-Id: If4f1226473b48365e5962df9fff29910c99007fc
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43607
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index e0d3bea..0e8ad3e 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -211,15 +211,25 @@
# Enable DPTF
register "dptf_enable" = "1"
+ register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
+ .tdp_pl1_override = 15,
+ .tdp_pl2_override = 38,
+ .tdp_pl4 = 71,
+ }"
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 60,
.tdp_pl4 = 105,
}"
- register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
- .tdp_pl1_override = 15,
- .tdp_pl2_override = 38,
- .tdp_pl4 = 71,
+ register "power_limits_config[POWER_LIMITS_Y_2_CORE]" = "{
+ .tdp_pl1_override = 9,
+ .tdp_pl2_override = 35,
+ .tdp_pl4 = 66,
+ }"
+ register "power_limits_config[POWER_LIMITS_Y_4_CORE]" = "{
+ .tdp_pl1_override = 9,
+ .tdp_pl2_override = 40,
+ .tdp_pl4 = 83,
}"
register "Device4Enable" = "1"