Duncan Laurie | 9db8c25 | 2020-05-10 11:16:45 -0700 | [diff] [blame] | 1 | fw_config |
Nick Vaccaro | 2cc0600 | 2020-06-18 12:19:08 -0700 | [diff] [blame] | 2 | field DB_USB 0 3 |
| 3 | option USB_ABSENT 0 |
| 4 | option USB4_GEN2 1 |
| 5 | option USB3_ACTIVE 2 |
| 6 | option USB4_GEN3 3 |
| 7 | option USB3_PASSIVE 4 |
| 8 | option USB3_NO_A 5 |
Duncan Laurie | 9db8c25 | 2020-05-10 11:16:45 -0700 | [diff] [blame] | 9 | end |
| 10 | field THERMAL 4 7 end |
| 11 | field AUDIO 8 10 |
| 12 | option NONE 0 |
| 13 | option MAX98357_ALC5682I_I2S 1 |
| 14 | option MAX98373_ALC5682I_I2S 2 |
| 15 | option MAX98373_ALC5682_SNDW 3 |
| 16 | end |
| 17 | field TABLETMODE 11 |
Nick Vaccaro | 2cc0600 | 2020-06-18 12:19:08 -0700 | [diff] [blame] | 18 | option TABLETMODE_DISABLED 0 |
| 19 | option TABLETMODE_ENABLED 1 |
Duncan Laurie | 9db8c25 | 2020-05-10 11:16:45 -0700 | [diff] [blame] | 20 | end |
Nick Vaccaro | 2cc0600 | 2020-06-18 12:19:08 -0700 | [diff] [blame] | 21 | field DB_LTE 12 13 |
| 22 | option LTE_ABSENT 0 |
| 23 | option LTE_PRESENT 1 |
| 24 | end |
| 25 | field DB_SD 16 19 |
| 26 | option SD_ABSENT 0 |
| 27 | option SD_GL9755S 1 |
| 28 | option SD_RTS5261 2 |
Duncan Laurie | 9db8c25 | 2020-05-10 11:16:45 -0700 | [diff] [blame] | 29 | end |
| 30 | end |
| 31 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 32 | chip soc/intel/tigerlake |
| 33 | |
| 34 | device cpu_cluster 0 on |
| 35 | device lapic 0 on end |
| 36 | end |
| 37 | |
| 38 | # GPE configuration |
| 39 | # Note that GPE events called out in ASL code rely on this |
| 40 | # route. i.e. If this route changes then the affected GPE |
| 41 | # offset bits also need to be changed. |
| 42 | register "pmc_gpe0_dw0" = "GPP_C" |
| 43 | register "pmc_gpe0_dw1" = "GPP_D" |
| 44 | register "pmc_gpe0_dw2" = "GPP_E" |
| 45 | |
Jamie Ryu | 154625b | 2020-06-12 02:59:26 -0700 | [diff] [blame] | 46 | # Enable heci communication |
| 47 | register "HeciEnabled" = "1" |
| 48 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 49 | # FSP configuration |
Shreesh Chhabbi | 3708687 | 2020-06-17 12:40:42 -0700 | [diff] [blame^] | 50 | register "SaGv" = "SaGv_Enabled" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 51 | register "SmbusEnable" = "0" |
| 52 | |
| 53 | register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 |
| 54 | register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 |
| 55 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN |
| 56 | register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Cl |
| 57 | register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera |
| 58 | register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used |
| 59 | register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used |
| 60 | register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used |
| 61 | register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Co |
| 62 | register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth |
| 63 | |
| 64 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 |
| 65 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 |
| 66 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN |
| 67 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 Camera |
| 68 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 69 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 70 | register "gen1_dec" = "0x00fc0801" |
| 71 | register "gen2_dec" = "0x000c0201" |
| 72 | # EC memory map range is 0x900-0x9ff |
| 73 | register "gen3_dec" = "0x00fc0901" |
| 74 | |
| 75 | # Enable NVMe PCIE 9 using clk 0 |
| 76 | register "PcieRpEnable[8]" = "1" |
Wonkyu Kim | e3bf8ba | 2020-04-07 23:34:12 -0700 | [diff] [blame] | 77 | register "PcieRpLtrEnable[8]" = "1" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 78 | register "PcieClkSrcUsage[0]" = "8" |
| 79 | register "PcieClkSrcClkReq[0]" = "0" |
| 80 | |
Venkata Krishna Nimmagadda | c34bb38 | 2020-01-15 10:13:26 -0800 | [diff] [blame] | 81 | # Enable Optane PCIE 11 using clk 0 |
| 82 | register "PcieRpEnable[10]" = "1" |
Wonkyu Kim | e3bf8ba | 2020-04-07 23:34:12 -0700 | [diff] [blame] | 83 | register "PcieRpLtrEnable[10]" = "1" |
Venkata Krishna Nimmagadda | c34bb38 | 2020-01-15 10:13:26 -0800 | [diff] [blame] | 84 | register "HybridStorageMode" = "1" |
| 85 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 86 | # Enable SD Card PCIE 8 using clk 3 |
| 87 | register "PcieRpEnable[7]" = "1" |
Wonkyu Kim | e3bf8ba | 2020-04-07 23:34:12 -0700 | [diff] [blame] | 88 | register "PcieRpLtrEnable[7]" = "1" |
nick_xr_chen | f446b81 | 2020-06-30 09:34:33 +0800 | [diff] [blame] | 89 | register "PcieRpHotPlug[7]" = "1" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 90 | register "PcieClkSrcUsage[3]" = "7" |
| 91 | register "PcieClkSrcClkReq[3]" = "3" |
| 92 | |
| 93 | # Enable WLAN PCIE 7 using clk 1 |
| 94 | register "PcieRpEnable[6]" = "1" |
Wonkyu Kim | e3bf8ba | 2020-04-07 23:34:12 -0700 | [diff] [blame] | 95 | register "PcieRpLtrEnable[6]" = "1" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 96 | register "PcieClkSrcUsage[1]" = "6" |
| 97 | register "PcieClkSrcClkReq[1]" = "1" |
| 98 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 99 | # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality |
Alex Levin | a53dbd4 | 2020-03-09 16:52:59 -0700 | [diff] [blame] | 100 | register "PcieClkSrcUsage[2]" = "0xFF" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 101 | register "PcieClkSrcUsage[4]" = "0xFF" |
| 102 | register "PcieClkSrcUsage[5]" = "0xFF" |
| 103 | register "PcieClkSrcUsage[6]" = "0xFF" |
| 104 | |
| 105 | # Enable SATA |
| 106 | register "SataEnable" = "1" |
| 107 | register "SataMode" = "0" |
| 108 | register "SataSalpSupport" = "1" |
| 109 | register "SataPortsEnable[0]" = "0" |
| 110 | register "SataPortsEnable[1]" = "1" |
| 111 | register "SataPortsDevSlp[0]" = "0" |
Wonkyu Kim | b8bfe14 | 2020-04-21 17:07:57 -0700 | [diff] [blame] | 112 | register "SataPortsDevSlp[1]" = "1" |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 113 | |
| 114 | register "SerialIoI2cMode" = "{ |
| 115 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 116 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 117 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 118 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 119 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 120 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 121 | }" |
| 122 | |
| 123 | register "SerialIoGSpiMode" = "{ |
| 124 | [PchSerialIoIndexGSPI0] = PchSerialIoPci, |
| 125 | [PchSerialIoIndexGSPI1] = PchSerialIoPci, |
| 126 | [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, |
| 127 | [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, |
| 128 | }" |
| 129 | |
| 130 | register "SerialIoGSpiCsMode" = "{ |
| 131 | [PchSerialIoIndexGSPI0] = 1, |
| 132 | [PchSerialIoIndexGSPI1] = 1, |
| 133 | [PchSerialIoIndexGSPI2] = 0, |
| 134 | [PchSerialIoIndexGSPI3] = 0, |
| 135 | }" |
| 136 | |
| 137 | register "SerialIoGSpiCsState" = "{ |
| 138 | [PchSerialIoIndexGSPI0] = 0, |
| 139 | [PchSerialIoIndexGSPI1] = 0, |
| 140 | [PchSerialIoIndexGSPI2] = 0, |
| 141 | [PchSerialIoIndexGSPI3] = 0, |
| 142 | }" |
| 143 | |
| 144 | register "SerialIoUartMode" = "{ |
| 145 | [PchSerialIoIndexUART0] = PchSerialIoPci, |
| 146 | [PchSerialIoIndexUART1] = PchSerialIoDisabled, |
| 147 | [PchSerialIoIndexUART2] = PchSerialIoDisabled, |
| 148 | }" |
| 149 | |
Srinidhi N Kaushik | 22d5b07 | 2020-03-06 10:47:17 -0800 | [diff] [blame] | 150 | # HD Audio |
| 151 | register "PchHdaDspEnable" = "1" |
| 152 | register "PchHdaAudioLinkHdaEnable" = "0" |
Duncan Laurie | 4dffa9c | 2020-05-10 11:20:20 -0700 | [diff] [blame] | 153 | register "PchHdaAudioLinkDmicEnable[0]" = "0" |
| 154 | register "PchHdaAudioLinkDmicEnable[1]" = "0" |
| 155 | register "PchHdaAudioLinkSspEnable[0]" = "0" |
| 156 | register "PchHdaAudioLinkSspEnable[1]" = "0" |
| 157 | register "PchHdaAudioLinkSndwEnable[0]" = "0" |
| 158 | register "PchHdaAudioLinkSndwEnable[1]" = "0" |
Srinidhi N Kaushik | 22d5b07 | 2020-03-06 10:47:17 -0800 | [diff] [blame] | 159 | |
Brandon Breitenstein | 01ec713 | 2020-03-06 10:51:30 -0800 | [diff] [blame] | 160 | # TCSS USB3 |
| 161 | register "TcssXhciEn" = "1" |
Brandon Breitenstein | b7911c8 | 2020-04-06 15:34:19 -0700 | [diff] [blame] | 162 | register "TcssAuxOri" = "1" |
| 163 | register "IomTypeCPortPadCfg[0]" = "0x090E000A" |
| 164 | register "IomTypeCPortPadCfg[1]" = "0x090E000D" |
Brandon Breitenstein | c9a3451 | 2020-06-10 17:04:29 -0700 | [diff] [blame] | 165 | register "IomTypeCPortPadCfg[2]" = "0x09000000" |
| 166 | register "IomTypeCPortPadCfg[3]" = "0x09000000" |
| 167 | register "IomTypeCPortPadCfg[4]" = "0x09000000" |
| 168 | register "IomTypeCPortPadCfg[5]" = "0x09000000" |
| 169 | register "IomTypeCPortPadCfg[6]" = "0x09000000" |
| 170 | register "IomTypeCPortPadCfg[7]" = "0x09000000" |
Brandon Breitenstein | b7911c8 | 2020-04-06 15:34:19 -0700 | [diff] [blame] | 171 | |
John Zhao | f5b33c0 | 2020-05-19 15:29:07 -0700 | [diff] [blame] | 172 | # D3Hot and D3Cold for TCSS |
| 173 | register "TcssD3HotEnable" = "1" |
John Zhao | 2c807ff | 2020-06-18 00:25:51 -0700 | [diff] [blame] | 174 | register "TcssD3ColdEnable" = "0" |
John Zhao | f5b33c0 | 2020-05-19 15:29:07 -0700 | [diff] [blame] | 175 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 176 | # DP port |
| 177 | register "DdiPortAConfig" = "1" # eDP |
| 178 | register "DdiPortBConfig" = "0" |
| 179 | |
| 180 | register "DdiPortAHpd" = "1" |
| 181 | register "DdiPortBHpd" = "1" |
| 182 | register "DdiPortCHpd" = "0" |
| 183 | register "DdiPort1Hpd" = "1" |
| 184 | register "DdiPort2Hpd" = "1" |
| 185 | register "DdiPort3Hpd" = "0" |
| 186 | register "DdiPort4Hpd" = "0" |
| 187 | |
| 188 | register "DdiPortADdc" = "0" |
| 189 | register "DdiPortBDdc" = "1" |
| 190 | register "DdiPortCDdc" = "0" |
| 191 | register "DdiPort1Ddc" = "0" |
| 192 | register "DdiPort2Ddc" = "0" |
| 193 | register "DdiPort3Ddc" = "0" |
| 194 | register "DdiPort4Ddc" = "0" |
| 195 | |
| 196 | # Disable PM to allow for shorter irq pulses |
| 197 | register "gpio_override_pm" = "1" |
| 198 | register "gpio_pm[0]" = "0" |
| 199 | register "gpio_pm[1]" = "0" |
| 200 | register "gpio_pm[2]" = "0" |
| 201 | register "gpio_pm[3]" = "0" |
| 202 | register "gpio_pm[4]" = "0" |
| 203 | |
| 204 | # Enable "Intel Speed Shift Technology" |
| 205 | register "speed_shift_enable" = "1" |
| 206 | |
| 207 | # Enable S0ix |
| 208 | register "s0ix_enable" = "1" |
| 209 | |
Sumeet R Pawnikar | 7d6bc60 | 2020-05-08 19:22:07 +0530 | [diff] [blame] | 210 | # Enable DPTF |
| 211 | register "dptf_enable" = "1" |
| 212 | |
Tim Wawrzynczak | 2dcca0f | 2020-06-16 10:50:47 -0600 | [diff] [blame] | 213 | register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ |
Sumeet R Pawnikar | 7d6bc60 | 2020-05-08 19:22:07 +0530 | [diff] [blame] | 214 | .tdp_pl1_override = 15, |
| 215 | .tdp_pl2_override = 60, |
Tim Wawrzynczak | 2dcca0f | 2020-06-16 10:50:47 -0600 | [diff] [blame] | 216 | .tdp_pl4 = 105, |
| 217 | }" |
| 218 | register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ |
| 219 | .tdp_pl1_override = 15, |
| 220 | .tdp_pl2_override = 38, |
| 221 | .tdp_pl4 = 71, |
Sumeet R Pawnikar | 7d6bc60 | 2020-05-08 19:22:07 +0530 | [diff] [blame] | 222 | }" |
| 223 | |
| 224 | register "Device4Enable" = "1" |
| 225 | |
Sumeet R Pawnikar | 9f9b97e | 2020-06-30 14:18:41 +0530 | [diff] [blame] | 226 | register "tcc_offset" = "10" # TCC of 90 |
| 227 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 228 | # Intel Common SoC Config |
| 229 | #+-------------------+---------------------------+ |
| 230 | #| Field | Value | |
| 231 | #+-------------------+---------------------------+ |
| 232 | #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | |
| 233 | #| GSPI0 | cr50 TPM. Early init is | |
| 234 | #| | required to set up a BAR | |
| 235 | #| | for TPM communication | |
| 236 | #| | before memory is up | |
Alex Levin | 3bc41cf | 2020-03-06 10:54:10 -0800 | [diff] [blame] | 237 | #| GSPI1 | Fingerprint MCU | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 238 | #| I2C0 | Audio | |
| 239 | #| I2C1 | Touchscreen | |
| 240 | #| I2C2 | WLAN, SAR0 | |
| 241 | #| I2C3 | Camera, SAR1 | |
| 242 | #| I2C5 | Trackpad | |
| 243 | #+-------------------+---------------------------+ |
| 244 | register "common_soc_config" = "{ |
| 245 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 246 | .gspi[0] = { |
| 247 | .speed_mhz = 1, |
| 248 | .early_init = 1, |
| 249 | }, |
| 250 | .i2c[0] = { |
| 251 | .speed = I2C_SPEED_FAST, |
| 252 | }, |
| 253 | .i2c[1] = { |
| 254 | .speed = I2C_SPEED_FAST, |
| 255 | }, |
| 256 | .i2c[2] = { |
| 257 | .speed = I2C_SPEED_FAST, |
| 258 | }, |
| 259 | .i2c[3] = { |
| 260 | .speed = I2C_SPEED_FAST, |
| 261 | }, |
| 262 | .i2c[5] = { |
| 263 | .speed = I2C_SPEED_FAST, |
| 264 | }, |
| 265 | }" |
| 266 | |
Venkata Krishna Nimmagadda | 7368da3 | 2020-06-09 00:11:34 -0700 | [diff] [blame] | 267 | register "ext_fivr_settings" = "{ |
| 268 | .configure_ext_fivr = 1, |
| 269 | .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, |
| 270 | .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, |
| 271 | .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | |
| 272 | FIVR_VOLTAGE_MIN_ACTIVE | |
| 273 | FIVR_VOLTAGE_MIN_RETENTION, |
| 274 | .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | |
| 275 | FIVR_VOLTAGE_MIN_ACTIVE | |
| 276 | FIVR_VOLTAGE_MIN_RETENTION, |
| 277 | .v1p05_icc_max_ma = 500, |
| 278 | .vnn_sx_voltage_mv = 1250, |
| 279 | }" |
| 280 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 281 | device domain 0 on |
| 282 | #From EDS(575683) |
| 283 | device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y |
| 284 | device pci 02.0 on end # Graphics |
Tim Wawrzynczak | 07ac2ec | 2020-05-29 15:58:19 -0600 | [diff] [blame] | 285 | device pci 04.0 on |
| 286 | # Default DPTF Policy for all Volteer boards if not overridden |
| 287 | chip drivers/intel/dptf |
| 288 | ## Active Policy |
| 289 | register "policies.active[0]" = "{.target=DPTF_CPU, |
| 290 | .thresholds={TEMP_PCT(85, 90), |
| 291 | TEMP_PCT(80, 69), |
| 292 | TEMP_PCT(75, 56), |
| 293 | TEMP_PCT(70, 46), |
| 294 | TEMP_PCT(65, 36),}}" |
| 295 | register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, |
| 296 | .thresholds={TEMP_PCT(50, 90), |
| 297 | TEMP_PCT(47, 69), |
| 298 | TEMP_PCT(45, 56), |
| 299 | TEMP_PCT(42, 46), |
| 300 | TEMP_PCT(39, 36),}}" |
| 301 | register "policies.active[2]" = "{.target=DPTF_TEMP_SENSOR_1, |
| 302 | .thresholds={TEMP_PCT(50, 90), |
| 303 | TEMP_PCT(47, 69), |
| 304 | TEMP_PCT(45, 56), |
| 305 | TEMP_PCT(42, 46), |
| 306 | TEMP_PCT(39, 36),}}" |
| 307 | register "policies.active[3]" = "{.target=DPTF_TEMP_SENSOR_2, |
| 308 | .thresholds={TEMP_PCT(50, 90), |
| 309 | TEMP_PCT(47, 69), |
| 310 | TEMP_PCT(45, 56), |
| 311 | TEMP_PCT(42, 46), |
| 312 | TEMP_PCT(39, 36),}}" |
| 313 | |
| 314 | ## Passive Policy |
| 315 | register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" |
| 316 | register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" |
| 317 | register "policies.passive[2]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 65, 6000)" |
| 318 | register "policies.passive[3]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000)" |
| 319 | |
| 320 | ## Critical Policy |
| 321 | register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" |
| 322 | register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" |
| 323 | register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN)" |
| 324 | register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN)" |
| 325 | |
| 326 | ## Power Limits Control |
| 327 | # 10-15W PL1 in 200mW increments, avg over 28-32s interval |
| 328 | # PL2 is fixed at 64W, avg over 28-32s interval |
| 329 | register "controls.power_limits.pl1" = "{ |
| 330 | .min_power = 3000, |
| 331 | .max_power = 15000, |
| 332 | .time_window_min = 28 * MSECS_PER_SEC, |
| 333 | .time_window_max = 32 * MSECS_PER_SEC, |
| 334 | .granularity = 200,}" |
| 335 | register "controls.power_limits.pl2" = "{ |
| 336 | .min_power = 15000, |
| 337 | .max_power = 60000, |
| 338 | .time_window_min = 28 * MSECS_PER_SEC, |
| 339 | .time_window_max = 32 * MSECS_PER_SEC, |
| 340 | .granularity = 1000,}" |
| 341 | |
| 342 | ## Charger Performance Control (Control, mA) |
| 343 | register "controls.charger_perf[0]" = "{ 255, 1700 }" |
| 344 | register "controls.charger_perf[1]" = "{ 24, 1500 }" |
| 345 | register "controls.charger_perf[2]" = "{ 16, 1000 }" |
| 346 | register "controls.charger_perf[3]" = "{ 8, 500 }" |
| 347 | |
| 348 | ## Fan Performance Control (Percent, Speed, Noise, Power) |
| 349 | register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" |
| 350 | register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" |
| 351 | register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" |
| 352 | register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" |
| 353 | register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" |
| 354 | register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" |
| 355 | register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" |
| 356 | register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" |
| 357 | register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" |
| 358 | register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" |
| 359 | |
| 360 | # Fan options |
| 361 | register "options.fan.fine_grained_control" = "1" |
| 362 | register "options.fan.step_size" = "2" |
| 363 | |
| 364 | device generic 0 on end |
| 365 | end |
| 366 | end # DPTF 0x9A03 |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 367 | device pci 05.0 off end # IPU 0x9A19 |
| 368 | device pci 06.0 off end # PEG60 0x9A09 |
John Zhao | 5d79a0c | 2020-05-13 16:44:38 -0700 | [diff] [blame] | 369 | device pci 07.0 on end # TBT_PCIe0 0x9A23 |
| 370 | device pci 07.1 on end # TBT_PCIe1 0x9A25 |
| 371 | device pci 07.2 off end # TBT_PCIe2 0x9A27 |
| 372 | device pci 07.3 off end # TBT_PCIe3 0x9A29 |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 373 | device pci 08.0 on end # GNA 0x9A11 |
| 374 | device pci 09.0 off end # NPK 0x9A33 |
| 375 | device pci 0a.0 off end # Crash-log SRAM 0x9A0D |
| 376 | device pci 0d.0 on end # USB xHCI 0x9A13 |
| 377 | device pci 0d.1 off end # USB xDCI (OTG) 0x9A15 |
John Zhao | 5d79a0c | 2020-05-13 16:44:38 -0700 | [diff] [blame] | 378 | device pci 0d.2 on end # TBT DMA0 0x9A1B |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 379 | device pci 0d.3 off end # TBT DMA1 0x9A1D |
| 380 | device pci 0e.0 off end # VMD 0x9A0B |
| 381 | |
| 382 | # From PCH EDS(576591) |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 383 | device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 |
| 384 | device pci 10.6 off end # THC0 0xA0D0 |
| 385 | device pci 10.7 off end # THC1 0xA0D1 |
| 386 | |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 387 | device pci 12.0 off end # SensorHUB 0xA0FC |
| 388 | device pci 12.6 off end # GSPI2 0x34FB |
| 389 | |
| 390 | device pci 13.0 off end # GSPI3 0xA0FD |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 391 | |
| 392 | device pci 14.0 on end # USB3.1 xHCI 0xA0ED |
| 393 | device pci 14.1 off end # USB3.1 xDCI 0xA0EE |
| 394 | device pci 14.2 on end # Shared RAM 0xA0EF |
Srinidhi N Kaushik | ac7d6b4 | 2020-03-05 17:19:51 -0800 | [diff] [blame] | 395 | chip drivers/intel/wifi |
| 396 | register "wake" = "GPE0_PME_B0" |
| 397 | device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 |
| 398 | end |
Nick Vaccaro | f3d399e | 2020-06-18 18:30:31 -0700 | [diff] [blame] | 399 | device pci 15.0 on end # I2C #0 0xA0E8 |
| 400 | device pci 15.1 on end # I2C1 0xA0E9 |
| 401 | device pci 15.2 on end # I2C2 0xA0EA |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 402 | device pci 15.3 on end # I2C3 0xA0EB |
| 403 | |
| 404 | device pci 16.0 on end # HECI1 0xA0E0 |
| 405 | device pci 16.1 off end # HECI2 0xA0E1 |
| 406 | device pci 16.2 off end # CSME 0xA0E2 |
| 407 | device pci 16.3 off end # CSME 0xA0E3 |
| 408 | device pci 16.4 off end # HECI3 0xA0E4 |
| 409 | device pci 16.5 off end # HECI4 0xA0E5 |
| 410 | |
| 411 | device pci 17.0 on end # SATA 0xA0D3 |
| 412 | |
| 413 | device pci 19.0 on end # I2C4 0xA0C5 |
Nick Vaccaro | f3d399e | 2020-06-18 18:30:31 -0700 | [diff] [blame] | 414 | device pci 19.1 on end # I2C5 0xA0C6 |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 415 | device pci 19.2 off end # UART2 0xA0C7 |
| 416 | |
| 417 | device pci 1c.0 on end # RP1 0xA0B8 |
| 418 | device pci 1c.1 off end # RP2 0xA0B9 |
| 419 | device pci 1c.2 off end # RP3 0xA0BA |
| 420 | device pci 1c.3 off end # RP4 0xA0BB |
| 421 | device pci 1c.4 off end # RP5 0xA0BC |
Alex Levin | a53dbd4 | 2020-03-09 16:52:59 -0700 | [diff] [blame] | 422 | device pci 1c.5 off end # WWAN RP6 0xA0BD |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 423 | device pci 1c.6 on end # RP7 0xA0BE |
| 424 | device pci 1c.7 on end # SD Card RP8 0xA0BF |
| 425 | |
| 426 | device pci 1d.0 on end # RP9 0xA0B0 |
| 427 | device pci 1d.1 off end # RP10 0xA0B1 |
Venkata Krishna Nimmagadda | c34bb38 | 2020-01-15 10:13:26 -0800 | [diff] [blame] | 428 | device pci 1d.2 on end # RP11 0xA0B2 |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 429 | device pci 1d.3 off end # RP12 0xA0B3 |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 430 | |
| 431 | device pci 1e.0 on end # UART0 0xA0A8 |
| 432 | device pci 1e.1 off end # UART1 0xA0A9 |
| 433 | device pci 1e.2 on |
| 434 | chip drivers/spi/acpi |
| 435 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 436 | register "compat_string" = ""google,cr50"" |
| 437 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" |
| 438 | device spi 0 on end |
| 439 | end |
Tim Wawrzynczak | 6d20d0c | 2020-05-13 17:00:33 -0600 | [diff] [blame] | 440 | end # GSPI0 0xA0AA |
Alex Levin | 3bc41cf | 2020-03-06 10:54:10 -0800 | [diff] [blame] | 441 | device pci 1e.3 on |
| 442 | chip drivers/spi/acpi |
| 443 | register "name" = ""CRFP"" |
| 444 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 445 | register "uid" = "1" |
| 446 | register "compat_string" = ""google,cros-ec-spi"" |
| 447 | register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" |
| 448 | device spi 0 on end |
| 449 | end # FPMCU |
Tim Wawrzynczak | 6d20d0c | 2020-05-13 17:00:33 -0600 | [diff] [blame] | 450 | end # GSPI1 0xA0AB |
Nick Vaccaro | 9a3486e | 2020-04-17 10:14:57 -0700 | [diff] [blame] | 451 | device pci 1f.0 on |
| 452 | chip ec/google/chromeec |
| 453 | device pnp 0c09.0 on end |
| 454 | end |
Tim Wawrzynczak | 6d20d0c | 2020-05-13 17:00:33 -0600 | [diff] [blame] | 455 | end # eSPI 0xA080 - A09F |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 456 | device pci 1f.1 off end # P2SB 0xA0A0 |
Tim Wawrzynczak | 6d20d0c | 2020-05-13 17:00:33 -0600 | [diff] [blame] | 457 | device pci 1f.2 hidden end # PMC 0xA0A1 |
Duncan Laurie | 4dffa9c | 2020-05-10 11:20:20 -0700 | [diff] [blame] | 458 | device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF |
Nick Vaccaro | f978191 | 2020-01-28 18:43:28 -0800 | [diff] [blame] | 459 | device pci 1f.4 off end # SMBus 0xA0A3 |
| 460 | device pci 1f.5 on end # SPI 0xA0A4 |
| 461 | device pci 1f.6 off end # GbE 0x15E1/0x15E2 |
| 462 | device pci 1f.7 off end # TH 0xA0A6 |
| 463 | end |
| 464 | end |