mb/google/volteer: add volteer mainboard initial support
Created a new Google baseboard named volteer from scratch.
BUG=b:142961277
BRANCH=master
TEST="emerge-volteer coreboot" compiles successfully.
Change-Id: I03a13f3df4e819ab9cf63ad69867c807d2a1b651
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
new file mode 100644
index 0000000..b9ed424
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -0,0 +1,346 @@
+chip soc/intel/tigerlake
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "pmc_gpe0_dw0" = "GPP_C"
+ register "pmc_gpe0_dw1" = "GPP_D"
+ register "pmc_gpe0_dw2" = "GPP_E"
+
+ # FSP configuration
+ register "SaGv" = "SaGv_Disabled"
+ register "SmbusEnable" = "0"
+
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Cl
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
+ register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
+ register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
+ register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Co
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 Camera
+
+ # Enable Pch iSCLK
+ register "pch_isclk" = "1"
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
+ # Enable NVMe PCIE 9 using clk 0
+ register "PcieRpEnable[8]" = "1"
+ register "PcieClkSrcUsage[0]" = "8"
+ register "PcieClkSrcClkReq[0]" = "0"
+
+ # Enable SD Card PCIE 8 using clk 3
+ register "PcieRpEnable[7]" = "1"
+ register "PcieClkSrcUsage[3]" = "7"
+ register "PcieClkSrcClkReq[3]" = "3"
+
+ # Enable WLAN PCIE 7 using clk 1
+ register "PcieRpEnable[6]" = "1"
+ register "PcieClkSrcUsage[1]" = "6"
+ register "PcieClkSrcClkReq[1]" = "1"
+
+ # Enable WWAN PCIE 6 using clk 2
+ register "PcieRpEnable[5]" = "1"
+ register "PcieClkSrcUsage[2]" = "5"
+ register "PcieClkSrcClkReq[2]" = "2"
+
+ # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality
+ register "PcieClkSrcUsage[4]" = "0xFF"
+ register "PcieClkSrcUsage[5]" = "0xFF"
+ register "PcieClkSrcUsage[6]" = "0xFF"
+
+ # Enable SATA
+ register "SataEnable" = "1"
+ register "SataMode" = "0"
+ register "SataSalpSupport" = "1"
+ register "SataPortsEnable[0]" = "0"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsDevSlp[0]" = "0"
+
+ register "SerialIoI2cMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ }"
+
+ register "SerialIoGSpiMode" = "{
+ [PchSerialIoIndexGSPI0] = PchSerialIoPci,
+ [PchSerialIoIndexGSPI1] = PchSerialIoPci,
+ [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
+ }"
+
+ register "SerialIoGSpiCsMode" = "{
+ [PchSerialIoIndexGSPI0] = 1,
+ [PchSerialIoIndexGSPI1] = 1,
+ [PchSerialIoIndexGSPI2] = 0,
+ [PchSerialIoIndexGSPI3] = 0,
+ }"
+
+ register "SerialIoGSpiCsState" = "{
+ [PchSerialIoIndexGSPI0] = 0,
+ [PchSerialIoIndexGSPI1] = 0,
+ [PchSerialIoIndexGSPI2] = 0,
+ [PchSerialIoIndexGSPI3] = 0,
+ }"
+
+ register "SerialIoUartMode" = "{
+ [PchSerialIoIndexUART0] = PchSerialIoPci,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
+ # DP port
+ register "DdiPortAConfig" = "1" # eDP
+ register "DdiPortBConfig" = "0"
+
+ register "DdiPortAHpd" = "1"
+ register "DdiPortBHpd" = "1"
+ register "DdiPortCHpd" = "0"
+ register "DdiPort1Hpd" = "1"
+ register "DdiPort2Hpd" = "1"
+ register "DdiPort3Hpd" = "0"
+ register "DdiPort4Hpd" = "0"
+
+ register "DdiPortADdc" = "0"
+ register "DdiPortBDdc" = "1"
+ register "DdiPortCDdc" = "0"
+ register "DdiPort1Ddc" = "0"
+ register "DdiPort2Ddc" = "0"
+ register "DdiPort3Ddc" = "0"
+ register "DdiPort4Ddc" = "0"
+
+ # Disable PM to allow for shorter irq pulses
+ register "gpio_override_pm" = "1"
+ register "gpio_pm[0]" = "0"
+ register "gpio_pm[1]" = "0"
+ register "gpio_pm[2]" = "0"
+ register "gpio_pm[3]" = "0"
+ register "gpio_pm[4]" = "0"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Enable S0ix
+ register "s0ix_enable" = "1"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| GSPI1 | Fingerprint MCU
+ #| I2C0 | Audio |
+ #| I2C1 | Touchscreen |
+ #| I2C2 | WLAN, SAR0 |
+ #| I2C3 | Camera, SAR1 |
+ #| I2C5 | Trackpad |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ }"
+
+ device domain 0 on
+ #From EDS(575683)
+ device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y
+ device pci 02.0 on end # Graphics
+ device pci 04.0 on end # DPTF 0x9A03
+ device pci 05.0 off end # IPU 0x9A19
+ device pci 06.0 off end # PEG60 0x9A09
+ device pci 07.0 on end # TBT_PCIe0 0x9A23
+ device pci 07.1 on end # TBT_PCIe1 0x9A25
+ device pci 07.2 on end # TBT_PCIe2 0x9A27
+ device pci 07.3 on end # TBT_PCIe3 0x9A29
+ device pci 08.0 on end # GNA 0x9A11
+ device pci 09.0 off end # NPK 0x9A33
+ device pci 0a.0 off end # Crash-log SRAM 0x9A0D
+ device pci 0d.0 on end # USB xHCI 0x9A13
+ device pci 0d.1 off end # USB xDCI (OTG) 0x9A15
+ device pci 0d.2 off end # TBT DMA0 0x9A1B
+ device pci 0d.3 off end # TBT DMA1 0x9A1D
+ device pci 0e.0 off end # VMD 0x9A0B
+
+ # From PCH EDS(576591)
+ device pci 10.0 on end # I2C6 0xA0D8
+ device pci 10.1 off end # I2C7 0xA0D9
+ device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7
+ device pci 10.6 off end # THC0 0xA0D0
+ device pci 10.7 off end # THC1 0xA0D1
+
+ device pci 11.0 off end # UART3 0xA0DA
+ device pci 11.1 off end # UART4 0xA0DB
+ device pci 11.2 off end # UART5 0xA0DC
+ device pci 11.3 off end # UART6 0xA0DD
+
+ device pci 12.0 off end # SensorHUB 0xA0FC
+ device pci 12.6 off end # GSPI2 0x34FB
+
+ device pci 13.0 off end # GSPI3 0xA0FD
+ device pci 13.1 off end # GSPI4 0xA0FE
+ device pci 13.2 off end # GSPI5 0xA0DE
+ device pci 13.3 off end # GSPI6 0xA0DF
+
+ device pci 14.0 on end # USB3.1 xHCI 0xA0ED
+ device pci 14.1 off end # USB3.1 xDCI 0xA0EE
+ device pci 14.2 on end # Shared RAM 0xA0EF
+ device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3
+
+ device pci 15.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""10EC5682""
+ register "name" = ""RT58""
+ register "desc" = ""Realtek RT5682""
+ register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_F8_IRQ)"
+ # Set the jd_src to RT5668_JD1 for jack detection
+ register "property_count" = "1"
+ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+ register "property_list[0].name" = ""realtek,jd-src""
+ register "property_list[0].integer" = "1"
+ device i2c 1a on end
+ end
+ end # I2C #0 0xA0E8
+ device pci 15.1 on end # I2C1 0xA0E9
+ device pci 15.2 on
+ chip drivers/i2c/sx9310
+ register "desc" = ""SAR0 Proximity Sensor""
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
+ register "speed" = "I2C_SPEED_FAST"
+ register "uid" = "0"
+ register "reg_prox_ctrl0" = "0x10"
+ register "reg_prox_ctrl1" = "0x00"
+ register "reg_prox_ctrl2" = "0x84"
+ register "reg_prox_ctrl3" = "0x0e"
+ register "reg_prox_ctrl4" = "0x07"
+ register "reg_prox_ctrl5" = "0xc6"
+ register "reg_prox_ctrl6" = "0x20"
+ register "reg_prox_ctrl7" = "0x0d"
+ register "reg_prox_ctrl8" = "0x8d"
+ register "reg_prox_ctrl9" = "0x43"
+ register "reg_prox_ctrl10" = "0x1f"
+ register "reg_prox_ctrl11" = "0x00"
+ register "reg_prox_ctrl12" = "0x00"
+ register "reg_prox_ctrl13" = "0x00"
+ register "reg_prox_ctrl14" = "0x00"
+ register "reg_prox_ctrl15" = "0x00"
+ register "reg_prox_ctrl16" = "0x00"
+ register "reg_prox_ctrl17" = "0x00"
+ register "reg_prox_ctrl18" = "0x00"
+ register "reg_prox_ctrl19" = "0x00"
+ register "reg_sar_ctrl0" = "0x50"
+ register "reg_sar_ctrl1" = "0x8a"
+ register "reg_sar_ctrl2" = "0x3c"
+ device i2c 28 on end
+ end
+ end # I2C2 0xA0EA
+ device pci 15.3 on end # I2C3 0xA0EB
+
+ device pci 16.0 on end # HECI1 0xA0E0
+ device pci 16.1 off end # HECI2 0xA0E1
+ device pci 16.2 off end # CSME 0xA0E2
+ device pci 16.3 off end # CSME 0xA0E3
+ device pci 16.4 off end # HECI3 0xA0E4
+ device pci 16.5 off end # HECI4 0xA0E5
+
+ device pci 17.0 on end # SATA 0xA0D3
+
+ device pci 19.0 on end # I2C4 0xA0C5
+ device pci 19.1 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E15_IRQ)"
+ register "probed" = "1"
+ device i2c 15 on end
+ end
+ end # I2C5 0xA0C6
+ device pci 19.2 off end # UART2 0xA0C7
+
+ device pci 1c.0 on end # RP1 0xA0B8
+ device pci 1c.1 off end # RP2 0xA0B9
+ device pci 1c.2 off end # RP3 0xA0BA
+ device pci 1c.3 off end # RP4 0xA0BB
+ device pci 1c.4 off end # RP5 0xA0BC
+ device pci 1c.5 on end # WWAN RP6 0xA0BD
+ device pci 1c.6 on end # RP7 0xA0BE
+ device pci 1c.7 on end # SD Card RP8 0xA0BF
+
+ device pci 1d.0 on end # RP9 0xA0B0
+ device pci 1d.1 off end # RP10 0xA0B1
+ device pci 1d.2 off end # RP11 0xA0B2
+ device pci 1d.3 off end # RP12 0xA0B3
+ device pci 1d.4 off end # RP13 0xA0B4
+ device pci 1d.5 off end # RP14 0xA0B5
+ device pci 1d.6 off end # RP15 0xA0B6
+ device pci 1d.7 off end # RP16 0xA0B7
+
+ device pci 1e.0 on end # UART0 0xA0A8
+ device pci 1e.1 off end # UART1 0xA0A9
+ device pci 1e.2 on
+ chip drivers/spi/acpi
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "compat_string" = ""google,cr50""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)"
+ device spi 0 on end
+ end
+ end # GSPI0 0xA0AA
+ device pci 1e.3 on end # GSPI1 0xA0AB
+
+ device pci 1f.0 on end # eSPI 0xA080 - A09F
+ device pci 1f.1 off end # P2SB 0xA0A0
+ device pci 1f.2 on end # PMC 0xA0A1
+ device pci 1f.3 on
+ chip drivers/generic/max98357a
+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
+ register "sdmode_delay" = "5"
+ device generic 0 on end
+ end
+ end # Intel HD audio 0xA0C8-A0CF
+ device pci 1f.4 off end # SMBus 0xA0A3
+ device pci 1f.5 on end # SPI 0xA0A4
+ device pci 1f.6 off end # GbE 0x15E1/0x15E2
+ device pci 1f.7 off end # TH 0xA0A6
+ end
+end