Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | config SOC_AMD_CEZANNE |
| 4 | bool |
| 5 | help |
| 6 | AMD Cezanne support |
| 7 | |
| 8 | if SOC_AMD_CEZANNE |
| 9 | |
| 10 | config SOC_SPECIFIC_OPTIONS |
| 11 | def_bool y |
Raul E Rangel | 24d024a | 2021-02-12 16:07:43 -0700 | [diff] [blame] | 12 | select ACPI_SOC_NVS |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 13 | select ARCH_BOOTBLOCK_X86_32 |
Kangheui Won | 66c5f25 | 2021-04-20 17:30:29 +1000 | [diff] [blame] | 14 | select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 15 | select ARCH_ROMSTAGE_X86_32 |
| 16 | select ARCH_RAMSTAGE_X86_32 |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 17 | select ARCH_X86 |
Raul E Rangel | 5461662 | 2021-02-05 17:29:12 -0700 | [diff] [blame] | 18 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
Mathew King | c519bff | 2021-03-04 08:26:51 -0700 | [diff] [blame] | 19 | select DRIVERS_USB_ACPI |
| 20 | select DRIVERS_USB_PCI_XHCI |
Raul E Rangel | 2bcf99f | 2021-11-08 16:58:26 -0700 | [diff] [blame] | 21 | select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING |
| 22 | select FSP_COMPRESS_FSP_M_LZ4 if ASYNC_FILE_LOADING |
Raul E Rangel | dc63bbd | 2021-11-08 14:10:45 -0700 | [diff] [blame] | 23 | select FSP_COMPRESS_FSP_S_LZ4 |
Raul E Rangel | e925af2 | 2021-03-30 16:32:20 -0600 | [diff] [blame] | 24 | select GENERIC_GPIO_LIB |
Felix Held | 8602495 | 2021-02-03 23:44:28 +0100 | [diff] [blame] | 25 | select HAVE_ACPI_TABLES |
Felix Held | 44f4153 | 2020-12-09 02:01:16 +0100 | [diff] [blame] | 26 | select HAVE_CF9_RESET |
Felix Held | 227c649 | 2021-03-22 14:44:58 +0100 | [diff] [blame] | 27 | select HAVE_EM100_SUPPORT |
Nikolai Vyssotski | 0671d73 | 2021-03-11 19:12:38 -0600 | [diff] [blame] | 28 | select HAVE_FSP_GOP |
Felix Held | ee2a365 | 2021-02-09 23:43:17 +0100 | [diff] [blame] | 29 | select HAVE_SMI_HANDLER |
Felix Held | cb97734 | 2021-01-19 20:36:38 +0100 | [diff] [blame] | 30 | select IDT_IN_EVERY_STAGE |
Felix Held | 7aacdd1 | 2021-02-10 23:27:47 +0100 | [diff] [blame] | 31 | select PARALLEL_MP_AP_WORK |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 32 | select PLATFORM_USES_FSP2_0 |
Raul E Rangel | 95b3dc3 | 2021-03-24 16:53:37 -0600 | [diff] [blame] | 33 | select PROVIDES_ROM_SHARING |
Karthikeyan Ramasubramanian | 1140b7c | 2021-09-17 16:33:35 -0600 | [diff] [blame] | 34 | select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 35 | select RESET_VECTOR_IN_RAM |
Felix Held | 7cd81b9 | 2021-02-11 14:58:08 +0100 | [diff] [blame] | 36 | select RTC |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 37 | select SOC_AMD_COMMON |
Fred Reitberger | 6f0b5b3 | 2022-02-08 11:55:48 -0500 | [diff] [blame] | 38 | select SOC_AMD_COMMON_BLOCK_ACP_GEN1 |
Felix Held | bb4bee85 | 2021-02-10 16:53:53 +0100 | [diff] [blame] | 39 | select SOC_AMD_COMMON_BLOCK_ACPI |
Felix Held | 64de2c1 | 2020-12-05 20:53:59 +0100 | [diff] [blame] | 40 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
Felix Held | dd882f3 | 2021-05-12 01:23:50 +0200 | [diff] [blame] | 41 | select SOC_AMD_COMMON_BLOCK_ACPI_ALIB |
Felix Held | 8f7f4bf | 2022-08-03 22:10:05 +0200 | [diff] [blame] | 42 | select SOC_AMD_COMMON_BLOCK_ACPI_CPPC |
Eric Lai | 65b0afe | 2021-04-09 11:50:48 +0800 | [diff] [blame] | 43 | select SOC_AMD_COMMON_BLOCK_ACPI_GPIO |
Jason Glenesk | 8d35428 | 2021-07-20 05:21:54 -0700 | [diff] [blame] | 44 | select SOC_AMD_COMMON_BLOCK_ACPI_IVRS |
Felix Held | 62ef88f | 2020-12-08 23:18:19 +0100 | [diff] [blame] | 45 | select SOC_AMD_COMMON_BLOCK_AOAC |
Felix Held | 9a6bc07 | 2021-03-05 00:14:08 +0100 | [diff] [blame] | 46 | select SOC_AMD_COMMON_BLOCK_APOB |
Fred Reitberger | f78e844 | 2022-10-27 13:58:58 -0400 | [diff] [blame] | 47 | select SOC_AMD_COMMON_BLOCK_APOB_HASH |
Felix Held | 07462ef | 2020-12-11 15:55:45 +0100 | [diff] [blame] | 48 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
Felix Held | ea32c52 | 2021-02-13 01:42:44 +0100 | [diff] [blame] | 49 | select SOC_AMD_COMMON_BLOCK_DATA_FABRIC |
Felix Held | 65d73cc | 2022-10-13 20:58:47 +0200 | [diff] [blame] | 50 | select SOC_AMD_COMMON_BLOCK_EMMC |
Nikolai Vyssotski | 0671d73 | 2021-03-11 19:12:38 -0600 | [diff] [blame] | 51 | select SOC_AMD_COMMON_BLOCK_GRAPHICS |
Felix Held | 28e2353 | 2021-02-24 20:52:08 +0100 | [diff] [blame] | 52 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI |
Zheng Bao | b0f00ed | 2021-03-16 15:28:49 +0800 | [diff] [blame] | 53 | select SOC_AMD_COMMON_BLOCK_I2C |
Felix Held | 556d1cc | 2022-02-02 22:11:52 +0100 | [diff] [blame] | 54 | select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL |
Raul E Rangel | 3acc515 | 2021-06-09 13:36:10 -0600 | [diff] [blame] | 55 | select SOC_AMD_COMMON_BLOCK_IOMMU |
Zheng Bao | 3da5569 | 2021-01-26 18:30:18 +0800 | [diff] [blame] | 56 | select SOC_AMD_COMMON_BLOCK_LPC |
Felix Held | 1e1d490 | 2021-07-14 00:05:39 +0200 | [diff] [blame] | 57 | select SOC_AMD_COMMON_BLOCK_MCAX |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 58 | select SOC_AMD_COMMON_BLOCK_NONCAR |
Raul E Rangel | a6529e7 | 2021-02-09 14:38:36 -0700 | [diff] [blame] | 59 | select SOC_AMD_COMMON_BLOCK_PCI |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 60 | select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |
Raul E Rangel | e4f8317 | 2021-05-10 14:49:55 -0600 | [diff] [blame] | 61 | select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER |
Robert Zieba | 5a040d6 | 2022-10-03 14:27:16 -0600 | [diff] [blame] | 62 | select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ |
Karthikeyan Ramasubramanian | f62bbc8 | 2021-03-30 15:19:12 -0600 | [diff] [blame] | 63 | select SOC_AMD_COMMON_BLOCK_PM |
Martin Roth | 31f7a72 | 2021-03-23 14:53:58 -0600 | [diff] [blame] | 64 | select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE |
Felix Held | 338d670 | 2021-01-29 23:13:56 +0100 | [diff] [blame] | 65 | select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
Felix Held | 4be064a | 2020-12-08 17:21:04 +0100 | [diff] [blame] | 66 | select SOC_AMD_COMMON_BLOCK_SMBUS |
Zheng Bao | 02a5ddd | 2020-12-15 22:16:51 +0800 | [diff] [blame] | 67 | select SOC_AMD_COMMON_BLOCK_SMI |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 68 | select SOC_AMD_COMMON_BLOCK_SMM |
Felix Held | 7f3f52d | 2021-03-03 18:56:41 +0100 | [diff] [blame] | 69 | select SOC_AMD_COMMON_BLOCK_SMU |
Raul E Rangel | 5461662 | 2021-02-05 17:29:12 -0700 | [diff] [blame] | 70 | select SOC_AMD_COMMON_BLOCK_SPI |
Felix Held | 65783fb | 2020-12-04 17:38:46 +0100 | [diff] [blame] | 71 | select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H |
Felix Held | 8a3d4d5 | 2021-01-13 03:06:21 +0100 | [diff] [blame] | 72 | select SOC_AMD_COMMON_BLOCK_UART |
Raul E Rangel | 35dc4b0 | 2021-02-12 16:04:27 -0700 | [diff] [blame] | 73 | select SOC_AMD_COMMON_BLOCK_UCODE |
Felix Held | d5ab24c | 2022-08-08 22:57:31 +0200 | [diff] [blame] | 74 | select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB |
Nikolai Vyssotski | cbc7c50 | 2021-04-28 18:24:28 -0500 | [diff] [blame] | 75 | select SOC_AMD_COMMON_FSP_DMI_TABLES |
Raul E Rangel | fd7ed87 | 2021-05-04 15:42:09 -0600 | [diff] [blame] | 76 | select SOC_AMD_COMMON_FSP_PCI |
Felix Held | cc975c5 | 2021-01-23 00:18:08 +0100 | [diff] [blame] | 77 | select SSE2 |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 78 | select UDK_2017_BINDING |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 79 | select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM |
| 80 | select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT |
| 81 | select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE |
Karthikeyan Ramasubramanian | bef5c40 | 2021-11-18 12:28:31 -0700 | [diff] [blame] | 82 | select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK |
Felix Held | f09221c | 2021-01-22 23:50:54 +0100 | [diff] [blame] | 83 | select X86_AMD_FIXED_MTRRS |
Subrata Banik | 9f91ced | 2021-07-28 15:38:32 +0530 | [diff] [blame] | 84 | select X86_INIT_NEED_1_SIPI |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 85 | |
Angel Pons | 6f5a658 | 2021-06-22 15:18:07 +0200 | [diff] [blame] | 86 | config ARCH_ALL_STAGES_X86 |
| 87 | default n |
| 88 | |
Furquan Shaikh | 696f4ea | 2021-01-08 11:48:52 -0800 | [diff] [blame] | 89 | config CHIPSET_DEVICETREE |
| 90 | string |
| 91 | default "soc/amd/cezanne/chipset.cb" |
| 92 | |
Felix Held | 44e4bf2 | 2021-08-27 23:32:56 +0200 | [diff] [blame] | 93 | config FSP_M_FILE |
| 94 | string "FSP-M (memory init) binary path and filename" |
| 95 | depends on ADD_FSP_BINARIES |
| 96 | default "3rdparty/amd_blobs/cezanne/CEZANNE_M.fd" |
| 97 | help |
| 98 | The path and filename of the FSP-M binary for this platform. |
| 99 | |
| 100 | config FSP_S_FILE |
| 101 | string "FSP-S (silicon init) binary path and filename" |
| 102 | depends on ADD_FSP_BINARIES |
| 103 | default "3rdparty/amd_blobs/cezanne/CEZANNE_S.fd" |
| 104 | help |
| 105 | The path and filename of the FSP-S binary for this platform. |
| 106 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 107 | config EARLY_RESERVED_DRAM_BASE |
| 108 | hex |
| 109 | default 0x2000000 |
| 110 | help |
| 111 | This variable defines the base address of the DRAM which is reserved |
| 112 | for usage by coreboot in early stages (i.e. before ramstage is up). |
| 113 | This memory gets reserved in BIOS tables to ensure that the OS does |
| 114 | not use it, thus preventing corruption of OS memory in case of S3 |
| 115 | resume. |
| 116 | |
| 117 | config EARLYRAM_BSP_STACK_SIZE |
| 118 | hex |
| 119 | default 0x1000 |
| 120 | |
| 121 | config PSP_APOB_DRAM_ADDRESS |
| 122 | hex |
| 123 | default 0x2001000 |
| 124 | help |
| 125 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 126 | Block. |
| 127 | |
Fred Reitberger | 475e282 | 2022-07-14 11:06:30 -0400 | [diff] [blame] | 128 | config PSP_APOB_DRAM_SIZE |
| 129 | hex |
| 130 | default 0x10000 |
| 131 | |
Kangheui Won | 66c5f25 | 2021-04-20 17:30:29 +1000 | [diff] [blame] | 132 | config PSP_SHAREDMEM_BASE |
| 133 | hex |
| 134 | default 0x2011000 if VBOOT |
| 135 | default 0x0 |
| 136 | help |
| 137 | This variable defines the base address in DRAM memory where PSP copies |
| 138 | the vboot workbuf. This is used in the linker script to have a static |
| 139 | allocation for the buffer as well as for adding relevant entries in |
| 140 | the BIOS directory table for the PSP. |
| 141 | |
| 142 | config PSP_SHAREDMEM_SIZE |
| 143 | hex |
| 144 | default 0x8000 if VBOOT |
| 145 | default 0x0 |
| 146 | help |
| 147 | Sets the maximum size for the PSP to pass the vboot workbuf and |
| 148 | any logs or timestamps back to coreboot. This will be copied |
| 149 | into main memory by the PSP and will be available when the x86 is |
| 150 | started. The workbuf's base depends on the address of the reset |
| 151 | vector. |
| 152 | |
Raul E Rangel | 86302a8 | 2022-01-18 15:29:54 -0700 | [diff] [blame] | 153 | config PRE_X86_CBMEM_CONSOLE_SIZE |
| 154 | hex |
| 155 | default 0x1600 |
| 156 | help |
| 157 | Size of the CBMEM console used in PSP verstage. |
| 158 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 159 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 160 | hex |
Raul E Rangel | 9d93b16 | 2022-01-13 13:43:57 -0700 | [diff] [blame] | 161 | default 0x2000 |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 162 | help |
| 163 | Increase this value if preram cbmem console is getting truncated |
| 164 | |
Kangheui Won | 4020aa7 | 2021-05-20 09:56:39 +1000 | [diff] [blame] | 165 | config CBFS_MCACHE_SIZE |
| 166 | hex |
| 167 | default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 168 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 169 | config C_ENV_BOOTBLOCK_SIZE |
| 170 | hex |
| 171 | default 0x10000 |
| 172 | help |
| 173 | Sets the size of the bootblock stage that should be loaded in DRAM. |
| 174 | This variable controls the DRAM allocation size in linker script |
| 175 | for bootblock stage. |
| 176 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 177 | config ROMSTAGE_ADDR |
| 178 | hex |
| 179 | default 0x2040000 |
| 180 | help |
| 181 | Sets the address in DRAM where romstage should be loaded. |
| 182 | |
| 183 | config ROMSTAGE_SIZE |
| 184 | hex |
| 185 | default 0x80000 |
| 186 | help |
| 187 | Sets the size of DRAM allocation for romstage in linker script. |
| 188 | |
| 189 | config FSP_M_ADDR |
| 190 | hex |
| 191 | default 0x20C0000 |
| 192 | help |
| 193 | Sets the address in DRAM where FSP-M should be loaded. cbfstool |
| 194 | performs relocation of FSP-M to this address. |
| 195 | |
| 196 | config FSP_M_SIZE |
| 197 | hex |
Karthikeyan Ramasubramanian | c2310a1 | 2021-08-31 12:39:47 -0600 | [diff] [blame] | 198 | default 0xC0000 |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 199 | help |
| 200 | Sets the size of DRAM allocation for FSP-M in linker script. |
| 201 | |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 202 | config FSP_TEMP_RAM_SIZE |
| 203 | hex |
| 204 | default 0x40000 |
| 205 | help |
| 206 | The amount of coreboot-allocated heap and stack usage by the FSP. |
| 207 | |
Raul E Rangel | 72616b3 | 2021-02-05 16:48:42 -0700 | [diff] [blame] | 208 | config VERSTAGE_ADDR |
| 209 | hex |
| 210 | depends on VBOOT_SEPARATE_VERSTAGE |
Karthikeyan Ramasubramanian | c2310a1 | 2021-08-31 12:39:47 -0600 | [diff] [blame] | 211 | default 0x2180000 |
Raul E Rangel | 72616b3 | 2021-02-05 16:48:42 -0700 | [diff] [blame] | 212 | help |
| 213 | Sets the address in DRAM where verstage should be loaded if running |
| 214 | as a separate stage on x86. |
| 215 | |
| 216 | config VERSTAGE_SIZE |
| 217 | hex |
| 218 | depends on VBOOT_SEPARATE_VERSTAGE |
| 219 | default 0x80000 |
| 220 | help |
| 221 | Sets the size of DRAM allocation for verstage in linker script if |
| 222 | running as a separate stage on x86. |
| 223 | |
Raul E Rangel | 61c9cd9 | 2021-11-02 11:51:48 -0600 | [diff] [blame] | 224 | config ASYNC_FILE_LOADING |
| 225 | bool "Loads files from SPI asynchronously" |
| 226 | select COOP_MULTITASKING |
| 227 | select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA |
Raul E Rangel | dcd8114 | 2021-11-02 11:51:48 -0600 | [diff] [blame] | 228 | select CBFS_PRELOAD |
Raul E Rangel | 61c9cd9 | 2021-11-02 11:51:48 -0600 | [diff] [blame] | 229 | help |
| 230 | When enabled, the platform will use the LPC SPI DMA controller to |
| 231 | asynchronously load contents from the SPI ROM. This will improve |
| 232 | boot time because the CPUs can be performing useful work while the |
| 233 | SPI contents are being preloaded. |
| 234 | |
Raul E Rangel | dcd8114 | 2021-11-02 11:51:48 -0600 | [diff] [blame] | 235 | config CBFS_CACHE_SIZE |
| 236 | hex |
| 237 | default 0x40000 if CBFS_PRELOAD |
| 238 | |
Raul E Rangel | 72616b3 | 2021-02-05 16:48:42 -0700 | [diff] [blame] | 239 | config RO_REGION_ONLY |
| 240 | string |
| 241 | depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A |
| 242 | default "apu/amdfw" |
| 243 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 244 | config ECAM_MMCONF_BASE_ADDRESS |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 245 | default 0xF8000000 |
| 246 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 247 | config ECAM_MMCONF_BUS_NUMBER |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 248 | default 64 |
| 249 | |
Felix Held | 8861562 | 2021-01-19 23:51:45 +0100 | [diff] [blame] | 250 | config MAX_CPUS |
| 251 | int |
| 252 | default 16 |
Felix Held | b77387f | 2021-04-23 22:16:04 +0200 | [diff] [blame] | 253 | help |
| 254 | Maximum number of threads the platform can have. |
Felix Held | 8861562 | 2021-01-19 23:51:45 +0100 | [diff] [blame] | 255 | |
Felix Held | 8a3d4d5 | 2021-01-13 03:06:21 +0100 | [diff] [blame] | 256 | config CONSOLE_UART_BASE_ADDRESS |
| 257 | depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART |
| 258 | hex |
| 259 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 260 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| 261 | |
Felix Held | ee2a365 | 2021-02-09 23:43:17 +0100 | [diff] [blame] | 262 | config SMM_TSEG_SIZE |
| 263 | hex |
Felix Held | e22eef7 | 2021-02-10 22:22:07 +0100 | [diff] [blame] | 264 | default 0x800000 if HAVE_SMI_HANDLER |
Felix Held | ee2a365 | 2021-02-09 23:43:17 +0100 | [diff] [blame] | 265 | default 0x0 |
| 266 | |
| 267 | config SMM_RESERVED_SIZE |
| 268 | hex |
| 269 | default 0x180000 |
| 270 | |
| 271 | config SMM_MODULE_STACK_SIZE |
| 272 | hex |
| 273 | default 0x800 |
| 274 | |
Felix Held | 90b0701 | 2021-04-15 20:23:56 +0200 | [diff] [blame] | 275 | config ACPI_BERT |
| 276 | bool "Build ACPI BERT Table" |
| 277 | default y |
| 278 | depends on HAVE_ACPI_TABLES |
| 279 | help |
| 280 | Report Machine Check errors identified in POST to the OS in an |
| 281 | ACPI Boot Error Record Table. |
| 282 | |
| 283 | config ACPI_BERT_SIZE |
| 284 | hex |
| 285 | default 0x4000 if ACPI_BERT |
| 286 | default 0x0 |
| 287 | help |
| 288 | Specify the amount of DRAM reserved for gathering the data used to |
| 289 | generate the ACPI table. |
| 290 | |
Zheng Bao | 7b13e4e | 2021-03-16 16:13:56 +0800 | [diff] [blame] | 291 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 292 | int |
| 293 | default 150 |
| 294 | |
Raul E Rangel | 95b3dc3 | 2021-03-24 16:53:37 -0600 | [diff] [blame] | 295 | config DISABLE_SPI_FLASH_ROM_SHARING |
| 296 | def_bool n |
| 297 | help |
| 298 | Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin |
| 299 | which indicates a board level ROM transaction request. This |
| 300 | removes arbitration with board and assumes the chipset controls |
| 301 | the SPI flash bus entirely. |
| 302 | |
Felix Held | 27b295b | 2021-03-25 01:20:41 +0100 | [diff] [blame] | 303 | config DISABLE_KEYBOARD_RESET_PIN |
| 304 | bool |
| 305 | help |
| 306 | Instruct the SoC to not use the state of GPIO_129 as keyboard reset |
| 307 | signal. When this pin is used as GPIO and the keyboard reset |
| 308 | functionality isn't disabled, configuring it as an output and driving |
| 309 | it as 0 will cause a reset. |
| 310 | |
Jason Glenesk | 79542fa | 2021-03-10 03:50:57 -0800 | [diff] [blame] | 311 | config ACPI_SSDT_PSD_INDEPENDENT |
| 312 | bool "Allow core p-state independent transitions" |
| 313 | default y |
| 314 | help |
| 315 | AMD recommends the ACPI _PSD object to be configured to cause |
| 316 | cores to transition between p-states independently. A vendor may |
| 317 | choose to generate _PSD object to allow cores to transition together. |
| 318 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 319 | menu "PSP Configuration Options" |
| 320 | |
| 321 | config AMD_FWM_POSITION_INDEX |
| 322 | int "Firmware Directory Table location (0 to 5)" |
| 323 | range 0 5 |
| 324 | default 0 if BOARD_ROMSIZE_KB_512 |
| 325 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 326 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 327 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 328 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 329 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 330 | help |
| 331 | Typically this is calculated by the ROM size, but there may |
| 332 | be situations where you want to put the firmware directory |
| 333 | table in a different location. |
| 334 | 0: 512 KB - 0xFFFA0000 |
| 335 | 1: 1 MB - 0xFFF20000 |
| 336 | 2: 2 MB - 0xFFE20000 |
| 337 | 3: 4 MB - 0xFFC20000 |
| 338 | 4: 8 MB - 0xFF820000 |
| 339 | 5: 16 MB - 0xFF020000 |
| 340 | |
| 341 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 342 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 343 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 344 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 345 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 346 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 347 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 348 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 349 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 350 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 351 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 352 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 353 | |
| 354 | config AMDFW_CONFIG_FILE |
| 355 | string |
| 356 | default "src/soc/amd/cezanne/fw.cfg" |
| 357 | |
Rob Barnes | e09b681 | 2021-04-15 17:21:19 -0600 | [diff] [blame] | 358 | config PSP_DISABLE_POSTCODES |
| 359 | bool "Disable PSP post codes" |
| 360 | help |
| 361 | Disables the output of port80 post codes from PSP. |
| 362 | |
Karthikeyan Ramasubramanian | 1a24d84 | 2022-03-16 16:27:49 -0600 | [diff] [blame] | 363 | config PSP_POSTCODES_ON_ESPI |
| 364 | bool "Use eSPI bus for PSP post codes" |
| 365 | depends on !PSP_DISABLE_POSTCODES |
| 366 | default y |
| 367 | help |
| 368 | Select to send PSP port80 post codes on eSPI bus. |
| 369 | If not selected, PSP port80 codes will be sent on LPC bus. |
| 370 | |
Raul E Rangel | fa4d051 | 2022-02-01 11:12:33 -0700 | [diff] [blame] | 371 | config PSP_INIT_ESPI |
| 372 | bool "Initialize eSPI in PSP Stage 2 Boot Loader" |
Rob Barnes | e09b681 | 2021-04-15 17:21:19 -0600 | [diff] [blame] | 373 | help |
Raul E Rangel | fa4d051 | 2022-02-01 11:12:33 -0700 | [diff] [blame] | 374 | Select to initialize the eSPI controller in the PSP Stage 2 Boot |
| 375 | Loader. |
Rob Barnes | e09b681 | 2021-04-15 17:21:19 -0600 | [diff] [blame] | 376 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 377 | config PSP_LOAD_MP2_FW |
| 378 | bool |
| 379 | default n |
| 380 | help |
| 381 | Include the MP2 firmwares and configuration into the PSP build. |
| 382 | |
| 383 | If unsure, answer 'n' |
| 384 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 385 | config PSP_UNLOCK_SECURE_DEBUG |
| 386 | bool "Unlock secure debug" |
| 387 | default y |
| 388 | help |
| 389 | Select this item to enable secure debug options in PSP. |
| 390 | |
Raul E Rangel | 97b8b17 | 2021-02-24 16:59:32 -0700 | [diff] [blame] | 391 | config HAVE_PSP_WHITELIST_FILE |
| 392 | bool "Include a debug whitelist file in PSP build" |
| 393 | default n |
| 394 | help |
| 395 | Support secured unlock prior to reset using a whitelisted |
| 396 | serial number. This feature requires a signed whitelist image |
| 397 | and bootloader from AMD. |
| 398 | |
| 399 | If unsure, answer 'n' |
| 400 | |
| 401 | config PSP_WHITELIST_FILE |
| 402 | string "Debug whitelist file path" |
| 403 | depends on HAVE_PSP_WHITELIST_FILE |
| 404 | default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin" |
| 405 | |
Zheng Bao | c5b912f7 | 2022-02-11 11:53:32 +0800 | [diff] [blame] | 406 | config HAVE_SPL_FILE |
| 407 | bool "Have a mainboard specific SPL table file" |
| 408 | default n |
| 409 | help |
| 410 | Have a mainboard specific SPL table file, which is created by AMD |
| 411 | and put to 3rdparty/blobs. |
| 412 | |
| 413 | If unsure, answer 'n' |
| 414 | |
| 415 | config SPL_TABLE_FILE |
| 416 | string "SPL table file" |
| 417 | depends on HAVE_SPL_FILE |
| 418 | default "3rdparty/amd_blobs/cezanne/PSP/TypeId0x55_SplTableBl_CZN.sbin" |
| 419 | |
Martin Roth | fdad5ad | 2021-04-16 11:36:01 -0600 | [diff] [blame] | 420 | config PSP_SOFTFUSE_BITS |
| 421 | string "PSP Soft Fuse bits to enable" |
| 422 | default "28 6" |
| 423 | help |
| 424 | Space separated list of Soft Fuse bits to enable. |
| 425 | Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) |
| 426 | Bit 7: Disable PSP postcodes on Renoir and newer chips only |
| 427 | (Set by PSP_DISABLE_PORT80) |
| 428 | Bit 15: PSP post code destination: 0=LPC 1=eSPI |
| 429 | (Set by PSP_INITIALIZE_ESPI) |
| 430 | Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) |
| 431 | |
| 432 | See #55758 (NDA) for additional bit definitions. |
| 433 | |
Kangheui Won | 66c5f25 | 2021-04-20 17:30:29 +1000 | [diff] [blame] | 434 | config PSP_VERSTAGE_FILE |
| 435 | string "Specify the PSP_verstage file path" |
| 436 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
Raul E Rangel | 21c70b1 | 2021-07-16 14:36:01 -0600 | [diff] [blame] | 437 | default "\$(obj)/psp_verstage.bin" |
Kangheui Won | 66c5f25 | 2021-04-20 17:30:29 +1000 | [diff] [blame] | 438 | help |
| 439 | Add psp_verstage file to the build & PSP Directory Table |
| 440 | |
| 441 | config PSP_VERSTAGE_SIGNING_TOKEN |
| 442 | string "Specify the PSP_verstage Signature Token file path" |
| 443 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 444 | default "" |
| 445 | help |
| 446 | Add psp_verstage signature token to the build & PSP Directory Table |
| 447 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 448 | endmenu |
| 449 | |
Raul E Rangel | 06d1e4d | 2021-04-09 14:42:06 -0600 | [diff] [blame] | 450 | config VBOOT |
| 451 | select VBOOT_VBNV_CMOS |
| 452 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 453 | |
Kangheui Won | 66c5f25 | 2021-04-20 17:30:29 +1000 | [diff] [blame] | 454 | config VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 455 | def_bool n |
| 456 | depends on VBOOT |
| 457 | select ARCH_VERSTAGE_ARMV7 |
| 458 | help |
| 459 | Runs verstage on the PSP. Only available on |
Jon Murphy | c4e9045 | 2022-06-28 10:36:23 -0600 | [diff] [blame] | 460 | certain ChromeOS branded parts from AMD. |
Kangheui Won | 66c5f25 | 2021-04-20 17:30:29 +1000 | [diff] [blame] | 461 | |
| 462 | config VBOOT_HASH_BLOCK_SIZE |
| 463 | hex |
| 464 | default 0x9000 |
| 465 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 466 | help |
| 467 | Because the bulk of the time in psp_verstage to hash the RO cbfs is |
| 468 | spent in the overhead of doing svc calls, increasing the hash block |
| 469 | size significantly cuts the verstage hashing time as seen below. |
| 470 | |
| 471 | 4k takes 180ms |
| 472 | 16k takes 44ms |
| 473 | 32k takes 33.7ms |
| 474 | 36k takes 32.5ms |
| 475 | There's actually still room for an even bigger stack, but we've |
| 476 | reached a point of diminishing returns. |
| 477 | |
| 478 | config CMOS_RECOVERY_BYTE |
| 479 | hex |
| 480 | default 0x51 |
| 481 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 482 | help |
| 483 | If the workbuf is not passed from the PSP to coreboot, set the |
| 484 | recovery flag and reboot. The PSP will read this byte, mark the |
| 485 | recovery request in VBNV, and reset the system into recovery mode. |
| 486 | |
| 487 | This is the byte before the default first byte used by VBNV |
| 488 | (0x26 + 0x0E - 1) |
| 489 | |
Matt DeVillier | f9fea86 | 2022-10-04 16:41:28 -0500 | [diff] [blame] | 490 | if VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK |
Kangheui Won | 1b2eeb1 | 2021-05-06 13:09:12 +1000 | [diff] [blame] | 491 | |
| 492 | config RWA_REGION_ONLY |
| 493 | string |
| 494 | default "apu/amdfw_a" |
| 495 | help |
| 496 | Add a space-delimited list of filenames that should only be in the |
| 497 | RW-A section. |
| 498 | |
Matt DeVillier | f9fea86 | 2022-10-04 16:41:28 -0500 | [diff] [blame] | 499 | endif # VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 500 | |
| 501 | if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 502 | |
Kangheui Won | 1b2eeb1 | 2021-05-06 13:09:12 +1000 | [diff] [blame] | 503 | config RWB_REGION_ONLY |
| 504 | string |
| 505 | default "apu/amdfw_b" |
| 506 | help |
| 507 | Add a space-delimited list of filenames that should only be in the |
| 508 | RW-B section. |
| 509 | |
| 510 | endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 511 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 512 | endif # SOC_AMD_CEZANNE |