soc/amd/cezanne: Port ACPI p-state and c-state entries from picasso
Add generate_cpu_entries to device operations. Add support to
generate cpu p-state and c-state SSDT entries.
BUG=b:184151560
TEST=Dump and verify SSDT entry for CPU p-states and c-states.
Change-Id: I77d8078b94fb661dc045b4184955c8cbec373d12
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 6f494bb..cee86f9 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -216,6 +216,14 @@
functionality isn't disabled, configuring it as an output and driving
it as 0 will cause a reset.
+config ACPI_SSDT_PSD_INDEPENDENT
+ bool "Allow core p-state independent transitions"
+ default y
+ help
+ AMD recommends the ACPI _PSD object to be configured to cause
+ cores to transition between p-states independently. A vendor may
+ choose to generate _PSD object to allow cores to transition together.
+
menu "PSP Configuration Options"
config AMD_FWM_POSITION_INDEX