| Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | config SOC_AMD_CEZANNE |
| 4 | bool |
| 5 | help |
| 6 | AMD Cezanne support |
| 7 | |
| 8 | if SOC_AMD_CEZANNE |
| 9 | |
| 10 | config SOC_SPECIFIC_OPTIONS |
| 11 | def_bool y |
| 12 | select ARCH_BOOTBLOCK_X86_32 |
| 13 | select ARCH_VERSTAGE_X86_32 |
| 14 | select ARCH_ROMSTAGE_X86_32 |
| 15 | select ARCH_RAMSTAGE_X86_32 |
| Felix Held | 44f4153 | 2020-12-09 02:01:16 +0100 | [diff] [blame] | 16 | select HAVE_CF9_RESET |
| Felix Held | 4be064a | 2020-12-08 17:21:04 +0100 | [diff] [blame] | 17 | select IOAPIC |
| Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 18 | select RESET_VECTOR_IN_RAM |
| 19 | select SOC_AMD_COMMON |
| Felix Held | 64de2c1 | 2020-12-05 20:53:59 +0100 | [diff] [blame] | 20 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
| Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 21 | select SOC_AMD_COMMON_BLOCK_NONCAR |
| 22 | select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |
| Felix Held | 4be064a | 2020-12-08 17:21:04 +0100 | [diff] [blame] | 23 | select SOC_AMD_COMMON_BLOCK_SMBUS |
| Zheng Bao | 02a5ddd | 2020-12-15 22:16:51 +0800 | [diff] [blame^] | 24 | select SOC_AMD_COMMON_BLOCK_SMI |
| Felix Held | 65783fb | 2020-12-04 17:38:46 +0100 | [diff] [blame] | 25 | select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H |
| Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 26 | |
| 27 | config EARLY_RESERVED_DRAM_BASE |
| 28 | hex |
| 29 | default 0x2000000 |
| 30 | help |
| 31 | This variable defines the base address of the DRAM which is reserved |
| 32 | for usage by coreboot in early stages (i.e. before ramstage is up). |
| 33 | This memory gets reserved in BIOS tables to ensure that the OS does |
| 34 | not use it, thus preventing corruption of OS memory in case of S3 |
| 35 | resume. |
| 36 | |
| 37 | config EARLYRAM_BSP_STACK_SIZE |
| 38 | hex |
| 39 | default 0x1000 |
| 40 | |
| 41 | config PSP_APOB_DRAM_ADDRESS |
| 42 | hex |
| 43 | default 0x2001000 |
| 44 | help |
| 45 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 46 | Block. |
| 47 | |
| 48 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 49 | hex |
| 50 | default 0x1600 |
| 51 | help |
| 52 | Increase this value if preram cbmem console is getting truncated |
| 53 | |
| Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 54 | config C_ENV_BOOTBLOCK_SIZE |
| 55 | hex |
| 56 | default 0x10000 |
| 57 | help |
| 58 | Sets the size of the bootblock stage that should be loaded in DRAM. |
| 59 | This variable controls the DRAM allocation size in linker script |
| 60 | for bootblock stage. |
| 61 | |
| Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 62 | config ROMSTAGE_ADDR |
| 63 | hex |
| 64 | default 0x2040000 |
| 65 | help |
| 66 | Sets the address in DRAM where romstage should be loaded. |
| 67 | |
| 68 | config ROMSTAGE_SIZE |
| 69 | hex |
| 70 | default 0x80000 |
| 71 | help |
| 72 | Sets the size of DRAM allocation for romstage in linker script. |
| 73 | |
| 74 | config FSP_M_ADDR |
| 75 | hex |
| 76 | default 0x20C0000 |
| 77 | help |
| 78 | Sets the address in DRAM where FSP-M should be loaded. cbfstool |
| 79 | performs relocation of FSP-M to this address. |
| 80 | |
| 81 | config FSP_M_SIZE |
| 82 | hex |
| 83 | default 0x80000 |
| 84 | help |
| 85 | Sets the size of DRAM allocation for FSP-M in linker script. |
| 86 | |
| 87 | config RAMBASE |
| 88 | hex |
| 89 | default 0x10000000 |
| 90 | |
| 91 | config CPU_ADDR_BITS |
| 92 | int |
| 93 | default 48 |
| 94 | |
| 95 | config MMCONF_BASE_ADDRESS |
| 96 | hex |
| 97 | default 0xF8000000 |
| 98 | |
| 99 | config MMCONF_BUS_NUMBER |
| 100 | int |
| 101 | default 64 |
| 102 | |
| 103 | endif # SOC_AMD_CEZANNE |