Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | config SOC_AMD_CEZANNE |
| 4 | bool |
| 5 | help |
| 6 | AMD Cezanne support |
| 7 | |
| 8 | if SOC_AMD_CEZANNE |
| 9 | |
| 10 | config SOC_SPECIFIC_OPTIONS |
| 11 | def_bool y |
| 12 | select ARCH_BOOTBLOCK_X86_32 |
| 13 | select ARCH_VERSTAGE_X86_32 |
| 14 | select ARCH_ROMSTAGE_X86_32 |
| 15 | select ARCH_RAMSTAGE_X86_32 |
Raul E Rangel | 5461662 | 2021-02-05 17:29:12 -0700 | [diff] [blame] | 16 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
Felix Held | c963499 | 2021-01-26 21:35:39 +0100 | [diff] [blame] | 17 | select FSP_COMPRESS_FSP_M_LZMA |
| 18 | select FSP_COMPRESS_FSP_S_LZMA |
Felix Held | 8602495 | 2021-02-03 23:44:28 +0100 | [diff] [blame^] | 19 | select HAVE_ACPI_TABLES |
Felix Held | 44f4153 | 2020-12-09 02:01:16 +0100 | [diff] [blame] | 20 | select HAVE_CF9_RESET |
Felix Held | ee2a365 | 2021-02-09 23:43:17 +0100 | [diff] [blame] | 21 | select HAVE_SMI_HANDLER |
Felix Held | cb97734 | 2021-01-19 20:36:38 +0100 | [diff] [blame] | 22 | select IDT_IN_EVERY_STAGE |
Felix Held | 4be064a | 2020-12-08 17:21:04 +0100 | [diff] [blame] | 23 | select IOAPIC |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 24 | select PLATFORM_USES_FSP2_0 |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 25 | select RESET_VECTOR_IN_RAM |
Felix Held | 7cd81b9 | 2021-02-11 14:58:08 +0100 | [diff] [blame] | 26 | select RTC |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 27 | select SOC_AMD_COMMON |
Felix Held | bb4bee85 | 2021-02-10 16:53:53 +0100 | [diff] [blame] | 28 | select SOC_AMD_COMMON_BLOCK_ACPI |
Felix Held | 64de2c1 | 2020-12-05 20:53:59 +0100 | [diff] [blame] | 29 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
Felix Held | 62ef88f | 2020-12-08 23:18:19 +0100 | [diff] [blame] | 30 | select SOC_AMD_COMMON_BLOCK_AOAC |
Felix Held | 07462ef | 2020-12-11 15:55:45 +0100 | [diff] [blame] | 31 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
Zheng Bao | 3da5569 | 2021-01-26 18:30:18 +0800 | [diff] [blame] | 32 | select SOC_AMD_COMMON_BLOCK_LPC |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 33 | select SOC_AMD_COMMON_BLOCK_NONCAR |
Raul E Rangel | a6529e7 | 2021-02-09 14:38:36 -0700 | [diff] [blame] | 34 | select SOC_AMD_COMMON_BLOCK_PCI |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 35 | select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |
Felix Held | 338d670 | 2021-01-29 23:13:56 +0100 | [diff] [blame] | 36 | select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
Felix Held | 4be064a | 2020-12-08 17:21:04 +0100 | [diff] [blame] | 37 | select SOC_AMD_COMMON_BLOCK_SMBUS |
Zheng Bao | 02a5ddd | 2020-12-15 22:16:51 +0800 | [diff] [blame] | 38 | select SOC_AMD_COMMON_BLOCK_SMI |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 39 | select SOC_AMD_COMMON_BLOCK_SMM |
Raul E Rangel | 5461662 | 2021-02-05 17:29:12 -0700 | [diff] [blame] | 40 | select SOC_AMD_COMMON_BLOCK_SPI |
Felix Held | 65783fb | 2020-12-04 17:38:46 +0100 | [diff] [blame] | 41 | select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H |
Felix Held | 8a3d4d5 | 2021-01-13 03:06:21 +0100 | [diff] [blame] | 42 | select SOC_AMD_COMMON_BLOCK_UART |
Felix Held | cc975c5 | 2021-01-23 00:18:08 +0100 | [diff] [blame] | 43 | select SSE2 |
Felix Held | 2976d32 | 2021-01-27 17:50:27 +0100 | [diff] [blame] | 44 | select SUPPORT_CPU_UCODE_IN_CBFS |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 45 | select UDK_2017_BINDING |
Felix Held | f09221c | 2021-01-22 23:50:54 +0100 | [diff] [blame] | 46 | select X86_AMD_FIXED_MTRRS |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 47 | |
Furquan Shaikh | 696f4ea | 2021-01-08 11:48:52 -0800 | [diff] [blame] | 48 | config CHIPSET_DEVICETREE |
| 49 | string |
| 50 | default "soc/amd/cezanne/chipset.cb" |
| 51 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 52 | config EARLY_RESERVED_DRAM_BASE |
| 53 | hex |
| 54 | default 0x2000000 |
| 55 | help |
| 56 | This variable defines the base address of the DRAM which is reserved |
| 57 | for usage by coreboot in early stages (i.e. before ramstage is up). |
| 58 | This memory gets reserved in BIOS tables to ensure that the OS does |
| 59 | not use it, thus preventing corruption of OS memory in case of S3 |
| 60 | resume. |
| 61 | |
| 62 | config EARLYRAM_BSP_STACK_SIZE |
| 63 | hex |
| 64 | default 0x1000 |
| 65 | |
| 66 | config PSP_APOB_DRAM_ADDRESS |
| 67 | hex |
| 68 | default 0x2001000 |
| 69 | help |
| 70 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 71 | Block. |
| 72 | |
| 73 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 74 | hex |
| 75 | default 0x1600 |
| 76 | help |
| 77 | Increase this value if preram cbmem console is getting truncated |
| 78 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 79 | config C_ENV_BOOTBLOCK_SIZE |
| 80 | hex |
| 81 | default 0x10000 |
| 82 | help |
| 83 | Sets the size of the bootblock stage that should be loaded in DRAM. |
| 84 | This variable controls the DRAM allocation size in linker script |
| 85 | for bootblock stage. |
| 86 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 87 | config ROMSTAGE_ADDR |
| 88 | hex |
| 89 | default 0x2040000 |
| 90 | help |
| 91 | Sets the address in DRAM where romstage should be loaded. |
| 92 | |
| 93 | config ROMSTAGE_SIZE |
| 94 | hex |
| 95 | default 0x80000 |
| 96 | help |
| 97 | Sets the size of DRAM allocation for romstage in linker script. |
| 98 | |
| 99 | config FSP_M_ADDR |
| 100 | hex |
| 101 | default 0x20C0000 |
| 102 | help |
| 103 | Sets the address in DRAM where FSP-M should be loaded. cbfstool |
| 104 | performs relocation of FSP-M to this address. |
| 105 | |
| 106 | config FSP_M_SIZE |
| 107 | hex |
| 108 | default 0x80000 |
| 109 | help |
| 110 | Sets the size of DRAM allocation for FSP-M in linker script. |
| 111 | |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 112 | config FSP_TEMP_RAM_SIZE |
| 113 | hex |
| 114 | default 0x40000 |
| 115 | help |
| 116 | The amount of coreboot-allocated heap and stack usage by the FSP. |
| 117 | |
Raul E Rangel | 72616b3 | 2021-02-05 16:48:42 -0700 | [diff] [blame] | 118 | config VERSTAGE_ADDR |
| 119 | hex |
| 120 | depends on VBOOT_SEPARATE_VERSTAGE |
| 121 | default 0x2140000 |
| 122 | help |
| 123 | Sets the address in DRAM where verstage should be loaded if running |
| 124 | as a separate stage on x86. |
| 125 | |
| 126 | config VERSTAGE_SIZE |
| 127 | hex |
| 128 | depends on VBOOT_SEPARATE_VERSTAGE |
| 129 | default 0x80000 |
| 130 | help |
| 131 | Sets the size of DRAM allocation for verstage in linker script if |
| 132 | running as a separate stage on x86. |
| 133 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 134 | config RAMBASE |
| 135 | hex |
| 136 | default 0x10000000 |
| 137 | |
Raul E Rangel | 72616b3 | 2021-02-05 16:48:42 -0700 | [diff] [blame] | 138 | config RO_REGION_ONLY |
| 139 | string |
| 140 | depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A |
| 141 | default "apu/amdfw" |
| 142 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 143 | config CPU_ADDR_BITS |
| 144 | int |
| 145 | default 48 |
| 146 | |
| 147 | config MMCONF_BASE_ADDRESS |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 148 | default 0xF8000000 |
| 149 | |
| 150 | config MMCONF_BUS_NUMBER |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 151 | default 64 |
| 152 | |
Felix Held | 8861562 | 2021-01-19 23:51:45 +0100 | [diff] [blame] | 153 | config MAX_CPUS |
| 154 | int |
| 155 | default 16 |
| 156 | |
Felix Held | 8a3d4d5 | 2021-01-13 03:06:21 +0100 | [diff] [blame] | 157 | config CONSOLE_UART_BASE_ADDRESS |
| 158 | depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART |
| 159 | hex |
| 160 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 161 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| 162 | |
Felix Held | ee2a365 | 2021-02-09 23:43:17 +0100 | [diff] [blame] | 163 | config SMM_TSEG_SIZE |
| 164 | hex |
Felix Held | e22eef7 | 2021-02-10 22:22:07 +0100 | [diff] [blame] | 165 | default 0x800000 if HAVE_SMI_HANDLER |
Felix Held | ee2a365 | 2021-02-09 23:43:17 +0100 | [diff] [blame] | 166 | default 0x0 |
| 167 | |
| 168 | config SMM_RESERVED_SIZE |
| 169 | hex |
| 170 | default 0x180000 |
| 171 | |
| 172 | config SMM_MODULE_STACK_SIZE |
| 173 | hex |
| 174 | default 0x800 |
| 175 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 176 | menu "PSP Configuration Options" |
| 177 | |
| 178 | config AMD_FWM_POSITION_INDEX |
| 179 | int "Firmware Directory Table location (0 to 5)" |
| 180 | range 0 5 |
| 181 | default 0 if BOARD_ROMSIZE_KB_512 |
| 182 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 183 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 184 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 185 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 186 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 187 | help |
| 188 | Typically this is calculated by the ROM size, but there may |
| 189 | be situations where you want to put the firmware directory |
| 190 | table in a different location. |
| 191 | 0: 512 KB - 0xFFFA0000 |
| 192 | 1: 1 MB - 0xFFF20000 |
| 193 | 2: 2 MB - 0xFFE20000 |
| 194 | 3: 4 MB - 0xFFC20000 |
| 195 | 4: 8 MB - 0xFF820000 |
| 196 | 5: 16 MB - 0xFF020000 |
| 197 | |
| 198 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 199 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 200 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 201 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 202 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 203 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 204 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 205 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 206 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 207 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 208 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 209 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 210 | |
| 211 | config AMDFW_CONFIG_FILE |
| 212 | string |
| 213 | default "src/soc/amd/cezanne/fw.cfg" |
| 214 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 215 | config PSP_LOAD_MP2_FW |
| 216 | bool |
| 217 | default n |
| 218 | help |
| 219 | Include the MP2 firmwares and configuration into the PSP build. |
| 220 | |
| 221 | If unsure, answer 'n' |
| 222 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 223 | config PSP_UNLOCK_SECURE_DEBUG |
| 224 | bool "Unlock secure debug" |
| 225 | default y |
| 226 | help |
| 227 | Select this item to enable secure debug options in PSP. |
| 228 | |
| 229 | endmenu |
| 230 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 231 | endif # SOC_AMD_CEZANNE |