soc/amd/common/psp_verstage: Write postcodes after ESPI init
On boards where PSP uses ESPI to write postcodes, update the verstage to
do it after ESPI initialization.
BUG=b:224543620
TEST=Build and boot to OS in Nipperkin. Ensure that there are no
attempts to write the post code from PSP verstage before ESPI
initialization.
Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mohan Viswanathan
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 81cf974..48944c8 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -345,6 +345,14 @@
help
Disables the output of port80 post codes from PSP.
+config PSP_POSTCODES_ON_ESPI
+ bool "Use eSPI bus for PSP post codes"
+ depends on !PSP_DISABLE_POSTCODES
+ default y
+ help
+ Select to send PSP port80 post codes on eSPI bus.
+ If not selected, PSP port80 codes will be sent on LPC bus.
+
config PSP_INIT_ESPI
bool "Initialize eSPI in PSP Stage 2 Boot Loader"
help