Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 17 | #include <assert.h> |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 18 | #include <stdint.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 19 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 20 | #include <device/pci_ops.h> |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 21 | #include <console/console.h> |
| 22 | #include <commonlib/helpers.h> |
| 23 | #include <delay.h> |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 24 | #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) |
| 25 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 26 | #else |
| 27 | #include <southbridge/intel/i82801jx/i82801jx.h> |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 28 | #endif |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 29 | #include <string.h> |
Martin Roth | cbe3892 | 2016-01-05 19:40:41 -0700 | [diff] [blame] | 30 | #include "iomap.h" |
| 31 | #include "x4x.h" |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 32 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 33 | #define ME_UMA_SIZEMB 0 |
| 34 | |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 35 | u32 fsb2mhz(u32 speed) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 36 | { |
| 37 | return (speed * 267) + 800; |
| 38 | } |
| 39 | |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 40 | u32 ddr2mhz(u32 speed) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 41 | { |
| 42 | static const u16 mhz[] = { 0, 0, 667, 800, 1067, 1333 }; |
| 43 | |
| 44 | if (speed >= ARRAY_SIZE(mhz)) |
| 45 | return 0; |
| 46 | |
| 47 | return mhz[speed]; |
| 48 | } |
| 49 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 50 | |
| 51 | static void program_crossclock(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 52 | { |
| 53 | u8 i, j; |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 54 | u32 reg32; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 55 | MCHBAR16_OR(0xc1c, (1 << 15)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 56 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 57 | static const u32 clkxtab[6][3][13] = { |
Arthur Heymans | 8a3514d | 2016-10-27 23:56:08 +0200 | [diff] [blame] | 58 | /* MEMCLK 400 N/A */ |
| 59 | {{}, {}, {} }, |
| 60 | /* MEMCLK 533 N/A */ |
| 61 | {{}, {}, {} }, |
| 62 | /* MEMCLK 667 |
| 63 | * FSB 800 */ |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 64 | {{0x1f1f1f1f, 0x0d07070b, 0x00000000, 0x10000000, |
Arthur Heymans | 8a3514d | 2016-10-27 23:56:08 +0200 | [diff] [blame] | 65 | 0x20010208, 0x04080000, 0x10010002, 0x00000000, |
| 66 | 0x00000000, 0x02000000, 0x04000100, 0x08000000, |
| 67 | 0x10200204}, |
| 68 | /* FSB 1067 */ |
| 69 | {0x6d5b1f1f, 0x0f0f0f0f, 0x00000000, 0x20000000, |
| 70 | 0x80020410, 0x02040008, 0x10000100, 0x00000000, |
| 71 | 0x00000000, 0x04000000, 0x08000102, 0x20000000, |
| 72 | 0x40010208}, |
| 73 | /* FSB 1333 */ |
| 74 | {0x05050303, 0xffffffff, 0xffff0000, 0x00000000, |
| 75 | 0x08020000, 0x00000000, 0x00020001, 0x00000000, |
| 76 | 0x00000000, 0x00000000, 0x08010204, 0x00000000, |
| 77 | 0x04010000} }, |
| 78 | /* MEMCLK 800 |
| 79 | * FSB 800 */ |
| 80 | {{0xffffffff, 0x05030305, 0x0000ffff, 0x0000000, |
| 81 | 0x08010204, 0x00000000, 0x08010204, 0x0000000, |
| 82 | 0x00000000, 0x00000000, 0x00020001, 0x0000000, |
| 83 | 0x04080102}, |
| 84 | /* FSB 1067 */ |
| 85 | {0x07070707, 0x06030303, 0x00000000, 0x00000000, |
| 86 | 0x08010200, 0x00000000, 0x04000102, 0x00000000, |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 87 | 0x00000000, 0x00000000, 0x00020100, 0x00000000, |
| 88 | 0x04080100}, |
Arthur Heymans | 8a3514d | 2016-10-27 23:56:08 +0200 | [diff] [blame] | 89 | /* FSB 1333 */ |
| 90 | {0x0d0b0707, 0x3e1f1f2f, 0x01010000, 0x00000000, |
| 91 | 0x10020400, 0x02000000, 0x00040100, 0x00000000, |
| 92 | 0x00000000, 0x04080000, 0x00100102, 0x00000000, |
| 93 | 0x08100200} }, |
| 94 | /* MEMCLK 1067 */ |
| 95 | {{}, |
| 96 | /* FSB 1067 */ |
| 97 | {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000, |
| 98 | 0x04080102, 0x00000000, 0x08010204, 0x00000000, |
| 99 | 0x00000000, 0x00000000, 0x00020001, 0x00000000, |
| 100 | 0x02040801}, |
| 101 | /* FSB 1333 */ |
| 102 | {0x0f0f0f0f, 0x5b1f1f6d, 0x00000000, 0x00000000, |
| 103 | 0x08010204, 0x04000000, 0x00080102, 0x00000000, |
| 104 | 0x00000000, 0x02000408, 0x00100001, 0x00000000, |
| 105 | 0x04080102} }, |
| 106 | /* MEMCLK 1333 */ |
| 107 | {{}, {}, |
| 108 | /* FSB 1333 */ |
| 109 | {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000, |
| 110 | 0x04080102, 0x00000000, 0x04080102, 0x00000000, |
| 111 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 112 | 0x02040801} } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 113 | }; |
| 114 | |
| 115 | i = (u8)s->selected_timings.mem_clk; |
| 116 | j = (u8)s->selected_timings.fsb_clk; |
| 117 | |
| 118 | MCHBAR32(0xc04) = clkxtab[i][j][0]; |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 119 | reg32 = clkxtab[i][j][1]; |
| 120 | if (s->spd_type == DDR3 && s->max_fsb == FSB_CLOCK_1333MHz |
| 121 | && s->selected_timings.mem_clk == MEM_CLOCK_800MHz) { |
| 122 | reg32 &= ~(0xff << 24); |
| 123 | reg32 |= 0x3d << 24; |
| 124 | } |
| 125 | MCHBAR32(0xc50) = reg32; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 126 | MCHBAR32(0xc54) = clkxtab[i][j][2]; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 127 | MCHBAR8_OR(0xc08, (1 << 7)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 128 | MCHBAR32(0x6d8) = clkxtab[i][j][3]; |
| 129 | MCHBAR32(0x6e0) = clkxtab[i][j][3]; |
| 130 | MCHBAR32(0x6dc) = clkxtab[i][j][4]; |
| 131 | MCHBAR32(0x6e4) = clkxtab[i][j][4]; |
| 132 | MCHBAR32(0x6e8) = clkxtab[i][j][5]; |
| 133 | MCHBAR32(0x6f0) = clkxtab[i][j][5]; |
| 134 | MCHBAR32(0x6ec) = clkxtab[i][j][6]; |
| 135 | MCHBAR32(0x6f4) = clkxtab[i][j][6]; |
| 136 | MCHBAR32(0x6f8) = clkxtab[i][j][7]; |
| 137 | MCHBAR32(0x6fc) = clkxtab[i][j][8]; |
| 138 | MCHBAR32(0x708) = clkxtab[i][j][11]; |
| 139 | MCHBAR32(0x70c) = clkxtab[i][j][12]; |
| 140 | } |
| 141 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 142 | static void setioclk_dram(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 143 | { |
| 144 | MCHBAR32(0x1bc) = 0x08060402; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 145 | MCHBAR16_OR(0x1c0, 0x200); |
| 146 | MCHBAR16_OR(0x1c0, 0x100); |
| 147 | MCHBAR16_OR(0x1c0, 0x20); |
| 148 | MCHBAR16_AND(0x1c0, ~1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 149 | switch (s->selected_timings.mem_clk) { |
| 150 | default: |
| 151 | case MEM_CLOCK_800MHz: |
| 152 | case MEM_CLOCK_1066MHz: |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 153 | MCHBAR8_AND_OR(0x5d9, ~0x2, 0x2); |
| 154 | MCHBAR8_AND_OR(0x9d9, ~0x2, 0x2); |
| 155 | MCHBAR8_AND_OR(0x189, ~0xf0, 0xc0); |
| 156 | MCHBAR8_AND_OR(0x189, ~0xf0, 0xe0); |
| 157 | MCHBAR8_AND_OR(0x189, ~0xf0, 0xa0); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 158 | break; |
| 159 | case MEM_CLOCK_667MHz: |
| 160 | case MEM_CLOCK_1333MHz: |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 161 | MCHBAR8_AND(0x5d9, ~0x2); |
| 162 | MCHBAR8_AND(0x9d9, ~0x2); |
| 163 | MCHBAR8_AND_OR(0x189, ~0xf0, 0x40); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 164 | break; |
| 165 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 166 | MCHBAR32_OR(0x594, 1 << 31); |
| 167 | MCHBAR32_OR(0x994, 1 << 31); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 168 | } |
| 169 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 170 | static void launch_dram(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 171 | { |
| 172 | u8 i; |
Arthur Heymans | 7a3a319 | 2017-05-15 10:26:29 +0200 | [diff] [blame] | 173 | u32 launch1; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 174 | u32 launch2 = 0; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 175 | |
Arthur Heymans | 7a3a319 | 2017-05-15 10:26:29 +0200 | [diff] [blame] | 176 | static const u32 ddr3_launch1_tab[2][3] = { |
| 177 | /* 1N */ |
| 178 | {0x58000007, /* DDR3 800 */ |
| 179 | 0x58000007, /* DDR3 1067 */ |
| 180 | 0x58100107}, /* DDR3 1333 */ |
| 181 | /* 2N */ |
| 182 | {0x58001117, /* DDR3 800 */ |
| 183 | 0x58001117, /* DDR3 1067 */ |
| 184 | 0x58001117} /* DDR3 1333 */ |
| 185 | }; |
| 186 | |
| 187 | static const u32 ddr3_launch2_tab[2][3][6] = { |
| 188 | { /* 1N */ |
| 189 | /* DDR3 800 */ |
| 190 | {0x08030000, /* CL = 5 */ |
| 191 | 0x0C040100}, /* CL = 6 */ |
| 192 | /* DDR3 1066 */ |
| 193 | {0x00000000, /* CL = 5 */ |
| 194 | 0x00000000, /* CL = 6 */ |
| 195 | 0x10050100, /* CL = 7 */ |
| 196 | 0x14260200}, /* CL = 8 */ |
| 197 | /* DDR3 1333 */ |
| 198 | {0x00000000, /* CL = 5 */ |
| 199 | 0x00000000, /* CL = 6 */ |
| 200 | 0x00000000, /* CL = 7 */ |
| 201 | 0x14060000, /* CL = 8 */ |
| 202 | 0x18070100, /* CL = 9 */ |
| 203 | 0x1C280200}, /* CL = 10 */ |
| 204 | |
| 205 | }, |
| 206 | { /* 2N */ |
| 207 | /* DDR3 800 */ |
| 208 | {0x00040101, /* CL = 5 */ |
| 209 | 0x00250201}, /* CL = 6 */ |
| 210 | /* DDR3 1066 */ |
| 211 | {0x00000000, /* CL = 5 */ |
| 212 | 0x00050101, /* CL = 6 */ |
| 213 | 0x04260201, /* CL = 7 */ |
| 214 | 0x08470301}, /* CL = 8 */ |
| 215 | /* DDR3 1333 */ |
| 216 | {0x00000000, /* CL = 5 */ |
| 217 | 0x00000000, /* CL = 6 */ |
| 218 | 0x00000000, /* CL = 7 */ |
| 219 | 0x08070100, /* CL = 8 */ |
| 220 | 0x0C280200, /* CL = 9 */ |
| 221 | 0x10490300} /* CL = 10 */ |
| 222 | } |
| 223 | }; |
| 224 | |
| 225 | if (s->spd_type == DDR2) { |
| 226 | launch1 = 0x58001117; |
| 227 | if (s->selected_timings.CAS == 5) |
| 228 | launch2 = 0x00220201; |
| 229 | else if (s->selected_timings.CAS == 6) |
| 230 | launch2 = 0x00230302; |
| 231 | else |
| 232 | die("Unsupported CAS\n"); |
| 233 | } else { /* DDR3 */ |
| 234 | /* Default 2N mode */ |
| 235 | s->nmode = 2; |
| 236 | |
| 237 | if (s->selected_timings.mem_clk <= MEM_CLOCK_1066MHz) |
| 238 | s->nmode = 1; |
| 239 | /* 2N on DDR3 1066 with with 2 dimms per channel */ |
| 240 | if ((s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) && |
| 241 | (BOTH_DIMMS_ARE_POPULATED(s->dimms, 0) || |
| 242 | BOTH_DIMMS_ARE_POPULATED(s->dimms, 1))) |
| 243 | s->nmode = 2; |
| 244 | launch1 = ddr3_launch1_tab[s->nmode - 1] |
| 245 | [s->selected_timings.mem_clk - MEM_CLOCK_800MHz]; |
| 246 | launch2 = ddr3_launch2_tab[s->nmode - 1] |
| 247 | [s->selected_timings.mem_clk - MEM_CLOCK_800MHz] |
| 248 | [s->selected_timings.CAS - 5]; |
| 249 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 250 | |
| 251 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
| 252 | MCHBAR32(0x400*i + 0x220) = launch1; |
| 253 | MCHBAR32(0x400*i + 0x224) = launch2; |
Arthur Heymans | 7a3a319 | 2017-05-15 10:26:29 +0200 | [diff] [blame] | 254 | MCHBAR32(0x400*i + 0x21c) = 0; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 255 | MCHBAR32_OR(0x400*i + 0x248, 1 << 23); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 256 | } |
| 257 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 258 | MCHBAR32_AND_OR(0x2c0, ~0x58000000, 0x48000000); |
| 259 | MCHBAR32_OR(0x2c0, 0x1e0); |
| 260 | MCHBAR32_AND_OR(0x2c4, ~0xf, 0xc); |
Arthur Heymans | 7a3a319 | 2017-05-15 10:26:29 +0200 | [diff] [blame] | 261 | if (s->spd_type == DDR3) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 262 | MCHBAR32_OR(0x2c4, 0x100); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 263 | } |
| 264 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 265 | static void clkset0(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 266 | { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 267 | MCHBAR16_AND_OR(0x400*ch + 0x5a0, ~0xc440, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 268 | (setting->clk_delay << 14) | |
| 269 | (setting->db_sel << 6) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 270 | (setting->db_en << 10)); |
| 271 | MCHBAR8_AND_OR(0x400*ch + 0x581, ~0x70, setting->pi << 4); |
| 272 | MCHBAR8_AND_OR(0x400*ch + 0x581, ~0xf, setting->tap); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 273 | } |
| 274 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 275 | static void clkset1(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 276 | { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 277 | MCHBAR32_AND_OR(0x400*ch + 0x5a0, ~0x30880, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 278 | (setting->clk_delay << 16) | |
| 279 | (setting->db_sel << 7) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 280 | (setting->db_en << 11)); |
| 281 | MCHBAR8_AND_OR(0x400*ch + 0x582, ~0x70, setting->pi << 4); |
| 282 | MCHBAR8_AND_OR(0x400*ch + 0x582, ~0xf, setting->tap); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 283 | } |
| 284 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 285 | static void ctrlset0(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 286 | { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 287 | MCHBAR32_AND_OR(0x400*ch + 0x59c, ~0x3300000, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 288 | (setting->clk_delay << 24) | |
| 289 | (setting->db_sel << 20) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 290 | (setting->db_en << 21)); |
| 291 | MCHBAR8_AND_OR(0x400*ch + 0x584, ~0x70, setting->pi << 4); |
| 292 | MCHBAR8_AND_OR(0x400*ch + 0x584, ~0xf, setting->tap); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 293 | } |
| 294 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 295 | static void ctrlset1(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 296 | { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 297 | MCHBAR32_AND_OR(0x400*ch + 0x59c, ~0x18c00000, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 298 | (setting->clk_delay << 27) | |
| 299 | (setting->db_sel << 22) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 300 | (setting->db_en << 23)); |
| 301 | MCHBAR8_AND_OR(0x400*ch + 0x585, ~0x70, setting->pi << 4); |
| 302 | MCHBAR8_AND_OR(0x400*ch + 0x585, ~0xf, setting->tap); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 303 | } |
| 304 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 305 | static void ctrlset2(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 306 | { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 307 | MCHBAR32_AND_OR(0x400*ch + 0x598, ~0x18c00000, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 308 | (setting->clk_delay << 14) | |
| 309 | (setting->db_sel << 12) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 310 | (setting->db_en << 13)); |
| 311 | MCHBAR8_AND_OR(0x400*ch + 0x586, ~0x70, setting->pi << 4); |
| 312 | MCHBAR8_AND_OR(0x400*ch + 0x586, ~0xf, setting->tap); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 313 | } |
| 314 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 315 | static void ctrlset3(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 316 | { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 317 | MCHBAR32_AND_OR(0x400*ch + 0x598, ~0x18c00000, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 318 | (setting->clk_delay << 10) | |
| 319 | (setting->db_sel << 8) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 320 | (setting->db_en << 9)); |
| 321 | MCHBAR8_AND_OR(0x400*ch + 0x587, ~0x70, setting->pi << 4); |
| 322 | MCHBAR8_AND_OR(0x400*ch + 0x587, ~0xf, setting->tap); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 323 | } |
| 324 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 325 | static void cmdset(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 326 | { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 327 | MCHBAR8_AND_OR(0x400*ch + 0x598, ~0x30, setting->clk_delay << 4); |
| 328 | MCHBAR8_AND_OR(0x400*ch + 0x594, ~0x60, |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 329 | (setting->db_sel << 5) | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 330 | (setting->db_en << 6)); |
| 331 | MCHBAR8_AND_OR(0x400*ch + 0x580, ~0x70, setting->pi << 4); |
| 332 | MCHBAR8_AND_OR(0x400*ch + 0x580, ~0xf, setting->tap); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 333 | } |
| 334 | |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 335 | /** |
| 336 | * All finer DQ and DQS DLL settings are set to the same value |
| 337 | * for each rank in a channel, while coarse is common. |
| 338 | */ |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 339 | void dqsset(u8 ch, u8 lane, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 340 | { |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 341 | int rank; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 342 | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 343 | MCHBAR32_AND_OR(0x400 * ch + 0x5fc, ~(1 << (lane * 4 + 1)), |
| 344 | setting->coarse << (lane * 4 + 1)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 345 | |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 346 | for (rank = 0; rank < 4; rank++) { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 347 | MCHBAR32_AND_OR(0x400 * ch + 0x5b4 + rank * 4, ~(0x201 << lane), |
| 348 | (setting->db_en << (9 + lane)) | |
| 349 | (setting->db_sel << lane)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 350 | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 351 | MCHBAR32_AND_OR(0x400*ch + 0x5c8 + rank * 4, |
| 352 | ~(0x3 << (16 + lane * 2)), |
| 353 | setting->clk_delay << (16+lane * 2)); |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 354 | |
| 355 | MCHBAR8(0x400*ch + 0x520 + lane * 4 + rank) = |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 356 | (MCHBAR8(0x400*ch + 0x520 + lane * 4) & ~0x7f) | |
| 357 | (setting->pi << 4) | |
| 358 | setting->tap; |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 359 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 360 | } |
| 361 | |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 362 | void dqset(u8 ch, u8 lane, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 363 | { |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 364 | int rank; |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 365 | MCHBAR32_AND_OR(0x400 * ch + 0x5fc, ~(1 << (lane * 4)), |
| 366 | setting->coarse << (lane * 4)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 367 | |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 368 | for (rank = 0; rank < 4; rank++) { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 369 | MCHBAR32_AND_OR(0x400 * ch + 0x5a4 + rank * 4, ~(0x201 << lane), |
| 370 | (setting->db_en << (9 + lane)) | |
| 371 | (setting->db_sel << lane)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 372 | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 373 | MCHBAR32_AND_OR(0x400 * ch + 0x5c8 + rank * 4, |
| 374 | ~(0x3 << (lane * 2)), setting->clk_delay << (2 * lane)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 375 | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 376 | MCHBAR8_AND_OR(0x400*ch + 0x500 + lane * 4 + rank, ~0x7f, |
| 377 | (setting->pi << 4) | setting->tap); |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 378 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 379 | } |
| 380 | |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 381 | void rt_set_dqs(u8 channel, u8 lane, u8 rank, |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 382 | struct rt_dqs_setting *dqs_setting) |
| 383 | { |
| 384 | u16 saved_tap = MCHBAR16(0x540 + 0x400 * channel + lane * 4); |
| 385 | u16 saved_pi = MCHBAR16(0x542 + 0x400 * channel + lane * 4); |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 386 | printk(RAM_SPEW, "RT DQS: ch%d, r%d, L%d: %d.%d\n", channel, rank, lane, |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 387 | dqs_setting->tap, |
| 388 | dqs_setting->pi); |
| 389 | |
| 390 | saved_tap &= ~(0xf << (rank * 4)); |
| 391 | saved_tap |= dqs_setting->tap << (rank * 4); |
| 392 | MCHBAR16(0x540 + 0x400 * channel + lane * 4) = saved_tap; |
| 393 | |
| 394 | saved_pi &= ~(0x7 << (rank * 3)); |
| 395 | saved_pi |= dqs_setting->pi << (rank * 3); |
| 396 | MCHBAR16(0x542 + 0x400 * channel + lane * 4) = saved_pi; |
| 397 | } |
| 398 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 399 | static void program_timings(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 400 | { |
| 401 | u8 i; |
| 402 | u8 twl, ta1, ta2, ta3, ta4; |
| 403 | u8 reg8; |
| 404 | u8 flag1 = 0; |
| 405 | u8 flag2 = 0; |
| 406 | u16 reg16; |
| 407 | u32 reg32; |
| 408 | u16 ddr, fsb; |
| 409 | u8 trpmod = 0; |
| 410 | u8 bankmod = 1; |
| 411 | u8 pagemod = 0; |
Arthur Heymans | eee4f6b | 2017-01-03 00:49:45 +0100 | [diff] [blame] | 412 | u8 adjusted_cas; |
| 413 | |
| 414 | adjusted_cas = s->selected_timings.CAS - 3; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 415 | |
| 416 | u16 fsb2ps[3] = { |
| 417 | 5000, // 800 |
| 418 | 3750, // 1067 |
| 419 | 3000 // 1333 |
| 420 | }; |
| 421 | |
| 422 | u16 ddr2ps[6] = { |
| 423 | 5000, // 400 |
| 424 | 3750, // 533 |
| 425 | 3000, // 667 |
| 426 | 2500, // 800 |
| 427 | 1875, // 1067 |
| 428 | 1500 // 1333 |
| 429 | }; |
| 430 | |
| 431 | u16 lut1[6] = { |
| 432 | 0, |
| 433 | 0, |
| 434 | 2600, |
| 435 | 3120, |
| 436 | 4171, |
| 437 | 5200 |
| 438 | }; |
| 439 | |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 440 | const static u8 ddr3_turnaround_tab[3][6][4] = { |
| 441 | { /* DDR3 800 */ |
| 442 | {0x9, 0x7, 0x7, 0x9}, /* CL = 5 */ |
| 443 | {0x9, 0x7, 0x8, 0x8}, /* CL = 6 */ |
| 444 | }, |
| 445 | { /* DDR3 1066 */ |
| 446 | {0x0, 0x0, 0x0, 0x0}, /* CL = 5 - Not supported */ |
| 447 | {0x9, 0x7, 0x7, 0x9}, /* CL = 6 */ |
| 448 | {0x9, 0x7, 0x8, 0x8}, /* CL = 7 */ |
| 449 | {0x9, 0x7, 0x9, 0x7} /* CL = 8 */ |
| 450 | }, |
| 451 | { /* DDR3 1333 */ |
| 452 | {0x0, 0x0, 0x0, 0x0}, /* CL = 5 - Not supported */ |
| 453 | {0x0, 0x0, 0x0, 0x0}, /* CL = 6 - Not supported */ |
| 454 | {0x0, 0x0, 0x0, 0x0}, /* CL = 7 - Not supported */ |
| 455 | {0x9, 0x7, 0x9, 0x8}, /* CL = 8 */ |
| 456 | {0x9, 0x7, 0xA, 0x7}, /* CL = 9 */ |
| 457 | {0x9, 0x7, 0xB, 0x6}, /* CL = 10 */ |
| 458 | } |
| 459 | }; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 460 | |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 461 | /* [DDR freq][0x26F & 1][pagemod] */ |
| 462 | const static u8 ddr2_x252_tab[2][2][2] = { |
| 463 | { /* DDR2 667 */ |
| 464 | {12, 16}, |
| 465 | {14, 18} |
| 466 | }, |
| 467 | { /* DDR2 800 */ |
| 468 | {14, 18}, |
| 469 | {16, 20} |
| 470 | } |
| 471 | }; |
| 472 | |
| 473 | const static u8 ddr3_x252_tab[3][2][2] = { |
| 474 | { /* DDR3 800 */ |
| 475 | {16, 20}, |
| 476 | {18, 22} |
| 477 | }, |
| 478 | { /* DDR3 1067 */ |
| 479 | {20, 26}, |
| 480 | {26, 26} |
| 481 | }, |
| 482 | { /* DDR3 1333 */ |
| 483 | {20, 30}, |
| 484 | {22, 32}, |
| 485 | } |
| 486 | }; |
| 487 | |
| 488 | if (s->spd_type == DDR2) { |
| 489 | ta1 = 6; |
| 490 | ta2 = 6; |
| 491 | ta3 = 5; |
| 492 | ta4 = 8; |
| 493 | } else { |
| 494 | int ddr3_idx = s->selected_timings.mem_clk - MEM_CLOCK_800MHz; |
| 495 | int cas_idx = s->selected_timings.CAS - 5; |
| 496 | ta1 = ddr3_turnaround_tab[ddr3_idx][cas_idx][0]; |
| 497 | ta2 = ddr3_turnaround_tab[ddr3_idx][cas_idx][1]; |
| 498 | ta3 = ddr3_turnaround_tab[ddr3_idx][cas_idx][2]; |
| 499 | ta4 = ddr3_turnaround_tab[ddr3_idx][cas_idx][3]; |
| 500 | } |
| 501 | |
| 502 | if (s->spd_type == DDR2) |
| 503 | twl = s->selected_timings.CAS - 1; |
| 504 | else /* DDR3 */ |
| 505 | twl = s->selected_timings.mem_clk - MEM_CLOCK_800MHz + 5; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 506 | |
| 507 | FOR_EACH_POPULATED_DIMM(s->dimms, i) { |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 508 | if (s->dimms[i].n_banks == N_BANKS_8) { |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 509 | trpmod = 1; |
| 510 | bankmod = 0; |
| 511 | } |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 512 | if (s->dimms[i].page_size == 2048) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 513 | pagemod = 1; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 514 | } |
| 515 | |
| 516 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 517 | MCHBAR8_OR(0x400*i + 0x26f, 0x3); |
| 518 | MCHBAR8_AND_OR(0x400*i + 0x228, ~0x7, 0x2); |
| 519 | /* tWL - x ?? */ |
| 520 | MCHBAR8_AND_OR(0x400*i + 0x240, ~0xf0, 0 << 4); |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 521 | MCHBAR8_AND_OR(0x400*i + 0x240, ~0xf, adjusted_cas); |
| 522 | MCHBAR16_AND_OR(0x400*i + 0x265, ~0x3f00, |
| 523 | (adjusted_cas + 9) << 8); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 524 | |
| 525 | reg16 = (s->selected_timings.tRAS << 11) | |
| 526 | ((twl + 4 + s->selected_timings.tWR) << 6) | |
| 527 | ((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1; |
| 528 | MCHBAR16(0x400*i + 0x250) = reg16; |
| 529 | |
| 530 | reg32 = (bankmod << 21) | |
| 531 | (s->selected_timings.tRRD << 17) | |
| 532 | (s->selected_timings.tRP << 13) | |
| 533 | ((s->selected_timings.tRP + trpmod) << 9) | |
| 534 | s->selected_timings.tRFC; |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 535 | if (bankmod == 0) { |
| 536 | reg8 = (MCHBAR8(0x400*i + 0x26f) >> 1) & 1; |
| 537 | if (s->spd_type == DDR2) |
| 538 | reg32 |= ddr2_x252_tab[s->selected_timings.mem_clk |
| 539 | - MEM_CLOCK_667MHz][reg8][pagemod] |
| 540 | << 22; |
| 541 | else |
| 542 | reg32 |= ddr3_x252_tab[s->selected_timings.mem_clk |
| 543 | - MEM_CLOCK_800MHz][reg8][pagemod] |
| 544 | << 22; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 545 | } |
| 546 | MCHBAR32(0x400*i + 0x252) = reg32; |
| 547 | |
| 548 | MCHBAR16(0x400*i + 0x256) = (s->selected_timings.tRCD << 12) | |
| 549 | (0x4 << 8) | (ta2 << 4) | ta4; |
| 550 | |
| 551 | MCHBAR32(0x400*i + 0x258) = (s->selected_timings.tRCD << 17) | |
| 552 | ((twl + 4 + s->selected_timings.tWTR) << 12) | |
| 553 | (ta3 << 8) | (4 << 4) | ta1; |
| 554 | |
| 555 | MCHBAR16(0x400*i + 0x25b) = ((s->selected_timings.tRP + trpmod) << 9) | |
| 556 | s->selected_timings.tRFC; |
| 557 | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 558 | MCHBAR16_AND_OR(0x400*i + 0x260, ~0x3fe, |
| 559 | (s->spd_type == DDR2 ? 100 : 256) << 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 560 | MCHBAR8(0x400*i + 0x264) = 0xff; |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 561 | MCHBAR8_AND_OR(0x400*i + 0x25d, ~0x3f, |
| 562 | s->selected_timings.tRAS); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 563 | MCHBAR16(0x400*i + 0x244) = 0x2310; |
| 564 | |
| 565 | switch (s->selected_timings.mem_clk) { |
| 566 | case MEM_CLOCK_667MHz: |
| 567 | reg8 = 0; |
| 568 | break; |
| 569 | default: |
| 570 | reg8 = 1; |
| 571 | break; |
| 572 | } |
| 573 | |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 574 | MCHBAR8_AND_OR(0x400*i + 0x246, ~0x1f, (reg8 << 2) | 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 575 | |
| 576 | fsb = fsb2ps[s->selected_timings.fsb_clk]; |
| 577 | ddr = ddr2ps[s->selected_timings.mem_clk]; |
Arthur Heymans | 66a0f55 | 2017-05-15 10:33:01 +0200 | [diff] [blame] | 578 | reg32 = (u32)((s->selected_timings.CAS + 7 + reg8) * ddr); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 579 | reg32 = (u32)((reg32 / fsb) << 8); |
| 580 | reg32 |= 0x0e000000; |
| 581 | if ((fsb2mhz(s->selected_timings.fsb_clk) / |
| 582 | ddr2mhz(s->selected_timings.mem_clk)) > 2) { |
| 583 | reg32 |= 1 << 24; |
| 584 | } |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 585 | MCHBAR32_AND_OR(0x400*i + 0x248, ~0x0f001f00, reg32); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 586 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 587 | if (twl > 2) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 588 | flag1 = 1; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 589 | |
| 590 | if (s->selected_timings.mem_clk >= MEM_CLOCK_800MHz) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 591 | flag2 = 1; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 592 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 593 | reg16 = (u8)(twl - 1 - flag1 - flag2); |
| 594 | reg16 |= reg16 << 4; |
| 595 | if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 596 | if (reg16) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 597 | reg16--; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 598 | } |
| 599 | reg16 |= flag1 << 8; |
| 600 | reg16 |= flag2 << 9; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 601 | MCHBAR16_AND_OR(0x400*i + 0x24d, ~0x1ff, reg16); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 602 | MCHBAR16(0x400*i + 0x25e) = 0x15a5; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 603 | MCHBAR32_AND(0x400*i + 0x265, ~0x1f); |
| 604 | MCHBAR32_AND_OR(0x400*i + 0x269, ~0x000fffff, |
| 605 | (0x3f << 14) | lut1[s->selected_timings.mem_clk]); |
| 606 | MCHBAR8_OR(0x400*i + 0x274, 1); |
| 607 | MCHBAR8_AND(0x400*i + 0x24c, ~0x3); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 608 | |
| 609 | reg16 = 0; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 610 | if (s->spd_type == DDR2) { |
| 611 | switch (s->selected_timings.mem_clk) { |
| 612 | default: |
| 613 | case MEM_CLOCK_667MHz: |
| 614 | reg16 = 0x99; |
| 615 | break; |
| 616 | case MEM_CLOCK_800MHz: |
| 617 | if (s->selected_timings.CAS == 5) |
| 618 | reg16 = 0x19a; |
| 619 | else if (s->selected_timings.CAS == 6) |
| 620 | reg16 = 0x9a; |
| 621 | break; |
| 622 | } |
| 623 | } else { /* DDR3 */ |
| 624 | switch (s->selected_timings.mem_clk) { |
| 625 | default: |
| 626 | case MEM_CLOCK_800MHz: |
| 627 | case MEM_CLOCK_1066MHz: |
| 628 | reg16 = 1; |
| 629 | break; |
| 630 | case MEM_CLOCK_1333MHz: |
| 631 | reg16 = 2; |
| 632 | break; |
| 633 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 634 | } |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 635 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 636 | reg16 &= 0x7; |
| 637 | reg16 += twl + 9; |
| 638 | reg16 <<= 10; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 639 | MCHBAR16_AND_OR(0x400*i + 0x24d, ~0x7c00, reg16); |
| 640 | MCHBAR8_AND_OR(0x400*i + 0x267, ~0x3f, 0x13); |
| 641 | MCHBAR8_AND_OR(0x400*i + 0x268, ~0xff, 0x4a); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 642 | |
| 643 | reg16 = (MCHBAR16(0x400*i + 0x269) & 0xc000) >> 2; |
| 644 | reg16 += 2 << 12; |
| 645 | reg16 |= (0x15 << 6) | 0x1f; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 646 | MCHBAR16_AND_OR(0x400*i + 0x26d, ~0x7fff, reg16); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 647 | |
| 648 | reg32 = (1 << 25) | (6 << 27); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 649 | MCHBAR32_AND_OR(0x400*i + 0x269, ~0xfa300000, reg32); |
| 650 | MCHBAR8_AND(0x400*i + 0x271, ~0x80); |
| 651 | MCHBAR8_AND(0x400*i + 0x274, ~0x6); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 652 | } // END EACH POPULATED CHANNEL |
| 653 | |
| 654 | reg16 = 0x1f << 5; |
| 655 | reg16 |= 0xe << 10; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 656 | MCHBAR16_AND_OR(0x125, ~0x3fe0, reg16); |
| 657 | MCHBAR16_AND_OR(0x127, ~0x7ff, 0x540); |
| 658 | MCHBAR8_OR(0x129, 0x1f); |
| 659 | MCHBAR8_OR(0x12c, 0xa0); |
| 660 | MCHBAR32_AND_OR(0x241, ~0x1ffff, 0x11); |
| 661 | MCHBAR32_AND_OR(0x641, ~0x1ffff, 0x11); |
| 662 | MCHBAR8_AND(0x246, ~0x10); |
| 663 | MCHBAR8_AND(0x646, ~0x10); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 664 | MCHBAR32(0x120) = (2 << 29) | (1 << 28) | (1 << 23) | 0xd7f5f; |
| 665 | reg8 = (u8)((MCHBAR32(0x252) & 0x1e000) >> 13); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 666 | MCHBAR8_AND_OR(0x12d, ~0xf0, reg8 << 4); |
Arthur Heymans | eee4f6b | 2017-01-03 00:49:45 +0100 | [diff] [blame] | 667 | reg8 = (u8)((MCHBAR32(0x258) & 0x1e0000) >> 17); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 668 | MCHBAR8_AND_OR(0x12d, ~0xf, reg8); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 669 | MCHBAR8(0x12f) = 0x4c; |
| 670 | reg32 = (1 << 31) | (0x80 << 14) | (1 << 13) | (0xa << 9); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 671 | if (s->spd_type == DDR3) { |
| 672 | MCHBAR8(0x114) = 0x42; |
| 673 | reg16 = (512 - MAX(5, s->selected_timings.tRFC + 10000 |
| 674 | / ddr2ps[s->selected_timings.mem_clk])) |
| 675 | / 2; |
| 676 | reg16 &= 0x1ff; |
| 677 | reg32 = (reg16 << 22) | (0x80 << 14) | (0xa << 9); |
| 678 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 679 | MCHBAR32_AND_OR(0x6c0, ~0xffffff00, reg32); |
| 680 | MCHBAR8_AND_OR(0x6c4, ~0x7, 0x2); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 681 | } |
| 682 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 683 | static void program_dll(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 684 | { |
Arthur Heymans | 37689fa | 2017-05-17 14:07:10 +0200 | [diff] [blame] | 685 | u8 i, j, r, reg8, clk, async = 0; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 686 | u16 reg16 = 0; |
| 687 | u32 reg32 = 0; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 688 | |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 689 | const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04, |
| 690 | 0x08, 0x10 }; |
| 691 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 692 | MCHBAR16_AND_OR(0x180, ~0x7e06, 0xc04); |
| 693 | MCHBAR16_AND_OR(0x182, ~0x3ff, 0xc8); |
| 694 | MCHBAR16_AND_OR(0x18a, ~0x1f1f, 0x0f0f); |
| 695 | MCHBAR16_AND_OR(0x1b4, ~0x8020, 0x100); |
| 696 | MCHBAR8_AND_OR(0x194, ~0x77, 0x33); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 697 | switch (s->selected_timings.mem_clk) { |
| 698 | default: |
| 699 | case MEM_CLOCK_667MHz: |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 700 | case MEM_CLOCK_1333MHz: |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 701 | reg16 = (0xa << 9) | 0xa; |
| 702 | break; |
| 703 | case MEM_CLOCK_800MHz: |
| 704 | reg16 = (0x9 << 9) | 0x9; |
| 705 | break; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 706 | case MEM_CLOCK_1066MHz: |
| 707 | reg16 = (0x7 << 9) | 0x7; |
| 708 | break; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 709 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 710 | MCHBAR16_AND_OR(0x19c, ~0x1e0f, reg16); |
| 711 | MCHBAR16_AND_OR(0x19c, ~0x2030, 0x2010); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 712 | udelay(1); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 713 | MCHBAR16_AND(0x198, ~0x100); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 714 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 715 | MCHBAR16_AND_OR(0x1c8, ~0x1f, 0xd); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 716 | |
| 717 | udelay(1); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 718 | MCHBAR8_AND(0x190, ~1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 719 | udelay(1); // 533ns |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 720 | MCHBAR32_AND(0x198, ~0x11554000); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 721 | udelay(1); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 722 | MCHBAR32_AND(0x198, ~0x1455); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 723 | udelay(1); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 724 | MCHBAR8_AND(0x583, ~0x1c); |
| 725 | MCHBAR8_AND(0x983, ~0x1c); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 726 | udelay(1); // 533ns |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 727 | MCHBAR8_AND(0x583, ~0x3); |
| 728 | MCHBAR8_AND(0x983, ~0x3); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 729 | udelay(1); // 533ns |
| 730 | |
| 731 | // ME related |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 732 | MCHBAR32_AND_OR(0x1a0, ~0x7ffffff, |
| 733 | s->spd_type == DDR2 ? 0x551803 : 0x555801); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 734 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 735 | MCHBAR16_AND(0x1b4, ~0x800); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 736 | if (s->spd_type == DDR2) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 737 | MCHBAR8_OR(0x1a8, 0xf0); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 738 | } else { /* DDR3 */ |
| 739 | reg8 = 0x9; /* 0x9 << 4 ?? */ |
| 740 | if (s->dimms[0].ranks == 2) |
| 741 | reg8 &= ~0x80; |
| 742 | if (s->dimms[3].ranks == 2) |
| 743 | reg8 &= ~0x10; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 744 | MCHBAR8_AND_OR(0x1a8, ~0xf0, reg8); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 745 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 746 | |
| 747 | FOR_EACH_CHANNEL(i) { |
| 748 | reg16 = 0; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 749 | if ((s->spd_type == DDR3) && (i == 0)) |
| 750 | reg16 = (0x3 << 12); |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 751 | MCHBAR16_AND_OR(0x400*i + 0x59c, ~0x3000, reg16); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 752 | |
| 753 | reg32 = 0; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 754 | FOR_EACH_RANK_IN_CHANNEL(r) { |
| 755 | if (!RANK_IS_POPULATED(s->dimms, i, r)) |
| 756 | reg32 |= 0x111 << r; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 757 | } |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 758 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 759 | MCHBAR32_AND_OR(0x400*i + 0x59c, ~0xfff, reg32); |
| 760 | MCHBAR8_AND(0x400*i + 0x594, ~1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 761 | |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 762 | if (s->spd_type == DDR2) { |
| 763 | if (!CHANNEL_IS_POPULATED(s->dimms, i)) { |
| 764 | printk(BIOS_DEBUG, |
| 765 | "No dimms in channel %d\n", i); |
| 766 | reg8 = 0x3f; |
| 767 | } else if (ONLY_DIMMA_IS_POPULATED(s->dimms, i)) { |
| 768 | printk(BIOS_DEBUG, |
| 769 | "DimmA populated only in channel %d\n", |
| 770 | i); |
| 771 | reg8 = 0x38; |
| 772 | } else if (ONLY_DIMMB_IS_POPULATED(s->dimms, i)) { |
| 773 | printk(BIOS_DEBUG, |
| 774 | "DimmB populated only in channel %d\n", |
| 775 | i); |
| 776 | reg8 = 0x7; |
| 777 | } else if (BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { |
| 778 | printk(BIOS_DEBUG, |
| 779 | "Both dimms populated in channel %d\n", |
| 780 | i); |
| 781 | reg8 = 0; |
| 782 | } else { |
| 783 | die("Unhandled case\n"); |
| 784 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 785 | MCHBAR32_AND_OR(0x400*i + 0x5a0, ~0x3f000000, |
| 786 | (u32)(reg8 << 24)); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 787 | |
| 788 | } else { /* DDR3 */ |
| 789 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 790 | MCHBAR8_AND(0x400 * i + 0x5a0 + 3, |
| 791 | ~rank2clken[r + i * 4]); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 792 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 793 | } |
| 794 | |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 795 | //reg8 = 0x00; // FIXME don't switch on all clocks anyway |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 796 | } // END EACH CHANNEL |
| 797 | |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 798 | if (s->spd_type == DDR2) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 799 | MCHBAR8_OR(0x1a8, 1); |
| 800 | MCHBAR8_AND(0x1a8, ~0x4); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 801 | } else { /* DDR3 */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 802 | MCHBAR8_AND(0x1a8, ~1); |
| 803 | MCHBAR8_OR(0x1a8, 0x4); |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 804 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 805 | |
| 806 | // Update DLL timing |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 807 | MCHBAR8_AND(0x1a4, ~0x80); |
| 808 | MCHBAR8_OR(0x1a4, 0x40); |
| 809 | MCHBAR16_AND_OR(0x5f0, ~0x400, 0x400); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 810 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 811 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 812 | MCHBAR16_AND_OR(0x400*i + 0x5f0, ~0x3fc, 0x3fc); |
| 813 | MCHBAR32_AND(0x400*i + 0x5fc, ~0xcccccccc); |
| 814 | MCHBAR8_AND_OR(0x400*i + 0x5d9, ~0xf0, |
| 815 | s->spd_type == DDR2 ? 0x70 : 0x60); |
| 816 | MCHBAR16_AND_OR(0x400*i + 0x590, ~0xffff, |
| 817 | s->spd_type == DDR2 ? 0x5555 : 0xa955); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 818 | } |
| 819 | |
| 820 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Jonathan Neuschäfer | 7be74db | 2018-02-12 12:00:40 +0100 | [diff] [blame] | 821 | const struct dll_setting *setting; |
| 822 | |
Elyes HAOUAS | 0ce41f1 | 2018-11-13 10:03:31 +0100 | [diff] [blame] | 823 | switch (s->selected_timings.mem_clk) { |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 824 | default: /* Should not happen */ |
| 825 | case MEM_CLOCK_667MHz: |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 826 | setting = default_ddr2_667_ctrl; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 827 | break; |
| 828 | case MEM_CLOCK_800MHz: |
| 829 | if (s->spd_type == DDR2) |
| 830 | setting = default_ddr2_800_ctrl; |
| 831 | else |
| 832 | setting = default_ddr3_800_ctrl[s->nmode - 1]; |
| 833 | break; |
| 834 | case MEM_CLOCK_1066MHz: |
| 835 | setting = default_ddr3_1067_ctrl[s->nmode - 1]; |
| 836 | break; |
| 837 | case MEM_CLOCK_1333MHz: |
| 838 | setting = default_ddr3_1333_ctrl[s->nmode - 1]; |
| 839 | break; |
| 840 | } |
Jonathan Neuschäfer | 7be74db | 2018-02-12 12:00:40 +0100 | [diff] [blame] | 841 | |
| 842 | clkset0(i, &setting[CLKSET0]); |
| 843 | clkset1(i, &setting[CLKSET1]); |
| 844 | ctrlset0(i, &setting[CTRL0]); |
| 845 | ctrlset1(i, &setting[CTRL1]); |
| 846 | ctrlset2(i, &setting[CTRL2]); |
| 847 | ctrlset3(i, &setting[CTRL3]); |
| 848 | cmdset(i, &setting[CMD]); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 849 | } |
| 850 | |
| 851 | // XXX if not async mode |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 852 | MCHBAR16_AND(0x180, ~0x8200); |
| 853 | MCHBAR8_OR(0x180, 0x4); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 854 | j = 0; |
| 855 | for (i = 0; i < 16; i++) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 856 | MCHBAR8_AND_OR(0x1c8, ~0x1f, i); |
| 857 | MCHBAR8_OR(0x180, 0x10); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 858 | while (MCHBAR8(0x180) & 0x10) |
| 859 | ; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 860 | if (MCHBAR32(0x184) == 0xffffffff) { |
| 861 | j++; |
| 862 | if (j >= 2) |
| 863 | break; |
| 864 | |
| 865 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { |
| 866 | j = 2; |
| 867 | break; |
| 868 | } |
| 869 | } else { |
| 870 | j = 0; |
| 871 | } |
| 872 | } |
| 873 | if (i == 1 || ((i == 0) && s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { |
| 874 | j = 0; |
| 875 | i++; |
| 876 | for (; i < 16; i++) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 877 | MCHBAR8_AND_OR(0x1c8, ~0x1f, i); |
| 878 | MCHBAR8_OR(0x180, 0x4); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 879 | while (MCHBAR8(0x180) & 0x10) |
| 880 | ; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 881 | if (MCHBAR32(0x184) == 0) { |
| 882 | i++; |
| 883 | break; |
| 884 | } |
| 885 | } |
| 886 | for (; i < 16; i++) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 887 | MCHBAR8_AND_OR(0x1c8, ~0x1f, i); |
| 888 | MCHBAR8_OR(0x180, 0x10); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 889 | while (MCHBAR8(0x180) & 0x10) |
| 890 | ; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 891 | if (MCHBAR32(0x184) == 0xffffffff) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 892 | j++; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 893 | if (j >= 2) |
| 894 | break; |
| 895 | } else { |
| 896 | j = 0; |
| 897 | } |
| 898 | } |
| 899 | if (j < 2) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 900 | MCHBAR8_AND(0x1c8, ~0x1f); |
| 901 | MCHBAR8_OR(0x180, 0x10); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 902 | while (MCHBAR8(0x180) & 0x10) |
| 903 | ; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 904 | j = 2; |
| 905 | } |
| 906 | } |
| 907 | |
| 908 | if (j < 2) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 909 | MCHBAR8_AND(0x1c8, ~0x1f); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 910 | async = 1; |
| 911 | } |
| 912 | |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 913 | switch (s->selected_timings.mem_clk) { |
| 914 | case MEM_CLOCK_667MHz: |
| 915 | clk = 0x1a; |
| 916 | if (async != 1) { |
| 917 | if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) |
| 918 | clk = 0x10; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 919 | } |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 920 | break; |
| 921 | case MEM_CLOCK_800MHz: |
| 922 | case MEM_CLOCK_1066MHz: |
| 923 | if (async != 1) |
| 924 | clk = 0x10; |
| 925 | else |
| 926 | clk = 0x1a; |
| 927 | break; |
| 928 | case MEM_CLOCK_1333MHz: |
| 929 | clk = 0x18; |
| 930 | break; |
| 931 | default: |
| 932 | clk = 0x1a; |
| 933 | break; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 934 | } |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 935 | |
| 936 | if (async != 1) |
| 937 | reg8 = MCHBAR8(0x188) & 0x1e; |
| 938 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 939 | MCHBAR8_AND(0x180, ~0x80); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 940 | |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 941 | if ((s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) |
| 942 | || (s->spd_type == DDR2 && s->selected_timings.fsb_clk == FSB_CLOCK_800MHz |
| 943 | && s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { |
Arthur Heymans | 24798a1 | 2017-08-13 16:02:09 +0200 | [diff] [blame] | 944 | i = MCHBAR8(0x1c8) & 0xf; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 945 | if (s->spd_type == DDR2) |
| 946 | i = (i + 10) % 14; |
| 947 | else /* DDR3 */ |
| 948 | i = (i + 3) % 12; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 949 | MCHBAR8_AND_OR(0x1c8, ~0x1f, i); |
| 950 | MCHBAR8_OR(0x180, 0x10); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 951 | while (MCHBAR8(0x180) & 0x10) |
| 952 | ; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 953 | } |
| 954 | |
| 955 | reg8 = MCHBAR8(0x188) & ~1; |
| 956 | MCHBAR8(0x188) = reg8; |
| 957 | reg8 &= ~0x3e; |
| 958 | reg8 |= clk; |
| 959 | MCHBAR8(0x188) = reg8; |
| 960 | reg8 |= 1; |
| 961 | MCHBAR8(0x188) = reg8; |
| 962 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 963 | if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 964 | MCHBAR8_OR(0x18c, 1); |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 965 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 966 | |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 967 | static void select_default_dq_dqs_settings(struct sysinfo *s) |
| 968 | { |
| 969 | int ch, lane; |
| 970 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 971 | FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(s->dimms, ch, lane) { |
| 972 | switch (s->selected_timings.mem_clk) { |
| 973 | case MEM_CLOCK_667MHz: |
| 974 | memcpy(s->dqs_settings[ch], |
| 975 | default_ddr2_667_dqs, |
| 976 | sizeof(s->dqs_settings[ch])); |
| 977 | memcpy(s->dq_settings[ch], |
| 978 | default_ddr2_667_dq, |
| 979 | sizeof(s->dq_settings[ch])); |
| 980 | s->rt_dqs[ch][lane].tap = 7; |
| 981 | s->rt_dqs[ch][lane].pi = 2; |
| 982 | break; |
| 983 | case MEM_CLOCK_800MHz: |
| 984 | if (s->spd_type == DDR2) { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 985 | memcpy(s->dqs_settings[ch], |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 986 | default_ddr2_800_dqs, |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 987 | sizeof(s->dqs_settings[ch])); |
| 988 | memcpy(s->dq_settings[ch], |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 989 | default_ddr2_800_dq, |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 990 | sizeof(s->dq_settings[ch])); |
| 991 | s->rt_dqs[ch][lane].tap = 7; |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 992 | s->rt_dqs[ch][lane].pi = 0; |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 993 | } else { /* DDR3 */ |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 994 | memcpy(s->dqs_settings[ch], |
| 995 | default_ddr3_800_dqs[s->nmode - 1], |
| 996 | sizeof(s->dqs_settings[ch])); |
| 997 | memcpy(s->dq_settings[ch], |
| 998 | default_ddr3_800_dq[s->nmode - 1], |
| 999 | sizeof(s->dq_settings[ch])); |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 1000 | s->rt_dqs[ch][lane].tap = 6; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 1001 | s->rt_dqs[ch][lane].pi = 3; |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 1002 | } |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 1003 | break; |
| 1004 | case MEM_CLOCK_1066MHz: |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 1005 | memcpy(s->dqs_settings[ch], |
| 1006 | default_ddr3_1067_dqs[s->nmode - 1], |
| 1007 | sizeof(s->dqs_settings[ch])); |
| 1008 | memcpy(s->dq_settings[ch], |
| 1009 | default_ddr3_1067_dq[s->nmode - 1], |
| 1010 | sizeof(s->dq_settings[ch])); |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 1011 | s->rt_dqs[ch][lane].tap = 5; |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 1012 | s->rt_dqs[ch][lane].pi = 3; |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 1013 | break; |
| 1014 | case MEM_CLOCK_1333MHz: |
Arthur Heymans | 638240e | 2017-12-25 18:14:46 +0100 | [diff] [blame] | 1015 | memcpy(s->dqs_settings[ch], |
| 1016 | default_ddr3_1333_dqs[s->nmode - 1], |
| 1017 | sizeof(s->dqs_settings[ch])); |
| 1018 | memcpy(s->dq_settings[ch], |
| 1019 | default_ddr3_1333_dq[s->nmode - 1], |
| 1020 | sizeof(s->dq_settings[ch])); |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 1021 | s->rt_dqs[ch][lane].tap = 7; |
| 1022 | s->rt_dqs[ch][lane].pi = 0; |
| 1023 | break; |
| 1024 | default: /* not supported */ |
| 1025 | break; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1026 | } |
| 1027 | } |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 1028 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1029 | |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 1030 | /* |
| 1031 | * It looks like only the RT DQS register for the first rank |
| 1032 | * is used for all ranks. Just set all the 'unused' RT DQS registers |
| 1033 | * to the same as rank 0, out of precaution. |
| 1034 | */ |
| 1035 | static void set_all_dq_dqs_dll_settings(struct sysinfo *s) |
| 1036 | { |
| 1037 | // Program DQ/DQS dll settings |
| 1038 | int ch, lane, rank; |
| 1039 | |
| 1040 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 1041 | FOR_EACH_BYTELANE(lane) { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 1042 | FOR_EACH_RANK_IN_CHANNEL(rank) { |
| 1043 | rt_set_dqs(ch, lane, rank, |
| 1044 | &s->rt_dqs[ch][lane]); |
| 1045 | } |
| 1046 | dqsset(ch, lane, &s->dqs_settings[ch][lane]); |
| 1047 | dqset(ch, lane, &s->dq_settings[ch][lane]); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1048 | } |
| 1049 | } |
| 1050 | } |
| 1051 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1052 | static void prog_rcomp(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1053 | { |
Arthur Heymans | 0d1c9b0 | 2017-05-15 10:40:42 +0200 | [diff] [blame] | 1054 | u8 i, j, k, reg8; |
| 1055 | const u32 ddr2_x32a[8] = { 0x04040404, 0x06050505, 0x09090807, 0x0D0C0B0A, |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1056 | 0x04040404, 0x08070605, 0x0C0B0A09, 0x100F0E0D }; |
Arthur Heymans | 0d1c9b0 | 2017-05-15 10:40:42 +0200 | [diff] [blame] | 1057 | const u16 ddr2_x378[6] = { 0, 0xAAAA, 0x7777, 0x7777, 0x7777, 0x7777 }; |
| 1058 | const u32 ddr2_x382[6] = { 0, 0x02020202, 0x02020202, 0x02020202, 0x04030303, 0x04030303 }; |
| 1059 | const u32 ddr2_x386[6] = { 0, 0x03020202, 0x03020202, 0x03020202, 0x05040404, 0x05040404 }; |
| 1060 | const u32 ddr2_x38a[6] = { 0, 0x04040303, 0x04040303, 0x04040303, 0x07070605, 0x07070605 }; |
| 1061 | const u32 ddr2_x38e[6] = { 0, 0x06060505, 0x06060505, 0x06060505, 0x09090808, 0x09090808 }; |
| 1062 | const u32 ddr2_x392[6] = { 0, 0x02020202, 0x02020202, 0x02020202, 0x03030202, 0x03030202 }; |
| 1063 | const u32 ddr2_x396[6] = { 0, 0x03030202, 0x03030202, 0x03030202, 0x05040303, 0x05040303 }; |
| 1064 | const u32 ddr2_x39a[6] = { 0, 0x04040403, 0x04040403, 0x04040403, 0x07070605, 0x07070605 }; |
| 1065 | const u32 ddr2_x39e[6] = { 0, 0x06060505, 0x06060505, 0x06060505, 0x08080808, 0x08080808 }; |
| 1066 | |
| 1067 | const u32 ddr3_x32a[8] = {0x06060606, 0x06060606, 0x0b090807, 0x12110f0d, |
| 1068 | 0x06060606, 0x08070606, 0x0d0b0a09, 0x16161511}; |
| 1069 | const u16 ddr3_x378[6] = {0, 0xbbbb, 0x6666, 0x6666, 0x6666, 0x6666}; |
| 1070 | const u32 ddr3_x382[6] = {0, 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434}; |
| 1071 | const u32 ddr3_x386[6] = {0, 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434}; |
| 1072 | const u32 ddr3_x38a[6] = {0, 0x06060605, 0x07060504, 0x07060504, 0x34343434, 0x34343434}; |
| 1073 | const u32 ddr3_x38e[6] = {0, 0x09080707, 0x09090808, 0x09090808, 0x34343434, 0x34343434}; |
| 1074 | const u32 ddr3_x392[6] = {0, 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434}; |
| 1075 | const u32 ddr3_x396[6] = {0, 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434}; |
| 1076 | const u32 ddr3_x39a[6] = {0, 0x07060606, 0x08070605, 0x08070605, 0x34343434, 0x34343434}; |
| 1077 | const u32 ddr3_x39e[6] = {0, 0x09090807, 0x0b0b0a09, 0x0b0b0a09, 0x34343434, 0x34343434}; |
| 1078 | |
| 1079 | const u16 *x378; |
| 1080 | const u32 *x32a, *x382, *x386, *x38a, *x38e; |
| 1081 | const u32 *x392, *x396, *x39a, *x39e; |
| 1082 | |
| 1083 | const u16 addr[6] = { 0x31c, 0x374, 0x3a2, 0x3d0, 0x3fe, 0x42c }; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1084 | u8 bit[6] = { 0, 0, 1, 1, 0, 0 }; |
| 1085 | |
Arthur Heymans | 0d1c9b0 | 2017-05-15 10:40:42 +0200 | [diff] [blame] | 1086 | if (s->spd_type == DDR2) { |
| 1087 | x32a = ddr2_x32a; |
| 1088 | x378 = ddr2_x378; |
| 1089 | x382 = ddr2_x382; |
| 1090 | x386 = ddr2_x386; |
| 1091 | x38a = ddr2_x38a; |
| 1092 | x38e = ddr2_x38e; |
| 1093 | x392 = ddr2_x392; |
| 1094 | x396 = ddr2_x396; |
| 1095 | x39a = ddr2_x39a; |
| 1096 | x39e = ddr2_x39e; |
| 1097 | } else { /* DDR3 */ |
| 1098 | x32a = ddr3_x32a; |
| 1099 | x378 = ddr3_x378; |
| 1100 | x382 = ddr3_x382; |
| 1101 | x386 = ddr3_x386; |
| 1102 | x38a = ddr3_x38a; |
| 1103 | x38e = ddr3_x38e; |
| 1104 | x392 = ddr3_x392; |
| 1105 | x396 = ddr3_x396; |
| 1106 | x39a = ddr3_x39a; |
| 1107 | x39e = ddr3_x39e; |
| 1108 | } |
| 1109 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1110 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
| 1111 | for (j = 0; j < 6; j++) { |
| 1112 | if (j == 0) { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 1113 | MCHBAR32_AND_OR(0x400*i + addr[j], ~0xff000, |
| 1114 | 0xaa000); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1115 | MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff, |
| 1116 | 0x6666); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1117 | for (k = 0; k < 8; k++) { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 1118 | MCHBAR32_AND_OR(0x400*i + addr[j] + |
| 1119 | 0xe + (k << 2), |
| 1120 | ~0x3f3f3f3f, x32a[k]); |
| 1121 | MCHBAR32_AND_OR(0x400*i + addr[j] + |
| 1122 | 0x2e + (k << 2), |
| 1123 | ~0x3f3f3f3f, x32a[k]); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1124 | } |
| 1125 | } else { |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 1126 | MCHBAR16_AND_OR(0x400*i + addr[j], |
| 1127 | ~0xf000, 0xa000); |
| 1128 | MCHBAR16_AND_OR(0x400*i + addr[j] + 4, |
| 1129 | ~0xffff, x378[j]); |
| 1130 | MCHBAR32_AND_OR(0x400*i + addr[j] + 0xe, |
| 1131 | ~0x3f3f3f3f, x382[j]); |
| 1132 | MCHBAR32_AND_OR(0x400*i + addr[j] + 0x12, |
| 1133 | ~0x3f3f3f3f, x386[j]); |
| 1134 | MCHBAR32_AND_OR(0x400*i + addr[j] + 0x16, |
| 1135 | ~0x3f3f3f3f, x38a[j]); |
| 1136 | MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1a, |
| 1137 | ~0x3f3f3f3f, x38e[j]); |
| 1138 | MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1e, |
| 1139 | ~0x3f3f3f3f, x392[j]); |
| 1140 | MCHBAR32_AND_OR(0x400*i + addr[j] + 0x22, |
| 1141 | ~0x3f3f3f3f, x396[j]); |
| 1142 | MCHBAR32_AND_OR(0x400*i + addr[j] + 0x26, |
| 1143 | ~0x3f3f3f3f, x39a[j]); |
| 1144 | MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a, |
| 1145 | ~0x3f3f3f3f, x39e[j]); |
Arthur Heymans | 0d1c9b0 | 2017-05-15 10:40:42 +0200 | [diff] [blame] | 1146 | } |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 1147 | if (s->spd_type == DDR3 && |
| 1148 | BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { |
| 1149 | MCHBAR16_AND_OR(0x378 + 0x400 * i, |
| 1150 | ~0xffff, 0xcccc); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1151 | } |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 1152 | MCHBAR8_AND_OR(0x400*i + addr[j], ~1, bit[j]); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1153 | } |
Arthur Heymans | 0d1c9b0 | 2017-05-15 10:40:42 +0200 | [diff] [blame] | 1154 | reg8 = (s->spd_type == DDR2) ? 0x12 : 0x36; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1155 | MCHBAR8_AND_OR(0x400*i + 0x45a, ~0x3f, reg8); |
| 1156 | MCHBAR8_AND_OR(0x400*i + 0x45e, ~0x3f, reg8); |
| 1157 | MCHBAR8_AND_OR(0x400*i + 0x462, ~0x3f, reg8); |
| 1158 | MCHBAR8_AND_OR(0x400*i + 0x466, ~0x3f, reg8); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1159 | } // END EACH POPULATED CHANNEL |
| 1160 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1161 | MCHBAR32_AND_OR(0x134, ~0x63c00, 0x63c00); |
| 1162 | MCHBAR16_AND_OR(0x174, ~0x63ff, 0x63ff); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1163 | MCHBAR16(0x178) = 0x0135; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1164 | MCHBAR32_AND_OR(0x130, ~0x7bdffe0, 0x7a9ffa0); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1165 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1166 | if (!CHANNEL_IS_POPULATED(s->dimms, 0)) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1167 | MCHBAR32_AND(0x130, ~(1 << 27)); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1168 | if (!CHANNEL_IS_POPULATED(s->dimms, 1)) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1169 | MCHBAR32_AND(0x130, ~(1 << 28)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1170 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1171 | MCHBAR8_OR(0x130, 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1172 | } |
| 1173 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1174 | static void program_odt(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1175 | { |
| 1176 | u8 i; |
Arthur Heymans | e6cc21e | 2017-05-15 10:43:20 +0200 | [diff] [blame] | 1177 | static u16 ddr2_odt[16][2] = { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1178 | { 0x0000, 0x0000 }, // NC_NC |
| 1179 | { 0x0000, 0x0001 }, // x8SS_NC |
| 1180 | { 0x0000, 0x0011 }, // x8DS_NC |
| 1181 | { 0x0000, 0x0001 }, // x16SS_NC |
| 1182 | { 0x0004, 0x0000 }, // NC_x8SS |
| 1183 | { 0x0101, 0x0404 }, // x8SS_x8SS |
| 1184 | { 0x0101, 0x4444 }, // x8DS_x8SS |
| 1185 | { 0x0101, 0x0404 }, // x16SS_x8SS |
| 1186 | { 0x0044, 0x0000 }, // NC_x8DS |
| 1187 | { 0x1111, 0x0404 }, // x8SS_x8DS |
| 1188 | { 0x1111, 0x4444 }, // x8DS_x8DS |
| 1189 | { 0x1111, 0x0404 }, // x16SS_x8DS |
| 1190 | { 0x0004, 0x0000 }, // NC_x16SS |
| 1191 | { 0x0101, 0x0404 }, // x8SS_x16SS |
| 1192 | { 0x0101, 0x4444 }, // x8DS_x16SS |
| 1193 | { 0x0101, 0x0404 }, // x16SS_x16SS |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1194 | }; |
| 1195 | |
Arthur Heymans | e6cc21e | 2017-05-15 10:43:20 +0200 | [diff] [blame] | 1196 | static const u16 ddr3_odt[16][2] = { |
| 1197 | { 0x0000, 0x0000 }, // NC_NC |
| 1198 | { 0x0000, 0x0001 }, // x8SS_NC |
| 1199 | { 0x0000, 0x0021 }, // x8DS_NC |
| 1200 | { 0x0000, 0x0001 }, // x16SS_NC |
| 1201 | { 0x0004, 0x0000 }, // NC_x8SS |
| 1202 | { 0x0105, 0x0405 }, // x8SS_x8SS |
| 1203 | { 0x0105, 0x4465 }, // x8DS_x8SS |
| 1204 | { 0x0105, 0x0405 }, // x16SS_x8SS |
| 1205 | { 0x0084, 0x0000 }, // NC_x8DS |
| 1206 | { 0x1195, 0x0405 }, // x8SS_x8DS |
| 1207 | { 0x1195, 0x4465 }, // x8DS_x8DS |
| 1208 | { 0x1195, 0x0405 }, // x16SS_x8DS |
| 1209 | { 0x0004, 0x0000 }, // NC_x16SS |
| 1210 | { 0x0105, 0x0405 }, // x8SS_x16SS |
| 1211 | { 0x0105, 0x4465 }, // x8DS_x16SS |
| 1212 | { 0x0105, 0x0405 }, // x16SS_x16SS |
| 1213 | }; |
| 1214 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1215 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Arthur Heymans | e6cc21e | 2017-05-15 10:43:20 +0200 | [diff] [blame] | 1216 | if (s->spd_type == DDR2) { |
| 1217 | MCHBAR16(0x400 * i + 0x298) = |
| 1218 | ddr2_odt[s->dimm_config[i]][1]; |
| 1219 | MCHBAR16(0x400 * i + 0x294) = |
| 1220 | ddr2_odt[s->dimm_config[i]][0]; |
| 1221 | } else { |
| 1222 | MCHBAR16(0x400 * i + 0x298) = |
| 1223 | ddr3_odt[s->dimm_config[i]][1]; |
| 1224 | MCHBAR16(0x400 * i + 0x294) = |
| 1225 | ddr3_odt[s->dimm_config[i]][0]; |
| 1226 | } |
| 1227 | u16 reg16 = MCHBAR16(0x400*i + 0x29c); |
| 1228 | reg16 &= ~0xfff; |
| 1229 | reg16 |= (s->spd_type == DDR2 ? 0x66b : 0x778); |
| 1230 | MCHBAR16(0x400*i + 0x29c) = reg16; |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 1231 | MCHBAR32_AND_OR(0x400*i + 0x260, ~0x70e3c00, 0x3063c00); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1232 | } |
| 1233 | } |
| 1234 | |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1235 | static void pre_jedec_memory_map(void) |
| 1236 | { |
| 1237 | /* |
| 1238 | * Configure the memory mapping in stacked mode (channel 1 being mapped |
| 1239 | * above channel 0) and with 128M per rank. |
| 1240 | * This simplifies dram trainings a lot since those need a test address. |
| 1241 | * |
| 1242 | * +-------------+ => 0 |
| 1243 | * | ch 0, rank 0| |
| 1244 | * +-------------+ => 0x8000000 (128M) |
| 1245 | * | ch 0, rank 1| |
| 1246 | * +-------------+ => 0x10000000 (256M) |
| 1247 | * | ch 0, rank 2| |
| 1248 | * +-------------+ => 0x18000000 (384M) |
| 1249 | * | ch 0, rank 3| |
| 1250 | * +-------------+ => 0x20000000 (512M) |
| 1251 | * | ch 1, rank 0| |
| 1252 | * +-------------+ => 0x28000000 (640M) |
| 1253 | * | ch 1, rank 1| |
| 1254 | * +-------------+ => 0x30000000 (768M) |
| 1255 | * | ch 1, rank 2| |
| 1256 | * +-------------+ => 0x38000000 (896M) |
| 1257 | * | ch 1, rank 3| |
| 1258 | * +-------------+ |
| 1259 | * |
| 1260 | * After all trainings are done this is set to the real values specified |
| 1261 | * by the SPD. |
| 1262 | */ |
| 1263 | /* Set rank 0-3 populated */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1264 | MCHBAR32_AND_OR(C0CKECTRL, ~1, 0xf00000); |
| 1265 | MCHBAR32_AND_OR(C1CKECTRL, ~1, 0xf00000); |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1266 | /* Set size of each rank to 128M */ |
| 1267 | MCHBAR16(C0DRA01) = 0x0101; |
| 1268 | MCHBAR16(C0DRA23) = 0x0101; |
| 1269 | MCHBAR16(C1DRA01) = 0x0101; |
| 1270 | MCHBAR16(C1DRA23) = 0x0101; |
| 1271 | MCHBAR16(C0DRB0) = 0x0002; |
| 1272 | MCHBAR16(C0DRB1) = 0x0004; |
| 1273 | MCHBAR16(C0DRB2) = 0x0006; |
| 1274 | MCHBAR16(C0DRB3) = 0x0008; |
| 1275 | MCHBAR16(C1DRB0) = 0x0002; |
| 1276 | MCHBAR16(C1DRB1) = 0x0004; |
| 1277 | MCHBAR16(C1DRB2) = 0x0006; |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1278 | /* In stacked mode the last present rank on ch1 needs to have its |
| 1279 | size doubled in c1drbx */ |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1280 | MCHBAR16(C1DRB3) = 0x0010; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1281 | MCHBAR8_OR(0x111, STACKED_MEM); |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1282 | MCHBAR32(0x104) = 0; |
| 1283 | MCHBAR16(0x102) = 0x400; |
| 1284 | MCHBAR8(0x110) = (2 << 5) | (3 << 3); |
| 1285 | MCHBAR16(0x10e) = 0; |
| 1286 | MCHBAR32(0x108) = 0; |
| 1287 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOLUD, 0x4000); |
| 1288 | /* TOM(64M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */ |
| 1289 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOM, 0x10); |
| 1290 | /* TOUUD(1M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */ |
| 1291 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOUUD, 0x0400); |
| 1292 | pci_write_config32(PCI_DEV(0, 0, 0), D0F0_GBSM, 0x40000000); |
| 1293 | pci_write_config32(PCI_DEV(0, 0, 0), D0F0_BGSM, 0x40000000); |
| 1294 | pci_write_config32(PCI_DEV(0, 0, 0), D0F0_TSEG, 0x40000000); |
| 1295 | } |
| 1296 | |
| 1297 | u32 test_address(int channel, int rank) |
| 1298 | { |
| 1299 | ASSERT(channel <= 1 && rank < 4); |
| 1300 | return channel * 512 * MiB + rank * 128 * MiB; |
| 1301 | } |
| 1302 | |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1303 | |
| 1304 | /* DDR3 Rank1 Address mirror |
| 1305 | * swap the following pins: |
| 1306 | * A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ |
| 1307 | static u32 mirror_shift_bit(const u32 data, u8 bit) |
| 1308 | { |
| 1309 | u32 temp0 = data, temp1 = data; |
| 1310 | temp0 &= 1 << bit; |
| 1311 | temp0 <<= 1; |
| 1312 | temp1 &= 1 << (bit + 1); |
| 1313 | temp1 >>= 1; |
| 1314 | return (data & ~(3 << bit)) | temp0 | temp1; |
| 1315 | } |
| 1316 | |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 1317 | void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1318 | { |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1319 | u32 addr = test_address(ch, r); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1320 | volatile u32 rubbish; |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1321 | u8 data8 = cmd; |
| 1322 | u32 data32; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1323 | |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1324 | if (s->spd_type == DDR3 && (r & 1) |
| 1325 | && s->dimms[ch * 2 + (r >> 1)].mirrored) { |
| 1326 | data8 = (u8)mirror_shift_bit(data8, 4); |
| 1327 | } |
| 1328 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1329 | MCHBAR8_AND_OR(0x271, ~0x3e, data8); |
| 1330 | MCHBAR8_AND_OR(0x671, ~0x3e, data8); |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1331 | data32 = val; |
| 1332 | if (s->spd_type == DDR3 && (r & 1) |
| 1333 | && s->dimms[ch * 2 + (r >> 1)].mirrored) { |
| 1334 | data32 = mirror_shift_bit(data32, 3); |
| 1335 | data32 = mirror_shift_bit(data32, 5); |
| 1336 | data32 = mirror_shift_bit(data32, 7); |
| 1337 | } |
| 1338 | data32 <<= 3; |
| 1339 | |
| 1340 | rubbish = read32((void *)((data32 | addr))); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1341 | udelay(10); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1342 | MCHBAR8_AND_OR(0x271, ~0x3e, NORMALOP_CMD); |
| 1343 | MCHBAR8_AND_OR(0x671, ~0x3e, NORMALOP_CMD); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1344 | } |
| 1345 | |
| 1346 | static void jedec_ddr2(struct sysinfo *s) |
| 1347 | { |
| 1348 | u8 i; |
| 1349 | u16 mrsval, ch, r, v; |
| 1350 | |
| 1351 | u8 odt[16][4] = { |
| 1352 | {0x00, 0x00, 0x00, 0x00}, |
| 1353 | {0x01, 0x00, 0x00, 0x00}, |
| 1354 | {0x01, 0x01, 0x00, 0x00}, |
| 1355 | {0x01, 0x00, 0x00, 0x00}, |
| 1356 | {0x00, 0x00, 0x01, 0x00}, |
| 1357 | {0x11, 0x00, 0x11, 0x00}, |
| 1358 | {0x11, 0x11, 0x11, 0x00}, |
| 1359 | {0x11, 0x00, 0x11, 0x00}, |
| 1360 | {0x00, 0x00, 0x01, 0x01}, |
| 1361 | {0x11, 0x00, 0x11, 0x11}, |
| 1362 | {0x11, 0x11, 0x11, 0x11}, |
| 1363 | {0x11, 0x00, 0x11, 0x11}, |
| 1364 | {0x00, 0x00, 0x01, 0x00}, |
| 1365 | {0x11, 0x00, 0x11, 0x00}, |
| 1366 | {0x11, 0x11, 0x11, 0x00}, |
| 1367 | {0x11, 0x00, 0x11, 0x00} |
| 1368 | }; |
| 1369 | |
| 1370 | u16 jedec[12][2] = { |
| 1371 | {NOP_CMD, 0x0}, |
| 1372 | {PRECHARGE_CMD, 0x0}, |
| 1373 | {EMRS2_CMD, 0x0}, |
| 1374 | {EMRS3_CMD, 0x0}, |
| 1375 | {EMRS1_CMD, 0x0}, |
| 1376 | {MRS_CMD, 0x100}, // DLL Reset |
| 1377 | {PRECHARGE_CMD, 0x0}, |
| 1378 | {CBR_CMD, 0x0}, |
| 1379 | {CBR_CMD, 0x0}, |
| 1380 | {MRS_CMD, 0x0}, // DLL out of reset |
| 1381 | {EMRS1_CMD, 0x380}, // OCD calib default |
| 1382 | {EMRS1_CMD, 0x0} |
| 1383 | }; |
| 1384 | |
| 1385 | mrsval = (s->selected_timings.CAS << 4) | ((s->selected_timings.tWR - 1) << 9) | 0xb; |
| 1386 | |
| 1387 | printk(BIOS_DEBUG, "MRS...\n"); |
| 1388 | |
| 1389 | udelay(200); |
| 1390 | |
| 1391 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
| 1392 | printk(BIOS_DEBUG, "CH%d: Found Rank %d\n", ch, r); |
| 1393 | for (i = 0; i < 12; i++) { |
| 1394 | v = jedec[i][1]; |
| 1395 | switch (jedec[i][0]) { |
| 1396 | case EMRS1_CMD: |
| 1397 | v |= (odt[s->dimm_config[ch]][r] << 2); |
| 1398 | break; |
| 1399 | case MRS_CMD: |
| 1400 | v |= mrsval; |
| 1401 | break; |
| 1402 | default: |
| 1403 | break; |
| 1404 | } |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1405 | send_jedec_cmd(s, r, ch, jedec[i][0], v); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1406 | udelay(1); |
Arthur Heymans | cfa2eaa | 2017-03-20 16:32:07 +0100 | [diff] [blame] | 1407 | printk(RAM_SPEW, "Jedec step %d\n", i); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1408 | } |
| 1409 | } |
| 1410 | printk(BIOS_DEBUG, "MRS done\n"); |
| 1411 | } |
| 1412 | |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 1413 | static void jedec_ddr3(struct sysinfo *s) |
| 1414 | { |
| 1415 | int ch, r, dimmconfig, cmd, ddr3_freq; |
| 1416 | |
| 1417 | u8 ddr3_emrs2_rtt_wr_config[16][4] = { /* [config][Rank] */ |
| 1418 | {0, 0, 0, 0}, /* NC_NC */ |
| 1419 | {0, 0, 0, 0}, /* x8ss_NC */ |
| 1420 | {0, 0, 0, 0}, /* x8ds_NC */ |
| 1421 | {0, 0, 0, 0}, /* x16ss_NC */ |
| 1422 | {0, 0, 0, 0}, /* NC_x8ss */ |
| 1423 | {2, 0, 2, 0}, /* x8ss_x8ss */ |
| 1424 | {2, 2, 2, 0}, /* x8ds_x8ss */ |
| 1425 | {2, 0, 2, 0}, /* x16ss_x8ss */ |
| 1426 | {0, 0, 0, 0}, /* NC_x8ss */ |
| 1427 | {2, 0, 2, 2}, /* x8ss_x8ds */ |
| 1428 | {2, 2, 2, 2}, /* x8ds_x8ds */ |
| 1429 | {2, 0, 2, 2}, /* x16ss_x8ds */ |
| 1430 | {0, 0, 0, 0}, /* NC_x16ss */ |
| 1431 | {2, 0, 2, 0}, /* x8ss_x16ss */ |
| 1432 | {2, 2, 2, 0}, /* x8ds_x16ss */ |
| 1433 | {2, 0, 2, 0}, /* x16ss_x16ss */ |
| 1434 | }; |
| 1435 | |
| 1436 | printk(BIOS_DEBUG, "MRS...\n"); |
| 1437 | |
| 1438 | ddr3_freq = s->selected_timings.mem_clk - MEM_CLOCK_800MHz; |
| 1439 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
| 1440 | printk(BIOS_DEBUG, "CH%d: Found Rank %d\n", ch, r); |
| 1441 | send_jedec_cmd(s, r, ch, NOP_CMD, 0); |
| 1442 | udelay(200); |
| 1443 | dimmconfig = s->dimm_config[ch]; |
| 1444 | cmd = ddr3_freq << 3; /* actually twl - 5 which is same */ |
| 1445 | cmd |= ddr3_emrs2_rtt_wr_config[dimmconfig][r] << 9; |
| 1446 | send_jedec_cmd(s, r, ch, EMRS2_CMD, cmd); |
| 1447 | send_jedec_cmd(s, r, ch, EMRS3_CMD, 0); |
| 1448 | cmd = ddr3_emrs1_rtt_nom_config[dimmconfig][r] << 2; |
| 1449 | /* Hardcode output drive strength to 34 Ohm / RZQ/7 (why??) */ |
| 1450 | cmd |= (1 << 1); |
| 1451 | send_jedec_cmd(s, r, ch, EMRS1_CMD, cmd); |
| 1452 | /* Burst type interleaved, burst length 8, Reset DLL, |
| 1453 | * Precharge PD: DLL on */ |
| 1454 | send_jedec_cmd(s, r, ch, MRS_CMD, (1 << 3) | (1 << 8) |
| 1455 | | (1 << 12) | ((s->selected_timings.CAS - 4) << 4) |
| 1456 | | ((s->selected_timings.tWR - 4) << 9)); |
| 1457 | send_jedec_cmd(s, r, ch, ZQCAL_CMD, (1 << 10)); |
| 1458 | } |
| 1459 | printk(BIOS_DEBUG, "MRS done\n"); |
| 1460 | } |
| 1461 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1462 | static void sdram_recover_receive_enable(const struct sysinfo *s) |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1463 | { |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1464 | u32 reg32; |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1465 | u16 medium, coarse_offset; |
| 1466 | u8 pi_tap; |
| 1467 | int lane, channel; |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1468 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1469 | FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) { |
| 1470 | medium = 0; |
| 1471 | coarse_offset = 0; |
| 1472 | reg32 = MCHBAR32(0x400 * channel + 0x248); |
| 1473 | reg32 &= ~0xf0000; |
| 1474 | reg32 |= s->rcven_t[channel].min_common_coarse << 16; |
| 1475 | MCHBAR32(0x400 * channel + 0x248) = reg32; |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1476 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 1477 | FOR_EACH_BYTELANE(lane) { |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1478 | medium |= s->rcven_t[channel].medium[lane] |
| 1479 | << (lane * 2); |
| 1480 | coarse_offset |= |
| 1481 | (s->rcven_t[channel].coarse_offset[lane] & 0x3) |
| 1482 | << (lane * 2); |
| 1483 | |
| 1484 | pi_tap = MCHBAR8(0x400 * channel + 0x560 + lane * 4); |
| 1485 | pi_tap &= ~0x7f; |
| 1486 | pi_tap |= s->rcven_t[channel].tap[lane]; |
| 1487 | pi_tap |= s->rcven_t[channel].pi[lane] << 4; |
| 1488 | MCHBAR8(0x400 * channel + 0x560 + lane * 4) = pi_tap; |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1489 | } |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1490 | MCHBAR16(0x400 * channel + 0x58c) = medium; |
| 1491 | MCHBAR16(0x400 * channel + 0x5fa) = coarse_offset; |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1492 | } |
| 1493 | } |
| 1494 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1495 | static void sdram_program_receive_enable(struct sysinfo *s, int fast_boot) |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1496 | { |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1497 | /* Program Receive Enable Timings */ |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1498 | if (fast_boot) |
| 1499 | sdram_recover_receive_enable(s); |
| 1500 | else |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 1501 | rcven(s); |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1502 | } |
| 1503 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1504 | static void set_dradrb(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1505 | { |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1506 | u8 map, i, ch, r, rankpop0, rankpop1, lastrank_ch1; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1507 | u32 c0dra = 0; |
| 1508 | u32 c1dra = 0; |
| 1509 | u32 c0drb = 0; |
| 1510 | u32 c1drb = 0; |
| 1511 | u32 dra; |
| 1512 | u32 dra0; |
| 1513 | u32 dra1; |
| 1514 | u16 totalmemorymb; |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1515 | u32 dual_channel_size, single_channel_size, single_channel_offset; |
| 1516 | u32 size_ch0, size_ch1, size_me; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1517 | u8 dratab[2][2][2][4] = { |
| 1518 | { |
| 1519 | { |
| 1520 | {0xff, 0xff, 0xff, 0xff}, |
| 1521 | {0xff, 0x00, 0x02, 0xff} |
| 1522 | }, |
| 1523 | { |
| 1524 | {0xff, 0x01, 0xff, 0xff}, |
| 1525 | {0xff, 0x03, 0xff, 0xff} |
| 1526 | } |
| 1527 | }, |
| 1528 | { |
| 1529 | { |
| 1530 | {0xff, 0xff, 0xff, 0xff}, |
| 1531 | {0xff, 0x04, 0x06, 0x08} |
| 1532 | }, |
| 1533 | { |
| 1534 | {0xff, 0xff, 0xff, 0xff}, |
| 1535 | {0x05, 0x07, 0x09, 0xff} |
| 1536 | } |
| 1537 | } |
| 1538 | }; |
| 1539 | |
| 1540 | u8 drbtab[10] = {0x04, 0x02, 0x08, 0x04, 0x08, 0x04, 0x10, 0x08, 0x20, 0x10}; |
| 1541 | |
| 1542 | // DRA |
| 1543 | rankpop0 = 0; |
| 1544 | rankpop1 = 0; |
| 1545 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1546 | if (s->dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED |
| 1547 | && (r) < s->dimms[ch<<1].ranks) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1548 | i = ch << 1; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1549 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1550 | i = (ch << 1) + 1; |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 1551 | |
| 1552 | dra = dratab[s->dimms[i].n_banks] |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1553 | [s->dimms[i].width] |
| 1554 | [s->dimms[i].cols-9] |
| 1555 | [s->dimms[i].rows-12]; |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 1556 | if (s->dimms[i].n_banks == N_BANKS_8) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1557 | dra |= 0x80; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1558 | if (ch == 0) { |
| 1559 | c0dra |= dra << (r*8); |
| 1560 | rankpop0 |= 1 << r; |
| 1561 | } else { |
| 1562 | c1dra |= dra << (r*8); |
| 1563 | rankpop1 |= 1 << r; |
| 1564 | } |
| 1565 | } |
| 1566 | MCHBAR32(0x208) = c0dra; |
| 1567 | MCHBAR32(0x608) = c1dra; |
| 1568 | |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1569 | MCHBAR8_AND_OR(0x262, ~0xf0, (rankpop0 << 4) & 0xf0); |
| 1570 | MCHBAR8_AND_OR(0x662, ~0xf0, (rankpop1 << 4) & 0xf0); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1571 | |
Arthur Heymans | b4a7804 | 2017-12-25 20:17:41 +0100 | [diff] [blame] | 1572 | if (s->spd_type == DDR3) { |
| 1573 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
| 1574 | /* ZQCAL enable */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1575 | MCHBAR32_OR(0x269 + 0x400 * ch, 1 << 26); |
Arthur Heymans | b4a7804 | 2017-12-25 20:17:41 +0100 | [diff] [blame] | 1576 | } |
| 1577 | } |
| 1578 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1579 | if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || |
| 1580 | ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1581 | MCHBAR8_OR(0x260, 1); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1582 | if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) || |
| 1583 | ONLY_DIMMB_IS_POPULATED(s->dimms, 1)) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1584 | MCHBAR8_OR(0x660, 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1585 | |
| 1586 | // DRB |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1587 | lastrank_ch1 = 0; |
Arthur Heymans | dfce932 | 2017-12-16 19:48:00 +0100 | [diff] [blame] | 1588 | FOR_EACH_RANK(ch, r) { |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1589 | if (ch == 0) { |
Arthur Heymans | dfce932 | 2017-12-16 19:48:00 +0100 | [diff] [blame] | 1590 | if (RANK_IS_POPULATED(s->dimms, ch, r)) { |
| 1591 | dra0 = (c0dra >> (8*r)) & 0x7f; |
| 1592 | c0drb = (u16)(c0drb + drbtab[dra0]); |
| 1593 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1594 | MCHBAR16(0x200 + 2*r) = c0drb; |
| 1595 | } else { |
Arthur Heymans | dfce932 | 2017-12-16 19:48:00 +0100 | [diff] [blame] | 1596 | if (RANK_IS_POPULATED(s->dimms, ch, r)) { |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1597 | lastrank_ch1 = r; |
Arthur Heymans | dfce932 | 2017-12-16 19:48:00 +0100 | [diff] [blame] | 1598 | dra1 = (c1dra >> (8*r)) & 0x7f; |
| 1599 | c1drb = (u16)(c1drb + drbtab[dra1]); |
| 1600 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1601 | MCHBAR16(0x600 + 2*r) = c1drb; |
| 1602 | } |
| 1603 | } |
| 1604 | |
| 1605 | s->channel_capacity[0] = c0drb << 6; |
| 1606 | s->channel_capacity[1] = c1drb << 6; |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1607 | |
| 1608 | /* |
| 1609 | * In stacked mode the last present rank on ch1 needs to have its |
| 1610 | * size doubled in c1drbx. All subsequent ranks need the same setting |
| 1611 | * according to: "Intel 4 Series Chipset Family Datasheet" |
| 1612 | */ |
| 1613 | if (s->stacked_mode) { |
| 1614 | for (r = lastrank_ch1; r < 4; r++) |
| 1615 | MCHBAR16(0x600 + 2*r) = 2 * c1drb; |
| 1616 | } |
| 1617 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1618 | totalmemorymb = s->channel_capacity[0] + s->channel_capacity[1]; |
| 1619 | printk(BIOS_DEBUG, "Total memory: %d + %d = %dMiB\n", |
| 1620 | s->channel_capacity[0], s->channel_capacity[1], totalmemorymb); |
| 1621 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1622 | /* Populated channel sizes in MiB */ |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1623 | size_ch0 = s->channel_capacity[0]; |
| 1624 | size_ch1 = s->channel_capacity[1]; |
| 1625 | size_me = ME_UMA_SIZEMB; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1626 | |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1627 | if (s->stacked_mode) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1628 | MCHBAR8_OR(0x111, STACKED_MEM); |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1629 | } else { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1630 | MCHBAR8_AND(0x111, ~STACKED_MEM); |
| 1631 | MCHBAR8_OR(0x111, 1 << 4); |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1632 | } |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1633 | |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1634 | if (s->stacked_mode) { |
| 1635 | dual_channel_size = 0; |
| 1636 | } else if (size_me == 0) { |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1637 | dual_channel_size = MIN(size_ch0, size_ch1) * 2; |
| 1638 | } else { |
| 1639 | if (size_ch0 == 0) { |
| 1640 | /* ME needs ram on CH0 */ |
| 1641 | size_me = 0; |
| 1642 | /* TOTEST: bailout? */ |
| 1643 | } else { |
| 1644 | /* Set ME UMA size in MiB */ |
| 1645 | MCHBAR16(0x100) = size_me; |
| 1646 | /* Set ME UMA Present bit */ |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1647 | MCHBAR32_OR(0x111, 1); |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1648 | } |
| 1649 | dual_channel_size = MIN(size_ch0 - size_me, size_ch1) * 2; |
| 1650 | } |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1651 | |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1652 | MCHBAR16(0x104) = dual_channel_size; |
| 1653 | single_channel_size = size_ch0 + size_ch1 - dual_channel_size; |
| 1654 | MCHBAR16(0x102) = single_channel_size; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1655 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1656 | map = 0; |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1657 | if (size_ch0 == 0) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1658 | map = 0; |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1659 | else if (size_ch1 == 0) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1660 | map |= 0x20; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1661 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1662 | map |= 0x40; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1663 | |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1664 | if (dual_channel_size == 0) |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1665 | map |= 0x18; |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1666 | /* Enable flex mode, we hardcode this everywhere */ |
| 1667 | if (size_me == 0) { |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1668 | if (!(s->stacked_mode && size_ch0 != 0 && size_ch1 != 0)) { |
| 1669 | map |= 0x04; |
| 1670 | if (size_ch0 <= size_ch1) |
| 1671 | map |= 0x01; |
| 1672 | } |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1673 | } else { |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1674 | if (s->stacked_mode == 0 && size_ch0 - size_me < size_ch1) |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1675 | map |= 0x04; |
| 1676 | } |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1677 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1678 | MCHBAR8(0x110) = map; |
| 1679 | MCHBAR16(0x10e) = 0; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1680 | |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1681 | /* |
| 1682 | * "108h[15:0] Single Channel Offset for Ch0" |
| 1683 | * This is the 'limit' of the part on CH0 that cannot be matched |
| 1684 | * with memory on CH1. MCHBAR16(0x10a) is where the dual channel |
| 1685 | * memory on ch0s end and MCHBAR16(0x108) is the limit of the single |
| 1686 | * channel size on ch0. |
| 1687 | */ |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 1688 | if (s->stacked_mode && size_ch1 != 0) { |
| 1689 | single_channel_offset = 0; |
| 1690 | } else if (size_me == 0) { |
Arthur Heymans | 701da39 | 2017-12-16 22:56:19 +0100 | [diff] [blame] | 1691 | if (size_ch0 > size_ch1) |
| 1692 | single_channel_offset = dual_channel_size / 2 |
| 1693 | + single_channel_size; |
| 1694 | else |
| 1695 | single_channel_offset = dual_channel_size / 2; |
| 1696 | } else { |
| 1697 | if ((size_ch0 > size_ch1) && ((map & 0x7) == 4)) |
| 1698 | single_channel_offset = dual_channel_size / 2 |
| 1699 | + single_channel_size; |
| 1700 | else |
| 1701 | single_channel_offset = dual_channel_size / 2 |
| 1702 | + size_me; |
| 1703 | } |
| 1704 | |
| 1705 | MCHBAR16(0x108) = single_channel_offset; |
| 1706 | MCHBAR16(0x10a) = dual_channel_size / 2; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1707 | } |
| 1708 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1709 | static void configure_mmap(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1710 | { |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1711 | bool reclaim; |
| 1712 | u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud; |
| 1713 | u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit; |
Arthur Heymans | 16a70a4 | 2017-09-22 12:22:24 +0200 | [diff] [blame] | 1714 | u32 mmiostart, umasizem; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1715 | u16 ggc; |
Arthur Heymans | 27f94ee | 2016-06-18 21:08:58 +0200 | [diff] [blame] | 1716 | u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, |
| 1717 | 160, 224, 352 }; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1718 | u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; |
Arthur Heymans | 16a70a4 | 2017-09-22 12:22:24 +0200 | [diff] [blame] | 1719 | u8 reg8; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1720 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1721 | ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1722 | gfxsize = ggc2uma[(ggc & 0xf0) >> 4]; |
| 1723 | gttsize = ggc2gtt[(ggc & 0xf00) >> 8]; |
Arthur Heymans | d522db0 | 2018-08-06 15:50:54 +0200 | [diff] [blame] | 1724 | /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, |
| 1725 | which requires to have TSEG_BASE aligned to TSEG_SIZE. */ |
| 1726 | tsegsize = 2; |
Damien Zammit | 523e90f | 2016-09-05 02:32:40 +1000 | [diff] [blame] | 1727 | mmiosize = 0x800; // 2GB MMIO |
Arthur Heymans | 16a70a4 | 2017-09-22 12:22:24 +0200 | [diff] [blame] | 1728 | umasizem = gfxsize + gttsize + tsegsize; |
| 1729 | mmiostart = 0x1000 - mmiosize + umasizem; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1730 | tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB; |
Arthur Heymans | 16a70a4 | 2017-09-22 12:22:24 +0200 | [diff] [blame] | 1731 | tolud = MIN(mmiostart, tom); |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1732 | |
| 1733 | reclaim = false; |
| 1734 | if ((tom - tolud) > 0x40) |
| 1735 | reclaim = true; |
| 1736 | |
| 1737 | if (reclaim) { |
| 1738 | tolud = tolud & ~0x3f; |
| 1739 | tom = tom & ~0x3f; |
| 1740 | reclaimbase = MAX(0x1000, tom); |
| 1741 | reclaimlimit = reclaimbase + (MIN(0x1000, tom) - tolud) - 0x40; |
| 1742 | } |
| 1743 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1744 | touud = tom; |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1745 | if (reclaim) |
| 1746 | touud = reclaimlimit + 0x40; |
| 1747 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1748 | gfxbase = tolud - gfxsize; |
| 1749 | gttbase = gfxbase - gttsize; |
| 1750 | tsegbase = gttbase - tsegsize; |
| 1751 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1752 | pci_write_config16(PCI_DEV(0, 0, 0), 0xb0, tolud << 4); |
| 1753 | pci_write_config16(PCI_DEV(0, 0, 0), 0xa0, tom >> 6); |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1754 | if (reclaim) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1755 | pci_write_config16(PCI_DEV(0, 0, 0), 0x98, |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1756 | (u16)(reclaimbase >> 6)); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1757 | pci_write_config16(PCI_DEV(0, 0, 0), 0x9a, |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1758 | (u16)(reclaimlimit >> 6)); |
| 1759 | } |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1760 | pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud); |
| 1761 | pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20); |
| 1762 | pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20); |
Arthur Heymans | d522db0 | 2018-08-06 15:50:54 +0200 | [diff] [blame] | 1763 | /* Enable and set tseg size to 2M */ |
Arthur Heymans | 16a70a4 | 2017-09-22 12:22:24 +0200 | [diff] [blame] | 1764 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); |
| 1765 | reg8 &= ~0x7; |
Arthur Heymans | d522db0 | 2018-08-06 15:50:54 +0200 | [diff] [blame] | 1766 | reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */ |
Arthur Heymans | 16a70a4 | 2017-09-22 12:22:24 +0200 | [diff] [blame] | 1767 | pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1768 | pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1769 | } |
| 1770 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1771 | static void set_enhanced_mode(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1772 | { |
| 1773 | u8 ch, reg8; |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1774 | u32 reg32; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1775 | |
| 1776 | MCHBAR32(0xfb0) = 0x1000d024; |
| 1777 | MCHBAR32(0xfb4) = 0xc842; |
| 1778 | MCHBAR32(0xfbc) = 0xf; |
| 1779 | MCHBAR32(0xfc4) = 0xfe22244; |
| 1780 | MCHBAR8(0x12f) = 0x5c; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1781 | MCHBAR8_OR(0xfb0, 1); |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 1782 | if (s->selected_timings.mem_clk <= MEM_CLOCK_800MHz) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1783 | MCHBAR8_OR(0x12f, 0x2); |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 1784 | else |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1785 | MCHBAR8_AND(0x12f, ~0x2); |
| 1786 | MCHBAR8_AND_OR(0x6c0, ~0xf0, 0xa0); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1787 | MCHBAR32(0xfa8) = 0x30d400; |
| 1788 | |
| 1789 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1790 | MCHBAR8_OR(0x400*ch + 0x26c, 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1791 | MCHBAR32(0x400*ch + 0x278) = 0x88141881; |
| 1792 | MCHBAR16(0x400*ch + 0x27c) = 0x0041; |
| 1793 | MCHBAR8(0x400*ch + 0x292) = 0xf2; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1794 | MCHBAR16_OR(0x400*ch + 0x272, 0x100); |
| 1795 | MCHBAR8_AND_OR(0x400*ch + 0x243, ~0x2, 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1796 | MCHBAR32(0x400*ch + 0x288) = 0x8040200; |
| 1797 | MCHBAR32(0x400*ch + 0x28c) = 0xff402010; |
| 1798 | MCHBAR32(0x400*ch + 0x290) = 0x4f2091c; |
| 1799 | } |
| 1800 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1801 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); |
| 1802 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | 1); |
Felix Held | 3a2f900 | 2018-07-29 18:51:22 +0200 | [diff] [blame] | 1803 | MCHBAR32_AND_OR(0xfa0, ~0x20002, 0x2 | (s->selected_timings.fsb_clk == |
| 1804 | FSB_CLOCK_1333MHz ? 0x20000 : 0)); |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1805 | reg32 = 0x219100c2; |
| 1806 | if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) { |
| 1807 | reg32 |= 1; |
| 1808 | if (s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) |
| 1809 | reg32 &= ~0x10000; |
| 1810 | } else if (s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz) { |
| 1811 | reg32 &= ~0x10000; |
| 1812 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1813 | MCHBAR32_AND_OR(0xfa4, ~0x219100c3, reg32); |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1814 | reg32 = 0x44a00; |
| 1815 | switch (s->selected_timings.fsb_clk) { |
| 1816 | case FSB_CLOCK_1333MHz: |
| 1817 | reg32 |= 0x62; |
| 1818 | break; |
| 1819 | case FSB_CLOCK_1066MHz: |
| 1820 | reg32 |= 0x5a; |
| 1821 | break; |
| 1822 | default: |
| 1823 | case FSB_CLOCK_800MHz: |
| 1824 | reg32 |= 0x53; |
| 1825 | break; |
| 1826 | } |
| 1827 | |
| 1828 | MCHBAR32(0x2c) = reg32; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1829 | MCHBAR32(0x30) = 0x1f5a86; |
| 1830 | MCHBAR32(0x34) = 0x1902810; |
| 1831 | MCHBAR32(0x38) = 0xf7000000; |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1832 | reg32 = 0x23014410; |
| 1833 | if (s->selected_timings.fsb_clk > FSB_CLOCK_800MHz) |
| 1834 | reg32 = (reg32 & ~0x2000000) | 0x44000000; |
| 1835 | MCHBAR32(0x3c) = reg32; |
| 1836 | reg32 = 0x8f038000; |
| 1837 | if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) |
| 1838 | reg32 &= ~0x4000000; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1839 | MCHBAR32_AND_OR(0x40, ~0x8f038000, reg32); |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1840 | reg32 = 0x00013001; |
| 1841 | if (s->selected_timings.fsb_clk < FSB_CLOCK_1333MHz) |
| 1842 | reg32 |= 0x20000; |
| 1843 | MCHBAR32(0x20) = reg32; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1844 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1845 | } |
| 1846 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 1847 | static void power_settings(struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1848 | { |
| 1849 | u32 reg1, reg2, reg3, reg4, clkgate, x592; |
| 1850 | u8 lane, ch; |
| 1851 | u8 twl = 0; |
| 1852 | u16 x264, x23c; |
| 1853 | |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 1854 | if (s->spd_type == DDR2) { |
| 1855 | twl = s->selected_timings.CAS - 1; |
| 1856 | x264 = 0x78; |
| 1857 | |
| 1858 | switch (s->selected_timings.mem_clk) { |
| 1859 | default: |
| 1860 | case MEM_CLOCK_667MHz: |
| 1861 | reg1 = 0x99; |
| 1862 | reg2 = 0x1048a9; |
| 1863 | clkgate = 0x230000; |
| 1864 | x23c = 0x7a89; |
| 1865 | break; |
| 1866 | case MEM_CLOCK_800MHz: |
| 1867 | if (s->selected_timings.CAS == 5) { |
| 1868 | reg1 = 0x19a; |
| 1869 | reg2 = 0x1048aa; |
| 1870 | } else { |
| 1871 | reg1 = 0x9a; |
| 1872 | reg2 = 0x2158aa; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1873 | x264 = 0x89; |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 1874 | } |
| 1875 | clkgate = 0x280000; |
| 1876 | x23c = 0x7b89; |
| 1877 | break; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1878 | } |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 1879 | reg3 = 0x232; |
| 1880 | reg4 = 0x2864; |
| 1881 | } else { /* DDR3 */ |
| 1882 | int ddr3_idx = s->selected_timings.mem_clk - MEM_CLOCK_800MHz; |
| 1883 | int cas_idx = s->selected_timings.CAS - 5; |
| 1884 | |
| 1885 | twl = s->selected_timings.mem_clk - MEM_CLOCK_800MHz + 5; |
| 1886 | reg1 = ddr3_c2_tab[s->nmode - 1][ddr3_idx][cas_idx][0]; |
| 1887 | reg2 = ddr3_c2_tab[s->nmode - 1][ddr3_idx][cas_idx][1]; |
| 1888 | reg3 = 0x764; |
| 1889 | reg4 = 0x78c8; |
| 1890 | x264 = ddr3_c2_x264[ddr3_idx][cas_idx]; |
| 1891 | x23c = ddr3_c2_x23c[ddr3_idx][cas_idx]; |
| 1892 | switch (s->selected_timings.mem_clk) { |
| 1893 | case MEM_CLOCK_800MHz: |
| 1894 | default: |
| 1895 | clkgate = 0x280000; |
| 1896 | break; |
| 1897 | case MEM_CLOCK_1066MHz: |
| 1898 | clkgate = 0x350000; |
| 1899 | break; |
| 1900 | case MEM_CLOCK_1333MHz: |
| 1901 | clkgate = 0xff0000; |
| 1902 | break; |
| 1903 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1904 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1905 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1906 | if (CHANNEL_IS_POPULATED(s->dimms, 0) && CHANNEL_IS_POPULATED(s->dimms, 1)) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1907 | MCHBAR32(0x14) = 0x0010461f; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1908 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1909 | MCHBAR32(0x14) = 0x0010691f; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1910 | MCHBAR32(0x18) = 0xdf6437f7; |
| 1911 | MCHBAR32(0x1c) = 0x0; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1912 | MCHBAR32_AND_OR(0x24, ~0xe0000000, 0x60000000); |
| 1913 | MCHBAR32_AND_OR(0x44, ~0x1fef0000, 0x6b0000); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1914 | MCHBAR16(0x115) = (u16) reg1; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1915 | MCHBAR32_AND_OR(0x117, ~0xffffff, reg2); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1916 | MCHBAR8(0x124) = 0x7; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1917 | // not sure if dummy reads are needed |
| 1918 | MCHBAR16_AND_OR(0x12a, 0, 0x80); |
| 1919 | MCHBAR8_AND_OR(0x12c, 0, 0xa0); |
| 1920 | MCHBAR16_AND(0x174, ~(1 << 15)); |
| 1921 | MCHBAR16_AND_OR(0x188, ~0x1f00, 0x1f00); |
| 1922 | MCHBAR8_AND(0x18c, ~0x8); |
| 1923 | MCHBAR8_OR(0x192, 1); |
| 1924 | MCHBAR8_OR(0x193, 0xf); |
| 1925 | MCHBAR16_AND_OR(0x1b4, ~0x480, 0x80); |
| 1926 | MCHBAR16_AND_OR(0x210, ~0x1fff, 0x3f); // | clockgatingiii |
| 1927 | // non-aligned access: possible bug? |
| 1928 | MCHBAR32_AND_OR(0x6d1, ~0xff03ff, 0x100 | clkgate); |
| 1929 | MCHBAR8_AND_OR(0x212, ~0x7f, 0x7f); |
| 1930 | MCHBAR32_AND_OR(0x2c0, ~0xffff0, 0xcc5f0); |
| 1931 | MCHBAR8_AND_OR(0x2c4, ~0x70, 0x70); |
| 1932 | // non-aligned access: possible bug? |
| 1933 | MCHBAR32_AND_OR(0x2d1, ~0xffffff, 0xff2831); // | clockgatingi |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1934 | MCHBAR32(0x2d4) = 0x40453600; |
| 1935 | MCHBAR32(0x300) = 0xc0b0a08; |
| 1936 | MCHBAR32(0x304) = 0x6040201; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1937 | MCHBAR32_AND_OR(0x30c, ~0x43c0f, 0x41405); |
Arthur Heymans | 7345a17 | 2018-05-26 15:08:06 +0200 | [diff] [blame] | 1938 | MCHBAR16(0x610) = reg3; |
| 1939 | MCHBAR16(0x612) = reg4; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1940 | MCHBAR32_AND_OR(0x62c, ~0xc000000, 0x4000000); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1941 | MCHBAR32(0xae4) = 0; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1942 | MCHBAR32_AND_OR(0xc00, ~0xf0000, 0x10000); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1943 | MCHBAR32(0xf00) = 0x393a3b3c; |
| 1944 | MCHBAR32(0xf04) = 0x3d3e3f40; |
| 1945 | MCHBAR32(0xf08) = 0x393a3b3c; |
| 1946 | MCHBAR32(0xf0c) = 0x3d3e3f40; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1947 | MCHBAR32_AND(0xf18, ~0xfff00001); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1948 | MCHBAR32(0xf48) = 0xfff0ffe0; |
| 1949 | MCHBAR32(0xf4c) = 0xffc0ff00; |
| 1950 | MCHBAR32(0xf50) = 0xfc00f000; |
| 1951 | MCHBAR32(0xf54) = 0xc0008000; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1952 | MCHBAR32_AND_OR(0xf6c, ~0xffff0000, 0xffff0000); |
| 1953 | MCHBAR32_AND(0xfac, ~0x80000000); |
| 1954 | MCHBAR32_AND(0xfb8, ~0xff000000); |
| 1955 | MCHBAR32_AND_OR(0xfbc, ~0x7f800, 0xf000); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1956 | MCHBAR32(0x1104) = 0x3003232; |
| 1957 | MCHBAR32(0x1108) = 0x74; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1958 | if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1959 | MCHBAR32(0x110c) = 0xaa; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1960 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1961 | MCHBAR32(0x110c) = 0x100; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1962 | MCHBAR32(0x1110) = 0x10810350 & ~0x78; |
| 1963 | MCHBAR32(0x1114) = 0; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1964 | x592 = 0xff; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1965 | if (pci_read_config8(PCI_DEV(0, 0, 0), 0x8) < 3) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1966 | x592 = ~0x4; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1967 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1968 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
| 1969 | MCHBAR8(0x400*ch + 0x239) = twl + 15; |
| 1970 | MCHBAR16(0x400*ch + 0x23c) = x23c; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1971 | MCHBAR32_AND_OR(0x400*ch + 0x248, ~0x706033, 0x406033); |
| 1972 | MCHBAR32_AND_OR(0x400*ch + 0x260, ~(1 << 16), 1 << 16); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1973 | MCHBAR8(0x400*ch + 0x264) = x264; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1974 | MCHBAR8_AND_OR(0x400*ch + 0x592, ~0x3f, 0x3c & x592); |
| 1975 | MCHBAR8_AND_OR(0x400*ch + 0x593, ~0x1f, 0x1e); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1976 | } |
| 1977 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1978 | for (lane = 0; lane < 8; lane++) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1979 | MCHBAR8_AND(0x561 + (lane << 2), ~(1 << 3)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1980 | } |
| 1981 | |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 1982 | static void software_ddr3_reset(struct sysinfo *s) |
| 1983 | { |
| 1984 | printk(BIOS_DEBUG, "Software initiated DDR3 reset.\n"); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1985 | MCHBAR8_OR(0x1a8, 0x02); |
| 1986 | MCHBAR8_AND(0x5da, ~0x80); |
| 1987 | MCHBAR8_AND(0x1a8, ~0x02); |
| 1988 | MCHBAR8_AND_OR(0x5da, ~0x03, 1); |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 1989 | udelay(200); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1990 | MCHBAR8_AND(0x1a8, ~0x02); |
| 1991 | MCHBAR8_OR(0x5da, 0x80); |
| 1992 | MCHBAR8_AND(0x5da, ~0x80); |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 1993 | udelay(500); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 1994 | MCHBAR8_OR(0x5da, 0x03); |
| 1995 | MCHBAR8_AND(0x5da, ~0x03); |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 1996 | /* After write leveling the dram needs to be reset and reinitialised */ |
| 1997 | jedec_ddr3(s); |
| 1998 | } |
| 1999 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2000 | void do_raminit(struct sysinfo *s, int fast_boot) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2001 | { |
| 2002 | u8 ch; |
| 2003 | u8 r, bank; |
| 2004 | u32 reg32; |
| 2005 | |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2006 | if (s->boot_path != BOOT_PATH_WARM_RESET) { |
| 2007 | // Clear self refresh |
| 2008 | MCHBAR32(PMSTS_MCHBAR) = MCHBAR32(PMSTS_MCHBAR) |
| 2009 | | PMSTS_BOTH_SELFREFRESH; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2010 | |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2011 | // Clear host clk gate reg |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2012 | MCHBAR32_OR(0x1c, 0xffffffff); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2013 | |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 2014 | // Select type |
| 2015 | if (s->spd_type == DDR2) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2016 | MCHBAR8_AND(0x1a8, ~0x4); |
Arthur Heymans | 840c27e | 2017-05-15 10:21:37 +0200 | [diff] [blame] | 2017 | else |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2018 | MCHBAR8_OR(0x1a8, 0x4); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2019 | |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2020 | // Set freq |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2021 | MCHBAR32_AND_OR(0xc00, ~0x70, |
| 2022 | (s->selected_timings.mem_clk << 4) | (1 << 10)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2023 | |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2024 | // Overwrite freq if chipset rejects it |
| 2025 | s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4; |
| 2026 | if (s->selected_timings.mem_clk > (s->max_fsb + 3)) |
| 2027 | die("Error: DDR is faster than FSB, halt\n"); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2028 | } |
| 2029 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2030 | // Program clock crossing |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2031 | program_crossclock(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2032 | printk(BIOS_DEBUG, "Done clk crossing\n"); |
| 2033 | |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2034 | if (s->boot_path != BOOT_PATH_WARM_RESET) { |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2035 | setioclk_dram(s); |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2036 | printk(BIOS_DEBUG, "Done I/O clk\n"); |
| 2037 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2038 | |
| 2039 | // Grant to launch |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2040 | launch_dram(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2041 | printk(BIOS_DEBUG, "Done launch\n"); |
| 2042 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2043 | // Program DRAM timings |
| 2044 | program_timings(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2045 | printk(BIOS_DEBUG, "Done timings\n"); |
| 2046 | |
| 2047 | // Program DLL |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2048 | program_dll(s); |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 2049 | if (!fast_boot) |
| 2050 | select_default_dq_dqs_settings(s); |
| 2051 | set_all_dq_dqs_dll_settings(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2052 | |
| 2053 | // RCOMP |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2054 | if (s->boot_path != BOOT_PATH_WARM_RESET) { |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2055 | prog_rcomp(s); |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2056 | printk(BIOS_DEBUG, "RCOMP\n"); |
| 2057 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2058 | |
| 2059 | // ODT |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2060 | program_odt(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2061 | printk(BIOS_DEBUG, "Done ODT\n"); |
| 2062 | |
| 2063 | // RCOMP update |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2064 | if (s->boot_path != BOOT_PATH_WARM_RESET) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2065 | while (MCHBAR8(0x130) & 1) |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2066 | ; |
| 2067 | printk(BIOS_DEBUG, "Done RCOMP update\n"); |
| 2068 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2069 | |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 2070 | pre_jedec_memory_map(); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2071 | |
| 2072 | // IOBUFACT |
| 2073 | if (CHANNEL_IS_POPULATED(s->dimms, 0)) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2074 | MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f); |
| 2075 | MCHBAR8_OR(0x5d8, 0x7); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2076 | } |
| 2077 | if (CHANNEL_IS_POPULATED(s->dimms, 1)) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 2078 | if (pci_read_config8(PCI_DEV(0, 0, 0), 0x8) < 2) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2079 | MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f); |
| 2080 | MCHBAR8_OR(0x5d8, 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2081 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2082 | MCHBAR8_OR(0x9dd, 0x3f); |
| 2083 | MCHBAR8_OR(0x9d8, 0x7); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2084 | } |
| 2085 | |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 2086 | /* DDR3 reset */ |
| 2087 | if ((s->spd_type == DDR3) && (s->boot_path != BOOT_PATH_RESUME)) { |
| 2088 | printk(BIOS_DEBUG, "DDR3 Reset.\n"); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2089 | MCHBAR8_AND(0x1a8, ~0x2); |
| 2090 | MCHBAR8_OR(0x5da, 0x80); |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 2091 | udelay(500); |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2092 | MCHBAR8_AND(0x1a8, ~0x2); |
| 2093 | MCHBAR8_AND(0x5da, ~0x80); |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 2094 | udelay(500); |
| 2095 | } |
| 2096 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2097 | // Pre jedec |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2098 | MCHBAR8_OR(0x40, 0x2); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2099 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2100 | MCHBAR32_OR(0x400*ch + 0x260, 1 << 27); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2101 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2102 | MCHBAR16_OR(0x212, 0xf000); |
| 2103 | MCHBAR16_OR(0x212, 0xf00); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2104 | printk(BIOS_DEBUG, "Done pre-jedec\n"); |
| 2105 | |
| 2106 | // JEDEC reset |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 2107 | if (s->boot_path != BOOT_PATH_RESUME) { |
| 2108 | if (s->spd_type == DDR2) |
| 2109 | jedec_ddr2(s); |
| 2110 | else /* DDR3 */ |
| 2111 | jedec_ddr3(s); |
| 2112 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2113 | |
| 2114 | printk(BIOS_DEBUG, "Done jedec steps\n"); |
| 2115 | |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 2116 | if (s->spd_type == DDR3) { |
| 2117 | if (!fast_boot) |
| 2118 | search_write_leveling(s); |
| 2119 | if (s->boot_path == BOOT_PATH_NORMAL) |
| 2120 | software_ddr3_reset(s); |
| 2121 | } |
| 2122 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2123 | // After JEDEC reset |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2124 | MCHBAR8_AND(0x40, ~0x2); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2125 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Arthur Heymans | 0d28495 | 2017-05-25 19:55:52 +0200 | [diff] [blame] | 2126 | reg32 = (2 << 18); |
| 2127 | reg32 |= post_jedec_tab[s->selected_timings.fsb_clk] |
| 2128 | [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][0] |
| 2129 | << 13; |
| 2130 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz && |
| 2131 | s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz && |
| 2132 | ch == 1) { |
| 2133 | reg32 |= (post_jedec_tab[s->selected_timings.fsb_clk] |
| 2134 | [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] |
| 2135 | - 1) << 8; |
| 2136 | } else { |
| 2137 | reg32 |= post_jedec_tab[s->selected_timings.fsb_clk] |
| 2138 | [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] |
| 2139 | << 8; |
| 2140 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2141 | MCHBAR32_AND_OR(0x400*ch + 0x274, ~0xfff00, reg32); |
| 2142 | MCHBAR8_AND(0x400*ch + 0x274, ~0x80); |
| 2143 | MCHBAR8_OR(0x400*ch + 0x26c, 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2144 | MCHBAR32(0x400*ch + 0x278) = 0x88141881; |
| 2145 | MCHBAR16(0x400*ch + 0x27c) = 0x41; |
| 2146 | MCHBAR8(0x400*ch + 0x292) = 0xf2; |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2147 | MCHBAR8_OR(0x400*ch + 0x271, 0xe); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2148 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2149 | MCHBAR8_OR(0x2c4, 0x8); |
| 2150 | MCHBAR8_OR(0x2c3, 0x40); |
| 2151 | MCHBAR8_OR(0x2c4, 0x4); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2152 | |
| 2153 | printk(BIOS_DEBUG, "Done post-jedec\n"); |
| 2154 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2155 | // Set DDR init complete |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2156 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2157 | MCHBAR32_OR(0x400*ch + 0x268, 0xc0000000); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2158 | } |
| 2159 | |
| 2160 | // Receive enable |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 2161 | sdram_program_receive_enable(s, fast_boot); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2162 | printk(BIOS_DEBUG, "Done rcven\n"); |
| 2163 | |
| 2164 | // Finish rcven |
| 2165 | FOR_EACH_CHANNEL(ch) { |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2166 | MCHBAR8_AND(0x400*ch + 0x5d8, ~0xe); |
| 2167 | MCHBAR8_OR(0x400*ch + 0x5d8, 0x2); |
| 2168 | MCHBAR8_OR(0x400*ch + 0x5d8, 0x4); |
| 2169 | MCHBAR8_OR(0x400*ch + 0x5d8, 0x8); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2170 | } |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2171 | MCHBAR8_OR(0x5dc, 0x80); |
| 2172 | MCHBAR8_AND(0x5dc, ~0x80); |
| 2173 | MCHBAR8_OR(0x5dc, 0x80); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2174 | |
| 2175 | // Dummy writes / reads |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2176 | if (s->boot_path == BOOT_PATH_NORMAL) { |
| 2177 | volatile u32 data; |
| 2178 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
| 2179 | for (bank = 0; bank < 4; bank++) { |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 2180 | reg32 = test_address(ch, r) | |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 2181 | (bank << 12); |
| 2182 | write32((u32 *)reg32, 0xffffffff); |
| 2183 | data = read32((u32 *)reg32); |
| 2184 | printk(BIOS_DEBUG, "Wrote ones,"); |
| 2185 | printk(BIOS_DEBUG, " Read: [0x%08x]=0x%08x\n", |
| 2186 | reg32, data); |
| 2187 | write32((u32 *)reg32, 0x00000000); |
| 2188 | data = read32((u32 *)reg32); |
| 2189 | printk(BIOS_DEBUG, "Wrote zeros,"); |
| 2190 | printk(BIOS_DEBUG, " Read: [0x%08x]=0x%08x\n", |
| 2191 | reg32, data); |
| 2192 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2193 | } |
| 2194 | } |
| 2195 | printk(BIOS_DEBUG, "Done dummy reads\n"); |
| 2196 | |
| 2197 | // XXX tRD |
| 2198 | |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 2199 | if (!fast_boot) { |
| 2200 | if (s->selected_timings.mem_clk > MEM_CLOCK_667MHz) { |
| 2201 | if(do_write_training(s)) |
| 2202 | die("DQ write training failed!"); |
| 2203 | } |
| 2204 | if (do_read_training(s)) |
| 2205 | die("DQS read training failed!"); |
| 2206 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2207 | |
| 2208 | // DRADRB |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2209 | set_dradrb(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2210 | printk(BIOS_DEBUG, "Done DRADRB\n"); |
| 2211 | |
| 2212 | // Memory map |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2213 | configure_mmap(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2214 | printk(BIOS_DEBUG, "Done memory map\n"); |
| 2215 | |
| 2216 | // Enhanced mode |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2217 | set_enhanced_mode(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2218 | printk(BIOS_DEBUG, "Done enhanced mode\n"); |
| 2219 | |
| 2220 | // Periodic RCOMP |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2221 | MCHBAR16_AND_OR(0x160, ~0xfff, 0x999); |
| 2222 | MCHBAR16_OR(0x1b4, 0x3000); |
| 2223 | MCHBAR8_OR(0x130, 0x82); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2224 | printk(BIOS_DEBUG, "Done PRCOMP\n"); |
| 2225 | |
| 2226 | // Power settings |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2227 | power_settings(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2228 | printk(BIOS_DEBUG, "Done power settings\n"); |
| 2229 | |
| 2230 | // ME related |
Arthur Heymans | ddc8828 | 2017-02-27 16:27:21 +0100 | [diff] [blame] | 2231 | /* |
| 2232 | * FIXME: This locks some registers like bit1 of GGC |
| 2233 | * and is only needed in case of ME being used. |
| 2234 | */ |
| 2235 | if (ME_UMA_SIZEMB != 0) { |
| 2236 | if (RANK_IS_POPULATED(s->dimms, 0, 0) |
| 2237 | || RANK_IS_POPULATED(s->dimms, 1, 0)) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2238 | MCHBAR8_OR(0xa2f, 1 << 0); |
Arthur Heymans | ddc8828 | 2017-02-27 16:27:21 +0100 | [diff] [blame] | 2239 | if (RANK_IS_POPULATED(s->dimms, 0, 1) |
| 2240 | || RANK_IS_POPULATED(s->dimms, 1, 1)) |
Felix Held | 432575c | 2018-07-29 18:09:30 +0200 | [diff] [blame] | 2241 | MCHBAR8_OR(0xa2f, 1 << 1); |
| 2242 | MCHBAR32_OR(0xa30, 1 << 26); |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 2243 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2244 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 2245 | printk(BIOS_DEBUG, "Done raminit\n"); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2246 | } |